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pci.c
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linux-6.19.14/arch/powerpc/platforms/powernv/pci.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Support PCI/PCIe on PowerNV platforms 4 * 5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 6 */ 7 8#include <linux/kernel.h> 9#include <linux/pci.h> 10#include <linux/delay.h> 11#include <linux/string.h> 12#include <linux/init.h> 13#include <linux/irq.h> 14#include <linux/io.h> 15#include <linux/msi.h> 16#include <linux/iommu.h> 17 18#include <asm/sections.h> 19#include <asm/io.h> 20#include <asm/pci-bridge.h> 21#include <asm/machdep.h> 22#include <asm/msi_bitmap.h> 23#include <asm/ppc-pci.h> 24#include <asm/pnv-pci.h> 25#include <asm/opal.h> 26#include <asm/iommu.h> 27#include <asm/tce.h> 28#include <asm/firmware.h> 29#include <asm/eeh_event.h> 30#include <asm/eeh.h> 31 32#include "powernv.h" 33#include "pci.h" 34 35int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id) 36{ 37 struct device_node *node = np; 38 u32 bdfn; 39 u64 phbid; 40 int ret; 41 42 ret = of_property_read_u32(np, "reg", &bdfn); 43 if (ret) 44 return -ENXIO; 45 46 bdfn = ((bdfn & 0x00ffff00) >> 8); 47 for (node = np; node; node = of_get_parent(node)) { 48 if (!PCI_DN(node)) { 49 of_node_put(node); 50 break; 51 } 52 53 if (!of_device_is_compatible(node, "ibm,ioda2-phb") && 54 !of_device_is_compatible(node, "ibm,ioda3-phb") && 55 !of_device_is_compatible(node, "ibm,ioda2-npu2-opencapi-phb")) { 56 of_node_put(node); 57 continue; 58 } 59 60 ret = of_property_read_u64(node, "ibm,opal-phbid", &phbid); 61 if (ret) { 62 of_node_put(node); 63 return -ENXIO; 64 } 65 66 if (of_device_is_compatible(node, "ibm,ioda2-npu2-opencapi-phb")) 67 *id = PCI_PHB_SLOT_ID(phbid); 68 else 69 *id = PCI_SLOT_ID(phbid, bdfn); 70 return 0; 71 } 72 73 return -ENODEV; 74} 75EXPORT_SYMBOL_GPL(pnv_pci_get_slot_id); 76 77int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len) 78{ 79 int64_t rc; 80 81 if (!opal_check_token(OPAL_GET_DEVICE_TREE)) 82 return -ENXIO; 83 84 rc = opal_get_device_tree(phandle, (uint64_t)buf, len); 85 if (rc < OPAL_SUCCESS) 86 return -EIO; 87 88 return rc; 89} 90EXPORT_SYMBOL_GPL(pnv_pci_get_device_tree); 91 92int pnv_pci_get_presence_state(uint64_t id, uint8_t *state) 93{ 94 int64_t rc; 95 96 if (!opal_check_token(OPAL_PCI_GET_PRESENCE_STATE)) 97 return -ENXIO; 98 99 rc = opal_pci_get_presence_state(id, (uint64_t)state); 100 if (rc != OPAL_SUCCESS) 101 return -EIO; 102 103 return 0; 104} 105EXPORT_SYMBOL_GPL(pnv_pci_get_presence_state); 106 107int pnv_pci_get_power_state(uint64_t id, uint8_t *state) 108{ 109 int64_t rc; 110 111 if (!opal_check_token(OPAL_PCI_GET_POWER_STATE)) 112 return -ENXIO; 113 114 rc = opal_pci_get_power_state(id, (uint64_t)state); 115 if (rc != OPAL_SUCCESS) 116 return -EIO; 117 118 return 0; 119} 120EXPORT_SYMBOL_GPL(pnv_pci_get_power_state); 121 122int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg) 123{ 124 struct opal_msg m; 125 int token, ret; 126 int64_t rc; 127 128 if (!opal_check_token(OPAL_PCI_SET_POWER_STATE)) 129 return -ENXIO; 130 131 token = opal_async_get_token_interruptible(); 132 if (unlikely(token < 0)) 133 return token; 134 135 rc = opal_pci_set_power_state(token, id, (uint64_t)&state); 136 if (rc == OPAL_SUCCESS) { 137 ret = 0; 138 goto exit; 139 } else if (rc != OPAL_ASYNC_COMPLETION) { 140 ret = -EIO; 141 goto exit; 142 } 143 144 ret = opal_async_wait_response(token, &m); 145 if (ret < 0) 146 goto exit; 147 148 if (msg) { 149 ret = 1; 150 memcpy(msg, &m, sizeof(m)); 151 } 152 153exit: 154 opal_async_release_token(token); 155 return ret; 156} 157EXPORT_SYMBOL_GPL(pnv_pci_set_power_state); 158 159/* Nicely print the contents of the PE State Tables (PEST). */ 160static void pnv_pci_dump_pest(__be64 pestA[], __be64 pestB[], int pest_size) 161{ 162 __be64 prevA = ULONG_MAX, prevB = ULONG_MAX; 163 bool dup = false; 164 int i; 165 166 for (i = 0; i < pest_size; i++) { 167 __be64 peA = be64_to_cpu(pestA[i]); 168 __be64 peB = be64_to_cpu(pestB[i]); 169 170 if (peA != prevA || peB != prevB) { 171 if (dup) { 172 pr_info("PE[..%03x] A/B: as above\n", i-1); 173 dup = false; 174 } 175 prevA = peA; 176 prevB = peB; 177 if (peA & PNV_IODA_STOPPED_STATE || 178 peB & PNV_IODA_STOPPED_STATE) 179 pr_info("PE[%03x] A/B: %016llx %016llx\n", 180 i, peA, peB); 181 } else if (!dup && (peA & PNV_IODA_STOPPED_STATE || 182 peB & PNV_IODA_STOPPED_STATE)) { 183 dup = true; 184 } 185 } 186} 187 188static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, 189 struct OpalIoPhbErrorCommon *common) 190{ 191 struct OpalIoP7IOCPhbErrorData *data; 192 193 data = (struct OpalIoP7IOCPhbErrorData *)common; 194 pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n", 195 hose->global_number, be32_to_cpu(common->version)); 196 197 if (data->brdgCtl) 198 pr_info("brdgCtl: %08x\n", 199 be32_to_cpu(data->brdgCtl)); 200 if (data->portStatusReg || data->rootCmplxStatus || 201 data->busAgentStatus) 202 pr_info("UtlSts: %08x %08x %08x\n", 203 be32_to_cpu(data->portStatusReg), 204 be32_to_cpu(data->rootCmplxStatus), 205 be32_to_cpu(data->busAgentStatus)); 206 if (data->deviceStatus || data->slotStatus || 207 data->linkStatus || data->devCmdStatus || 208 data->devSecStatus) 209 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 210 be32_to_cpu(data->deviceStatus), 211 be32_to_cpu(data->slotStatus), 212 be32_to_cpu(data->linkStatus), 213 be32_to_cpu(data->devCmdStatus), 214 be32_to_cpu(data->devSecStatus)); 215 if (data->rootErrorStatus || data->uncorrErrorStatus || 216 data->corrErrorStatus) 217 pr_info("RootErrSts: %08x %08x %08x\n", 218 be32_to_cpu(data->rootErrorStatus), 219 be32_to_cpu(data->uncorrErrorStatus), 220 be32_to_cpu(data->corrErrorStatus)); 221 if (data->tlpHdr1 || data->tlpHdr2 || 222 data->tlpHdr3 || data->tlpHdr4) 223 pr_info("RootErrLog: %08x %08x %08x %08x\n", 224 be32_to_cpu(data->tlpHdr1), 225 be32_to_cpu(data->tlpHdr2), 226 be32_to_cpu(data->tlpHdr3), 227 be32_to_cpu(data->tlpHdr4)); 228 if (data->sourceId || data->errorClass || 229 data->correlator) 230 pr_info("RootErrLog1: %08x %016llx %016llx\n", 231 be32_to_cpu(data->sourceId), 232 be64_to_cpu(data->errorClass), 233 be64_to_cpu(data->correlator)); 234 if (data->p7iocPlssr || data->p7iocCsr) 235 pr_info("PhbSts: %016llx %016llx\n", 236 be64_to_cpu(data->p7iocPlssr), 237 be64_to_cpu(data->p7iocCsr)); 238 if (data->lemFir) 239 pr_info("Lem: %016llx %016llx %016llx\n", 240 be64_to_cpu(data->lemFir), 241 be64_to_cpu(data->lemErrorMask), 242 be64_to_cpu(data->lemWOF)); 243 if (data->phbErrorStatus) 244 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 245 be64_to_cpu(data->phbErrorStatus), 246 be64_to_cpu(data->phbFirstErrorStatus), 247 be64_to_cpu(data->phbErrorLog0), 248 be64_to_cpu(data->phbErrorLog1)); 249 if (data->mmioErrorStatus) 250 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 251 be64_to_cpu(data->mmioErrorStatus), 252 be64_to_cpu(data->mmioFirstErrorStatus), 253 be64_to_cpu(data->mmioErrorLog0), 254 be64_to_cpu(data->mmioErrorLog1)); 255 if (data->dma0ErrorStatus) 256 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 257 be64_to_cpu(data->dma0ErrorStatus), 258 be64_to_cpu(data->dma0FirstErrorStatus), 259 be64_to_cpu(data->dma0ErrorLog0), 260 be64_to_cpu(data->dma0ErrorLog1)); 261 if (data->dma1ErrorStatus) 262 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 263 be64_to_cpu(data->dma1ErrorStatus), 264 be64_to_cpu(data->dma1FirstErrorStatus), 265 be64_to_cpu(data->dma1ErrorLog0), 266 be64_to_cpu(data->dma1ErrorLog1)); 267 268 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_P7IOC_NUM_PEST_REGS); 269} 270 271static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, 272 struct OpalIoPhbErrorCommon *common) 273{ 274 struct OpalIoPhb3ErrorData *data; 275 276 data = (struct OpalIoPhb3ErrorData*)common; 277 pr_info("PHB3 PHB#%x Diag-data (Version: %d)\n", 278 hose->global_number, be32_to_cpu(common->version)); 279 if (data->brdgCtl) 280 pr_info("brdgCtl: %08x\n", 281 be32_to_cpu(data->brdgCtl)); 282 if (data->portStatusReg || data->rootCmplxStatus || 283 data->busAgentStatus) 284 pr_info("UtlSts: %08x %08x %08x\n", 285 be32_to_cpu(data->portStatusReg), 286 be32_to_cpu(data->rootCmplxStatus), 287 be32_to_cpu(data->busAgentStatus)); 288 if (data->deviceStatus || data->slotStatus || 289 data->linkStatus || data->devCmdStatus || 290 data->devSecStatus) 291 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 292 be32_to_cpu(data->deviceStatus), 293 be32_to_cpu(data->slotStatus), 294 be32_to_cpu(data->linkStatus), 295 be32_to_cpu(data->devCmdStatus), 296 be32_to_cpu(data->devSecStatus)); 297 if (data->rootErrorStatus || data->uncorrErrorStatus || 298 data->corrErrorStatus) 299 pr_info("RootErrSts: %08x %08x %08x\n", 300 be32_to_cpu(data->rootErrorStatus), 301 be32_to_cpu(data->uncorrErrorStatus), 302 be32_to_cpu(data->corrErrorStatus)); 303 if (data->tlpHdr1 || data->tlpHdr2 || 304 data->tlpHdr3 || data->tlpHdr4) 305 pr_info("RootErrLog: %08x %08x %08x %08x\n", 306 be32_to_cpu(data->tlpHdr1), 307 be32_to_cpu(data->tlpHdr2), 308 be32_to_cpu(data->tlpHdr3), 309 be32_to_cpu(data->tlpHdr4)); 310 if (data->sourceId || data->errorClass || 311 data->correlator) 312 pr_info("RootErrLog1: %08x %016llx %016llx\n", 313 be32_to_cpu(data->sourceId), 314 be64_to_cpu(data->errorClass), 315 be64_to_cpu(data->correlator)); 316 if (data->nFir) 317 pr_info("nFir: %016llx %016llx %016llx\n", 318 be64_to_cpu(data->nFir), 319 be64_to_cpu(data->nFirMask), 320 be64_to_cpu(data->nFirWOF)); 321 if (data->phbPlssr || data->phbCsr) 322 pr_info("PhbSts: %016llx %016llx\n", 323 be64_to_cpu(data->phbPlssr), 324 be64_to_cpu(data->phbCsr)); 325 if (data->lemFir) 326 pr_info("Lem: %016llx %016llx %016llx\n", 327 be64_to_cpu(data->lemFir), 328 be64_to_cpu(data->lemErrorMask), 329 be64_to_cpu(data->lemWOF)); 330 if (data->phbErrorStatus) 331 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 332 be64_to_cpu(data->phbErrorStatus), 333 be64_to_cpu(data->phbFirstErrorStatus), 334 be64_to_cpu(data->phbErrorLog0), 335 be64_to_cpu(data->phbErrorLog1)); 336 if (data->mmioErrorStatus) 337 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 338 be64_to_cpu(data->mmioErrorStatus), 339 be64_to_cpu(data->mmioFirstErrorStatus), 340 be64_to_cpu(data->mmioErrorLog0), 341 be64_to_cpu(data->mmioErrorLog1)); 342 if (data->dma0ErrorStatus) 343 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 344 be64_to_cpu(data->dma0ErrorStatus), 345 be64_to_cpu(data->dma0FirstErrorStatus), 346 be64_to_cpu(data->dma0ErrorLog0), 347 be64_to_cpu(data->dma0ErrorLog1)); 348 if (data->dma1ErrorStatus) 349 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 350 be64_to_cpu(data->dma1ErrorStatus), 351 be64_to_cpu(data->dma1FirstErrorStatus), 352 be64_to_cpu(data->dma1ErrorLog0), 353 be64_to_cpu(data->dma1ErrorLog1)); 354 355 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB3_NUM_PEST_REGS); 356} 357 358static void pnv_pci_dump_phb4_diag_data(struct pci_controller *hose, 359 struct OpalIoPhbErrorCommon *common) 360{ 361 struct OpalIoPhb4ErrorData *data; 362 363 data = (struct OpalIoPhb4ErrorData*)common; 364 pr_info("PHB4 PHB#%d Diag-data (Version: %d)\n", 365 hose->global_number, be32_to_cpu(common->version)); 366 if (data->brdgCtl) 367 pr_info("brdgCtl: %08x\n", 368 be32_to_cpu(data->brdgCtl)); 369 if (data->deviceStatus || data->slotStatus || 370 data->linkStatus || data->devCmdStatus || 371 data->devSecStatus) 372 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 373 be32_to_cpu(data->deviceStatus), 374 be32_to_cpu(data->slotStatus), 375 be32_to_cpu(data->linkStatus), 376 be32_to_cpu(data->devCmdStatus), 377 be32_to_cpu(data->devSecStatus)); 378 if (data->rootErrorStatus || data->uncorrErrorStatus || 379 data->corrErrorStatus) 380 pr_info("RootErrSts: %08x %08x %08x\n", 381 be32_to_cpu(data->rootErrorStatus), 382 be32_to_cpu(data->uncorrErrorStatus), 383 be32_to_cpu(data->corrErrorStatus)); 384 if (data->tlpHdr1 || data->tlpHdr2 || 385 data->tlpHdr3 || data->tlpHdr4) 386 pr_info("RootErrLog: %08x %08x %08x %08x\n", 387 be32_to_cpu(data->tlpHdr1), 388 be32_to_cpu(data->tlpHdr2), 389 be32_to_cpu(data->tlpHdr3), 390 be32_to_cpu(data->tlpHdr4)); 391 if (data->sourceId) 392 pr_info("sourceId: %08x\n", be32_to_cpu(data->sourceId)); 393 if (data->nFir) 394 pr_info("nFir: %016llx %016llx %016llx\n", 395 be64_to_cpu(data->nFir), 396 be64_to_cpu(data->nFirMask), 397 be64_to_cpu(data->nFirWOF)); 398 if (data->phbPlssr || data->phbCsr) 399 pr_info("PhbSts: %016llx %016llx\n", 400 be64_to_cpu(data->phbPlssr), 401 be64_to_cpu(data->phbCsr)); 402 if (data->lemFir) 403 pr_info("Lem: %016llx %016llx %016llx\n", 404 be64_to_cpu(data->lemFir), 405 be64_to_cpu(data->lemErrorMask), 406 be64_to_cpu(data->lemWOF)); 407 if (data->phbErrorStatus) 408 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 409 be64_to_cpu(data->phbErrorStatus), 410 be64_to_cpu(data->phbFirstErrorStatus), 411 be64_to_cpu(data->phbErrorLog0), 412 be64_to_cpu(data->phbErrorLog1)); 413 if (data->phbTxeErrorStatus) 414 pr_info("PhbTxeErr: %016llx %016llx %016llx %016llx\n", 415 be64_to_cpu(data->phbTxeErrorStatus), 416 be64_to_cpu(data->phbTxeFirstErrorStatus), 417 be64_to_cpu(data->phbTxeErrorLog0), 418 be64_to_cpu(data->phbTxeErrorLog1)); 419 if (data->phbRxeArbErrorStatus) 420 pr_info("RxeArbErr: %016llx %016llx %016llx %016llx\n", 421 be64_to_cpu(data->phbRxeArbErrorStatus), 422 be64_to_cpu(data->phbRxeArbFirstErrorStatus), 423 be64_to_cpu(data->phbRxeArbErrorLog0), 424 be64_to_cpu(data->phbRxeArbErrorLog1)); 425 if (data->phbRxeMrgErrorStatus) 426 pr_info("RxeMrgErr: %016llx %016llx %016llx %016llx\n", 427 be64_to_cpu(data->phbRxeMrgErrorStatus), 428 be64_to_cpu(data->phbRxeMrgFirstErrorStatus), 429 be64_to_cpu(data->phbRxeMrgErrorLog0), 430 be64_to_cpu(data->phbRxeMrgErrorLog1)); 431 if (data->phbRxeTceErrorStatus) 432 pr_info("RxeTceErr: %016llx %016llx %016llx %016llx\n", 433 be64_to_cpu(data->phbRxeTceErrorStatus), 434 be64_to_cpu(data->phbRxeTceFirstErrorStatus), 435 be64_to_cpu(data->phbRxeTceErrorLog0), 436 be64_to_cpu(data->phbRxeTceErrorLog1)); 437 438 if (data->phbPblErrorStatus) 439 pr_info("PblErr: %016llx %016llx %016llx %016llx\n", 440 be64_to_cpu(data->phbPblErrorStatus), 441 be64_to_cpu(data->phbPblFirstErrorStatus), 442 be64_to_cpu(data->phbPblErrorLog0), 443 be64_to_cpu(data->phbPblErrorLog1)); 444 if (data->phbPcieDlpErrorStatus) 445 pr_info("PcieDlp: %016llx %016llx %016llx\n", 446 be64_to_cpu(data->phbPcieDlpErrorLog1), 447 be64_to_cpu(data->phbPcieDlpErrorLog2), 448 be64_to_cpu(data->phbPcieDlpErrorStatus)); 449 if (data->phbRegbErrorStatus) 450 pr_info("RegbErr: %016llx %016llx %016llx %016llx\n", 451 be64_to_cpu(data->phbRegbErrorStatus), 452 be64_to_cpu(data->phbRegbFirstErrorStatus), 453 be64_to_cpu(data->phbRegbErrorLog0), 454 be64_to_cpu(data->phbRegbErrorLog1)); 455 456 457 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB4_NUM_PEST_REGS); 458} 459 460void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 461 unsigned char *log_buff) 462{ 463 struct OpalIoPhbErrorCommon *common; 464 465 if (!hose || !log_buff) 466 return; 467 468 common = (struct OpalIoPhbErrorCommon *)log_buff; 469 switch (be32_to_cpu(common->ioType)) { 470 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: 471 pnv_pci_dump_p7ioc_diag_data(hose, common); 472 break; 473 case OPAL_PHB_ERROR_DATA_TYPE_PHB3: 474 pnv_pci_dump_phb3_diag_data(hose, common); 475 break; 476 case OPAL_PHB_ERROR_DATA_TYPE_PHB4: 477 pnv_pci_dump_phb4_diag_data(hose, common); 478 break; 479 default: 480 pr_warn("%s: Unrecognized ioType %d\n", 481 __func__, be32_to_cpu(common->ioType)); 482 } 483} 484 485static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 486{ 487 unsigned long flags, rc; 488 int has_diag, ret = 0; 489 490 spin_lock_irqsave(&phb->lock, flags); 491 492 /* Fetch PHB diag-data */ 493 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 494 phb->diag_data_size); 495 has_diag = (rc == OPAL_SUCCESS); 496 497 /* If PHB supports compound PE, to handle it */ 498 if (phb->unfreeze_pe) { 499 ret = phb->unfreeze_pe(phb, 500 pe_no, 501 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 502 } else { 503 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 504 pe_no, 505 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 506 if (rc) { 507 pr_warn("%s: Failure %ld clearing frozen " 508 "PHB#%x-PE#%x\n", 509 __func__, rc, phb->hose->global_number, 510 pe_no); 511 ret = -EIO; 512 } 513 } 514 515 /* 516 * For now, let's only display the diag buffer when we fail to clear 517 * the EEH status. We'll do more sensible things later when we have 518 * proper EEH support. We need to make sure we don't pollute ourselves 519 * with the normal errors generated when probing empty slots 520 */ 521 if (has_diag && ret) 522 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 523 524 spin_unlock_irqrestore(&phb->lock, flags); 525} 526 527static void pnv_pci_config_check_eeh(struct pci_dn *pdn) 528{ 529 struct pnv_phb *phb = pdn->phb->private_data; 530 u8 fstate = 0; 531 __be16 pcierr = 0; 532 unsigned int pe_no; 533 s64 rc; 534 535 /* 536 * Get the PE#. During the PCI probe stage, we might not 537 * setup that yet. So all ER errors should be mapped to 538 * reserved PE. 539 */ 540 pe_no = pdn->pe_number; 541 if (pe_no == IODA_INVALID_PE) { 542 pe_no = phb->ioda.reserved_pe_idx; 543 } 544 545 /* 546 * Fetch frozen state. If the PHB support compound PE, 547 * we need handle that case. 548 */ 549 if (phb->get_pe_state) { 550 fstate = phb->get_pe_state(phb, pe_no); 551 } else { 552 rc = opal_pci_eeh_freeze_status(phb->opal_id, 553 pe_no, 554 &fstate, 555 &pcierr, 556 NULL); 557 if (rc) { 558 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", 559 __func__, rc, phb->hose->global_number, pe_no); 560 return; 561 } 562 } 563 564 pr_devel(" -> EEH check, bdfn=%04x PE#%x fstate=%x\n", 565 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate); 566 567 /* Clear the frozen state if applicable */ 568 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || 569 fstate == OPAL_EEH_STOPPED_DMA_FREEZE || 570 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { 571 /* 572 * If PHB supports compound PE, freeze it for 573 * consistency. 574 */ 575 if (phb->freeze_pe) 576 phb->freeze_pe(phb, pe_no); 577 578 pnv_pci_handle_eeh_config(phb, pe_no); 579 } 580} 581 582int pnv_pci_cfg_read(struct pci_dn *pdn, 583 int where, int size, u32 *val) 584{ 585 struct pnv_phb *phb = pdn->phb->private_data; 586 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 587 s64 rc; 588 589 switch (size) { 590 case 1: { 591 u8 v8; 592 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 593 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 594 break; 595 } 596 case 2: { 597 __be16 v16; 598 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 599 &v16); 600 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; 601 break; 602 } 603 case 4: { 604 __be32 v32; 605 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 606 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; 607 break; 608 } 609 default: 610 return PCIBIOS_FUNC_NOT_SUPPORTED; 611 } 612 613 pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 614 __func__, pdn->busno, pdn->devfn, where, size, *val); 615 return PCIBIOS_SUCCESSFUL; 616} 617 618int pnv_pci_cfg_write(struct pci_dn *pdn, 619 int where, int size, u32 val) 620{ 621 struct pnv_phb *phb = pdn->phb->private_data; 622 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 623 624 pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 625 __func__, pdn->busno, pdn->devfn, where, size, val); 626 switch (size) { 627 case 1: 628 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 629 break; 630 case 2: 631 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 632 break; 633 case 4: 634 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 635 break; 636 default: 637 return PCIBIOS_FUNC_NOT_SUPPORTED; 638 } 639 640 return PCIBIOS_SUCCESSFUL; 641} 642 643#ifdef CONFIG_EEH 644static bool pnv_pci_cfg_check(struct pci_dn *pdn) 645{ 646 struct eeh_dev *edev = NULL; 647 struct pnv_phb *phb = pdn->phb->private_data; 648 649 /* EEH not enabled ? */ 650 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 651 return true; 652 653 /* PE reset or device removed ? */ 654 edev = pdn->edev; 655 if (edev) { 656 if (edev->pe && 657 (edev->pe->state & EEH_PE_CFG_BLOCKED)) 658 return false; 659 660 if (edev->mode & EEH_DEV_REMOVED) 661 return false; 662 } 663 664 return true; 665} 666#else 667static inline pnv_pci_cfg_check(struct pci_dn *pdn) 668{ 669 return true; 670} 671#endif /* CONFIG_EEH */ 672 673static int pnv_pci_read_config(struct pci_bus *bus, 674 unsigned int devfn, 675 int where, int size, u32 *val) 676{ 677 struct pci_dn *pdn; 678 struct pnv_phb *phb; 679 int ret; 680 681 *val = 0xFFFFFFFF; 682 pdn = pci_get_pdn_by_devfn(bus, devfn); 683 if (!pdn) 684 return PCIBIOS_DEVICE_NOT_FOUND; 685 686 if (!pnv_pci_cfg_check(pdn)) 687 return PCIBIOS_DEVICE_NOT_FOUND; 688 689 ret = pnv_pci_cfg_read(pdn, where, size, val); 690 phb = pdn->phb->private_data; 691 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { 692 if (*val == EEH_IO_ERROR_VALUE(size) && 693 eeh_dev_check_failure(pdn->edev)) 694 return PCIBIOS_DEVICE_NOT_FOUND; 695 } else { 696 pnv_pci_config_check_eeh(pdn); 697 } 698 699 return ret; 700} 701 702static int pnv_pci_write_config(struct pci_bus *bus, 703 unsigned int devfn, 704 int where, int size, u32 val) 705{ 706 struct pci_dn *pdn; 707 struct pnv_phb *phb; 708 int ret; 709 710 pdn = pci_get_pdn_by_devfn(bus, devfn); 711 if (!pdn) 712 return PCIBIOS_DEVICE_NOT_FOUND; 713 714 if (!pnv_pci_cfg_check(pdn)) 715 return PCIBIOS_DEVICE_NOT_FOUND; 716 717 ret = pnv_pci_cfg_write(pdn, where, size, val); 718 phb = pdn->phb->private_data; 719 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 720 pnv_pci_config_check_eeh(pdn); 721 722 return ret; 723} 724 725struct pci_ops pnv_pci_ops = { 726 .read = pnv_pci_read_config, 727 .write = pnv_pci_write_config, 728}; 729 730struct iommu_table *pnv_pci_table_alloc(int nid) 731{ 732 struct iommu_table *tbl; 733 734 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid); 735 if (!tbl) 736 return NULL; 737 738 INIT_LIST_HEAD_RCU(&tbl->it_group_list); 739 kref_init(&tbl->it_kref); 740 741 return tbl; 742} 743 744void pnv_pci_shutdown(void) 745{ 746 struct pci_controller *hose; 747 748 list_for_each_entry(hose, &hose_list, list_node) 749 if (hose->controller_ops.shutdown) 750 hose->controller_ops.shutdown(hose); 751} 752 753/* Fixup wrong class code in p7ioc and p8 root complex */ 754static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) 755{ 756 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 757} 758DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 759 760void __init pnv_pci_init(void) 761{ 762 struct device_node *np; 763 764 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 765 766 /* If we don't have OPAL, eg. in sim, just skip PCI probe */ 767 if (!firmware_has_feature(FW_FEATURE_OPAL)) 768 return; 769 770#ifdef CONFIG_PCIEPORTBUS 771 /* 772 * On PowerNV PCIe devices are (currently) managed in cooperation 773 * with firmware. This isn't *strictly* required, but there's enough 774 * assumptions baked into both firmware and the platform code that 775 * it's unwise to allow the portbus services to be used. 776 * 777 * We need to fix this eventually, but for now set this flag to disable 778 * the portbus driver. The AER service isn't required since that AER 779 * events are handled via EEH. The pciehp hotplug driver can't work 780 * without kernel changes (and portbus binding breaks pnv_php). The 781 * other services also require some thinking about how we're going 782 * to integrate them. 783 */ 784 pcie_ports_disabled = true; 785#endif 786 787 /* Look for ioda2 built-in PHB3's */ 788 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 789 pnv_pci_init_ioda2_phb(np); 790 791 /* Look for ioda3 built-in PHB4's, we treat them as IODA2 */ 792 for_each_compatible_node(np, NULL, "ibm,ioda3-phb") 793 pnv_pci_init_ioda2_phb(np); 794 795 /* Look for NPU2 OpenCAPI PHBs */ 796 for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-opencapi-phb") 797 pnv_pci_init_npu2_opencapi_phb(np); 798 799 /* Configure IOMMU DMA hooks */ 800 set_pci_dma_ops(&dma_iommu_ops); 801}
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