pci-ioda.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Support PCI/PCIe on PowerNV platforms
   4 *
   5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   6 */
   7
   8#undef DEBUG
   9
  10#include <linux/kernel.h>
  11#include <linux/pci.h>
  12#include <linux/crash_dump.h>
  13#include <linux/delay.h>
  14#include <linux/string.h>
  15#include <linux/init.h>
  16#include <linux/memblock.h>
  17#include <linux/irq.h>
  18#include <linux/irqchip/irq-msi-lib.h>
  19#include <linux/io.h>
  20#include <linux/msi.h>
  21#include <linux/iommu.h>
  22#include <linux/rculist.h>
  23#include <linux/sizes.h>
  24#include <linux/debugfs.h>
  25#include <linux/of_address.h>
  26#include <linux/of_irq.h>
  27
  28#include <asm/sections.h>
  29#include <asm/io.h>
  30#include <asm/pci-bridge.h>
  31#include <asm/machdep.h>
  32#include <asm/msi_bitmap.h>
  33#include <asm/ppc-pci.h>
  34#include <asm/opal.h>
  35#include <asm/iommu.h>
  36#include <asm/tce.h>
  37#include <asm/xics.h>
  38#include <asm/firmware.h>
  39#include <asm/pnv-pci.h>
  40#include <asm/mmzone.h>
  41
  42#include "powernv.h"
  43#include "pci.h"
  44#include "../../../../drivers/pci/pci.h"
  45
  46/* This array is indexed with enum pnv_phb_type */
  47static const char * const pnv_phb_names[] = { "IODA2", "NPU_OCAPI" };
  48
  49static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
  50static void pnv_pci_configure_bus(struct pci_bus *bus);
  51
  52void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  53			    const char *fmt, ...)
  54{
  55	struct va_format vaf;
  56	va_list args;
  57	char pfix[32];
  58
  59	va_start(args, fmt);
  60
  61	vaf.fmt = fmt;
  62	vaf.va = &args;
  63
  64	if (pe->flags & PNV_IODA_PE_DEV)
  65		strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  66	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  67		sprintf(pfix, "%04x:%02x     ",
  68			pci_domain_nr(pe->pbus), pe->pbus->number);
  69#ifdef CONFIG_PCI_IOV
  70	else if (pe->flags & PNV_IODA_PE_VF)
  71		sprintf(pfix, "%04x:%02x:%2x.%d",
  72			pci_domain_nr(pe->parent_dev->bus),
  73			(pe->rid & 0xff00) >> 8,
  74			PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  75#endif /* CONFIG_PCI_IOV*/
  76
  77	printk("%spci %s: [PE# %.2x] %pV",
  78	       level, pfix, pe->pe_number, &vaf);
  79
  80	va_end(args);
  81}
  82
  83static bool pnv_iommu_bypass_disabled __read_mostly;
  84static bool pci_reset_phbs __read_mostly;
  85
  86static int __init iommu_setup(char *str)
  87{
  88	if (!str)
  89		return -EINVAL;
  90
  91	while (*str) {
  92		if (!strncmp(str, "nobypass", 8)) {
  93			pnv_iommu_bypass_disabled = true;
  94			pr_info("PowerNV: IOMMU bypass window disabled.\n");
  95			break;
  96		}
  97		str += strcspn(str, ",");
  98		if (*str == ',')
  99			str++;
 100	}
 101
 102	return 0;
 103}
 104early_param("iommu", iommu_setup);
 105
 106static int __init pci_reset_phbs_setup(char *str)
 107{
 108	pci_reset_phbs = true;
 109	return 0;
 110}
 111
 112early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
 113
 114static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 115{
 116	s64 rc;
 117
 118	phb->ioda.pe_array[pe_no].phb = phb;
 119	phb->ioda.pe_array[pe_no].pe_number = pe_no;
 120	phb->ioda.pe_array[pe_no].dma_setup_done = false;
 121
 122	/*
 123	 * Clear the PE frozen state as it might be put into frozen state
 124	 * in the last PCI remove path. It's not harmful to do so when the
 125	 * PE is already in unfrozen state.
 126	 */
 127	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 128				       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 129	if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 130		pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 131			__func__, rc, phb->hose->global_number, pe_no);
 132
 133	return &phb->ioda.pe_array[pe_no];
 134}
 135
 136static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 137{
 138	if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 139		pr_warn("%s: Invalid PE %x on PHB#%x\n",
 140			__func__, pe_no, phb->hose->global_number);
 141		return;
 142	}
 143
 144	mutex_lock(&phb->ioda.pe_alloc_mutex);
 145	if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 146		pr_debug("%s: PE %x was reserved on PHB#%x\n",
 147			 __func__, pe_no, phb->hose->global_number);
 148	mutex_unlock(&phb->ioda.pe_alloc_mutex);
 149
 150	pnv_ioda_init_pe(phb, pe_no);
 151}
 152
 153struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count)
 154{
 155	struct pnv_ioda_pe *ret = NULL;
 156	int run = 0, pe, i;
 157
 158	mutex_lock(&phb->ioda.pe_alloc_mutex);
 159
 160	/* scan backwards for a run of @count cleared bits */
 161	for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 162		if (test_bit(pe, phb->ioda.pe_alloc)) {
 163			run = 0;
 164			continue;
 165		}
 166
 167		run++;
 168		if (run == count)
 169			break;
 170	}
 171	if (run != count)
 172		goto out;
 173
 174	for (i = pe; i < pe + count; i++) {
 175		set_bit(i, phb->ioda.pe_alloc);
 176		pnv_ioda_init_pe(phb, i);
 177	}
 178	ret = &phb->ioda.pe_array[pe];
 179
 180out:
 181	mutex_unlock(&phb->ioda.pe_alloc_mutex);
 182	return ret;
 183}
 184
 185void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 186{
 187	struct pnv_phb *phb = pe->phb;
 188	unsigned int pe_num = pe->pe_number;
 189
 190	WARN_ON(pe->pdev);
 191	memset(pe, 0, sizeof(struct pnv_ioda_pe));
 192
 193	mutex_lock(&phb->ioda.pe_alloc_mutex);
 194	clear_bit(pe_num, phb->ioda.pe_alloc);
 195	mutex_unlock(&phb->ioda.pe_alloc_mutex);
 196}
 197
 198/* The default M64 BAR is shared by all PEs */
 199static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 200{
 201	const char *desc;
 202	struct resource *r;
 203	s64 rc;
 204
 205	/* Configure the default M64 BAR */
 206	rc = opal_pci_set_phb_mem_window(phb->opal_id,
 207					 OPAL_M64_WINDOW_TYPE,
 208					 phb->ioda.m64_bar_idx,
 209					 phb->ioda.m64_base,
 210					 0, /* unused */
 211					 phb->ioda.m64_size);
 212	if (rc != OPAL_SUCCESS) {
 213		desc = "configuring";
 214		goto fail;
 215	}
 216
 217	/* Enable the default M64 BAR */
 218	rc = opal_pci_phb_mmio_enable(phb->opal_id,
 219				      OPAL_M64_WINDOW_TYPE,
 220				      phb->ioda.m64_bar_idx,
 221				      OPAL_ENABLE_M64_SPLIT);
 222	if (rc != OPAL_SUCCESS) {
 223		desc = "enabling";
 224		goto fail;
 225	}
 226
 227	/*
 228	 * Exclude the segments for reserved and root bus PE, which
 229	 * are first or last two PEs.
 230	 */
 231	r = &phb->hose->mem_resources[1];
 232	if (phb->ioda.reserved_pe_idx == 0)
 233		r->start += (2 * phb->ioda.m64_segsize);
 234	else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 235		r->end -= (2 * phb->ioda.m64_segsize);
 236	else
 237		pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 238			phb->ioda.reserved_pe_idx);
 239
 240	return 0;
 241
 242fail:
 243	pr_warn("  Failure %lld %s M64 BAR#%d\n",
 244		rc, desc, phb->ioda.m64_bar_idx);
 245	opal_pci_phb_mmio_enable(phb->opal_id,
 246				 OPAL_M64_WINDOW_TYPE,
 247				 phb->ioda.m64_bar_idx,
 248				 OPAL_DISABLE_M64);
 249	return -EIO;
 250}
 251
 252static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 253					 unsigned long *pe_bitmap)
 254{
 255	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
 256	struct resource *r;
 257	resource_size_t base, sgsz, start, end;
 258	int segno, i;
 259
 260	base = phb->ioda.m64_base;
 261	sgsz = phb->ioda.m64_segsize;
 262	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 263		r = &pdev->resource[i];
 264		if (!r->parent || !pnv_pci_is_m64(phb, r))
 265			continue;
 266
 267		start = ALIGN_DOWN(r->start - base, sgsz);
 268		end = ALIGN(r->end - base, sgsz);
 269		for (segno = start / sgsz; segno < end / sgsz; segno++) {
 270			if (pe_bitmap)
 271				set_bit(segno, pe_bitmap);
 272			else
 273				pnv_ioda_reserve_pe(phb, segno);
 274		}
 275	}
 276}
 277
 278static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 279				    unsigned long *pe_bitmap,
 280				    bool all)
 281{
 282	struct pci_dev *pdev;
 283
 284	list_for_each_entry(pdev, &bus->devices, bus_list) {
 285		pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 286
 287		if (all && pdev->subordinate)
 288			pnv_ioda_reserve_m64_pe(pdev->subordinate,
 289						pe_bitmap, all);
 290	}
 291}
 292
 293static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 294{
 295	struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
 296	struct pnv_ioda_pe *master_pe, *pe;
 297	unsigned long size, *pe_alloc;
 298	int i;
 299
 300	/* Root bus shouldn't use M64 */
 301	if (pci_is_root_bus(bus))
 302		return NULL;
 303
 304	/* Allocate bitmap */
 305	size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 306	pe_alloc = kzalloc(size, GFP_KERNEL);
 307	if (!pe_alloc) {
 308		pr_warn("%s: Out of memory !\n",
 309			__func__);
 310		return NULL;
 311	}
 312
 313	/* Figure out reserved PE numbers by the PE */
 314	pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 315
 316	/*
 317	 * the current bus might not own M64 window and that's all
 318	 * contributed by its child buses. For the case, we needn't
 319	 * pick M64 dependent PE#.
 320	 */
 321	if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 322		kfree(pe_alloc);
 323		return NULL;
 324	}
 325
 326	/*
 327	 * Figure out the master PE and put all slave PEs to master
 328	 * PE's list to form compound PE.
 329	 */
 330	master_pe = NULL;
 331	i = -1;
 332	while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 333		phb->ioda.total_pe_num) {
 334		pe = &phb->ioda.pe_array[i];
 335
 336		phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 337		if (!master_pe) {
 338			pe->flags |= PNV_IODA_PE_MASTER;
 339			INIT_LIST_HEAD(&pe->slaves);
 340			master_pe = pe;
 341		} else {
 342			pe->flags |= PNV_IODA_PE_SLAVE;
 343			pe->master = master_pe;
 344			list_add_tail(&pe->list, &master_pe->slaves);
 345		}
 346	}
 347
 348	kfree(pe_alloc);
 349	return master_pe;
 350}
 351
 352static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 353{
 354	struct pci_controller *hose = phb->hose;
 355	struct device_node *dn = hose->dn;
 356	struct resource *res;
 357	u32 m64_range[2], i;
 358	const __be32 *r;
 359	u64 pci_addr;
 360
 361	if (phb->type != PNV_PHB_IODA2) {
 362		pr_info("  Not support M64 window\n");
 363		return;
 364	}
 365
 366	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 367		pr_info("  Firmware too old to support M64 window\n");
 368		return;
 369	}
 370
 371	r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 372	if (!r) {
 373		pr_info("  No <ibm,opal-m64-window> on %pOF\n",
 374			dn);
 375		return;
 376	}
 377
 378	/*
 379	 * Find the available M64 BAR range and pickup the last one for
 380	 * covering the whole 64-bits space. We support only one range.
 381	 */
 382	if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 383				       m64_range, 2)) {
 384		/* In absence of the property, assume 0..15 */
 385		m64_range[0] = 0;
 386		m64_range[1] = 16;
 387	}
 388	/* We only support 64 bits in our allocator */
 389	if (m64_range[1] > 63) {
 390		pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 391			__func__, m64_range[1], phb->hose->global_number);
 392		m64_range[1] = 63;
 393	}
 394	/* Empty range, no m64 */
 395	if (m64_range[1] <= m64_range[0]) {
 396		pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 397			__func__, phb->hose->global_number);
 398		return;
 399	}
 400
 401	/* Configure M64 informations */
 402	res = &hose->mem_resources[1];
 403	res->name = dn->full_name;
 404	res->start = of_translate_address(dn, r + 2);
 405	res->end = res->start + of_read_number(r + 4, 2) - 1;
 406	res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 407	pci_addr = of_read_number(r, 2);
 408	hose->mem_offset[1] = res->start - pci_addr;
 409
 410	phb->ioda.m64_size = resource_size(res);
 411	phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 412	phb->ioda.m64_base = pci_addr;
 413
 414	/* This lines up nicely with the display from processing OF ranges */
 415	pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 416		res->start, res->end, pci_addr, m64_range[0],
 417		m64_range[0] + m64_range[1] - 1);
 418
 419	/* Mark all M64 used up by default */
 420	phb->ioda.m64_bar_alloc = (unsigned long)-1;
 421
 422	/* Use last M64 BAR to cover M64 window */
 423	m64_range[1]--;
 424	phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 425
 426	pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 427
 428	/* Mark remaining ones free */
 429	for (i = m64_range[0]; i < m64_range[1]; i++)
 430		clear_bit(i, &phb->ioda.m64_bar_alloc);
 431
 432	/*
 433	 * Setup init functions for M64 based on IODA version, IODA3 uses
 434	 * the IODA2 code.
 435	 */
 436	phb->init_m64 = pnv_ioda2_init_m64;
 437}
 438
 439static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 440{
 441	struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 442	struct pnv_ioda_pe *slave;
 443	s64 rc;
 444
 445	/* Fetch master PE */
 446	if (pe->flags & PNV_IODA_PE_SLAVE) {
 447		pe = pe->master;
 448		if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 449			return;
 450
 451		pe_no = pe->pe_number;
 452	}
 453
 454	/* Freeze master PE */
 455	rc = opal_pci_eeh_freeze_set(phb->opal_id,
 456				     pe_no,
 457				     OPAL_EEH_ACTION_SET_FREEZE_ALL);
 458	if (rc != OPAL_SUCCESS) {
 459		pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 460			__func__, rc, phb->hose->global_number, pe_no);
 461		return;
 462	}
 463
 464	/* Freeze slave PEs */
 465	if (!(pe->flags & PNV_IODA_PE_MASTER))
 466		return;
 467
 468	list_for_each_entry(slave, &pe->slaves, list) {
 469		rc = opal_pci_eeh_freeze_set(phb->opal_id,
 470					     slave->pe_number,
 471					     OPAL_EEH_ACTION_SET_FREEZE_ALL);
 472		if (rc != OPAL_SUCCESS)
 473			pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 474				__func__, rc, phb->hose->global_number,
 475				slave->pe_number);
 476	}
 477}
 478
 479static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 480{
 481	struct pnv_ioda_pe *pe, *slave;
 482	s64 rc;
 483
 484	/* Find master PE */
 485	pe = &phb->ioda.pe_array[pe_no];
 486	if (pe->flags & PNV_IODA_PE_SLAVE) {
 487		pe = pe->master;
 488		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 489		pe_no = pe->pe_number;
 490	}
 491
 492	/* Clear frozen state for master PE */
 493	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 494	if (rc != OPAL_SUCCESS) {
 495		pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 496			__func__, rc, opt, phb->hose->global_number, pe_no);
 497		return -EIO;
 498	}
 499
 500	if (!(pe->flags & PNV_IODA_PE_MASTER))
 501		return 0;
 502
 503	/* Clear frozen state for slave PEs */
 504	list_for_each_entry(slave, &pe->slaves, list) {
 505		rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 506					     slave->pe_number,
 507					     opt);
 508		if (rc != OPAL_SUCCESS) {
 509			pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 510				__func__, rc, opt, phb->hose->global_number,
 511				slave->pe_number);
 512			return -EIO;
 513		}
 514	}
 515
 516	return 0;
 517}
 518
 519static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 520{
 521	struct pnv_ioda_pe *slave, *pe;
 522	u8 fstate = 0, state;
 523	__be16 pcierr = 0;
 524	s64 rc;
 525
 526	/* Sanity check on PE number */
 527	if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 528		return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 529
 530	/*
 531	 * Fetch the master PE and the PE instance might be
 532	 * not initialized yet.
 533	 */
 534	pe = &phb->ioda.pe_array[pe_no];
 535	if (pe->flags & PNV_IODA_PE_SLAVE) {
 536		pe = pe->master;
 537		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 538		pe_no = pe->pe_number;
 539	}
 540
 541	/* Check the master PE */
 542	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 543					&state, &pcierr, NULL);
 544	if (rc != OPAL_SUCCESS) {
 545		pr_warn("%s: Failure %lld getting "
 546			"PHB#%x-PE#%x state\n",
 547			__func__, rc,
 548			phb->hose->global_number, pe_no);
 549		return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 550	}
 551
 552	/* Check the slave PE */
 553	if (!(pe->flags & PNV_IODA_PE_MASTER))
 554		return state;
 555
 556	list_for_each_entry(slave, &pe->slaves, list) {
 557		rc = opal_pci_eeh_freeze_status(phb->opal_id,
 558						slave->pe_number,
 559						&fstate,
 560						&pcierr,
 561						NULL);
 562		if (rc != OPAL_SUCCESS) {
 563			pr_warn("%s: Failure %lld getting "
 564				"PHB#%x-PE#%x state\n",
 565				__func__, rc,
 566				phb->hose->global_number, slave->pe_number);
 567			return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 568		}
 569
 570		/*
 571		 * Override the result based on the ascending
 572		 * priority.
 573		 */
 574		if (fstate > state)
 575			state = fstate;
 576	}
 577
 578	return state;
 579}
 580
 581struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn)
 582{
 583	int pe_number = phb->ioda.pe_rmap[bdfn];
 584
 585	if (pe_number == IODA_INVALID_PE)
 586		return NULL;
 587
 588	return &phb->ioda.pe_array[pe_number];
 589}
 590
 591struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 592{
 593	struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
 594	struct pci_dn *pdn = pci_get_pdn(dev);
 595
 596	if (!pdn)
 597		return NULL;
 598	if (pdn->pe_number == IODA_INVALID_PE)
 599		return NULL;
 600	return &phb->ioda.pe_array[pdn->pe_number];
 601}
 602
 603static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 604				  struct pnv_ioda_pe *parent,
 605				  struct pnv_ioda_pe *child,
 606				  bool is_add)
 607{
 608	const char *desc = is_add ? "adding" : "removing";
 609	uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 610			      OPAL_REMOVE_PE_FROM_DOMAIN;
 611	struct pnv_ioda_pe *slave;
 612	long rc;
 613
 614	/* Parent PE affects child PE */
 615	rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 616				child->pe_number, op);
 617	if (rc != OPAL_SUCCESS) {
 618		pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 619			rc, desc);
 620		return -ENXIO;
 621	}
 622
 623	if (!(child->flags & PNV_IODA_PE_MASTER))
 624		return 0;
 625
 626	/* Compound case: parent PE affects slave PEs */
 627	list_for_each_entry(slave, &child->slaves, list) {
 628		rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 629					slave->pe_number, op);
 630		if (rc != OPAL_SUCCESS) {
 631			pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 632				rc, desc);
 633			return -ENXIO;
 634		}
 635	}
 636
 637	return 0;
 638}
 639
 640static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 641			      struct pnv_ioda_pe *pe,
 642			      bool is_add)
 643{
 644	struct pnv_ioda_pe *slave;
 645	struct pci_dev *pdev = NULL;
 646	int ret;
 647
 648	/*
 649	 * Clear PE frozen state. If it's master PE, we need
 650	 * clear slave PE frozen state as well.
 651	 */
 652	if (is_add) {
 653		opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 654					  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 655		if (pe->flags & PNV_IODA_PE_MASTER) {
 656			list_for_each_entry(slave, &pe->slaves, list)
 657				opal_pci_eeh_freeze_clear(phb->opal_id,
 658							  slave->pe_number,
 659							  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 660		}
 661	}
 662
 663	/*
 664	 * Associate PE in PELT. We need add the PE into the
 665	 * corresponding PELT-V as well. Otherwise, the error
 666	 * originated from the PE might contribute to other
 667	 * PEs.
 668	 */
 669	ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 670	if (ret)
 671		return ret;
 672
 673	/* For compound PEs, any one affects all of them */
 674	if (pe->flags & PNV_IODA_PE_MASTER) {
 675		list_for_each_entry(slave, &pe->slaves, list) {
 676			ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 677			if (ret)
 678				return ret;
 679		}
 680	}
 681
 682	if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 683		pdev = pe->pbus->self;
 684	else if (pe->flags & PNV_IODA_PE_DEV)
 685		pdev = pe->pdev->bus->self;
 686#ifdef CONFIG_PCI_IOV
 687	else if (pe->flags & PNV_IODA_PE_VF)
 688		pdev = pe->parent_dev;
 689#endif /* CONFIG_PCI_IOV */
 690	while (pdev) {
 691		struct pci_dn *pdn = pci_get_pdn(pdev);
 692		struct pnv_ioda_pe *parent;
 693
 694		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 695			parent = &phb->ioda.pe_array[pdn->pe_number];
 696			ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 697			if (ret)
 698				return ret;
 699		}
 700
 701		pdev = pdev->bus->self;
 702	}
 703
 704	return 0;
 705}
 706
 707static void pnv_ioda_unset_peltv(struct pnv_phb *phb,
 708				 struct pnv_ioda_pe *pe,
 709				 struct pci_dev *parent)
 710{
 711	int64_t rc;
 712
 713	while (parent) {
 714		struct pci_dn *pdn = pci_get_pdn(parent);
 715
 716		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 717			rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 718						pe->pe_number,
 719						OPAL_REMOVE_PE_FROM_DOMAIN);
 720			/* XXX What to do in case of error ? */
 721		}
 722		parent = parent->bus->self;
 723	}
 724
 725	opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 726				  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 727
 728	/* Disassociate PE in PELT */
 729	rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 730				pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 731	if (rc)
 732		pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
 733}
 734
 735int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 736{
 737	struct pci_dev *parent;
 738	uint8_t bcomp, dcomp, fcomp;
 739	int64_t rc;
 740	long rid_end, rid;
 741
 742	/* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 743	if (pe->pbus) {
 744		int count;
 745
 746		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 747		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 748		parent = pe->pbus->self;
 749		if (pe->flags & PNV_IODA_PE_BUS_ALL)
 750			count = resource_size(&pe->pbus->busn_res);
 751		else
 752			count = 1;
 753
 754		switch(count) {
 755		case  1: bcomp = OpalPciBusAll;         break;
 756		case  2: bcomp = OpalPciBus7Bits;       break;
 757		case  4: bcomp = OpalPciBus6Bits;       break;
 758		case  8: bcomp = OpalPciBus5Bits;       break;
 759		case 16: bcomp = OpalPciBus4Bits;       break;
 760		case 32: bcomp = OpalPciBus3Bits;       break;
 761		default:
 762			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 763			        count);
 764			/* Do an exact match only */
 765			bcomp = OpalPciBusAll;
 766		}
 767		rid_end = pe->rid + (count << 8);
 768	} else {
 769#ifdef CONFIG_PCI_IOV
 770		if (pe->flags & PNV_IODA_PE_VF)
 771			parent = pe->parent_dev;
 772		else
 773#endif
 774			parent = pe->pdev->bus->self;
 775		bcomp = OpalPciBusAll;
 776		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 777		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 778		rid_end = pe->rid + 1;
 779	}
 780
 781	/* Clear the reverse map */
 782	for (rid = pe->rid; rid < rid_end; rid++)
 783		phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 784
 785	/*
 786	 * Release from all parents PELT-V. NPUs don't have a PELTV
 787	 * table
 788	 */
 789	if (phb->type != PNV_PHB_NPU_OCAPI)
 790		pnv_ioda_unset_peltv(phb, pe, parent);
 791
 792	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 793			     bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 794	if (rc)
 795		pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
 796
 797	pe->pbus = NULL;
 798	pe->pdev = NULL;
 799#ifdef CONFIG_PCI_IOV
 800	pe->parent_dev = NULL;
 801#endif
 802
 803	return 0;
 804}
 805
 806int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 807{
 808	uint8_t bcomp, dcomp, fcomp;
 809	long rc, rid_end, rid;
 810
 811	/* Bus validation ? */
 812	if (pe->pbus) {
 813		int count;
 814
 815		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 816		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 817		if (pe->flags & PNV_IODA_PE_BUS_ALL)
 818			count = resource_size(&pe->pbus->busn_res);
 819		else
 820			count = 1;
 821
 822		switch(count) {
 823		case  1: bcomp = OpalPciBusAll;		break;
 824		case  2: bcomp = OpalPciBus7Bits;	break;
 825		case  4: bcomp = OpalPciBus6Bits;	break;
 826		case  8: bcomp = OpalPciBus5Bits;	break;
 827		case 16: bcomp = OpalPciBus4Bits;	break;
 828		case 32: bcomp = OpalPciBus3Bits;	break;
 829		default:
 830			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 831			        count);
 832			/* Do an exact match only */
 833			bcomp = OpalPciBusAll;
 834		}
 835		rid_end = pe->rid + (count << 8);
 836	} else {
 837		bcomp = OpalPciBusAll;
 838		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 839		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 840		rid_end = pe->rid + 1;
 841	}
 842
 843	/*
 844	 * Associate PE in PELT. We need add the PE into the
 845	 * corresponding PELT-V as well. Otherwise, the error
 846	 * originated from the PE might contribute to other
 847	 * PEs.
 848	 */
 849	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 850			     bcomp, dcomp, fcomp, OPAL_MAP_PE);
 851	if (rc) {
 852		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 853		return -ENXIO;
 854	}
 855
 856	/*
 857	 * Configure PELTV. NPUs don't have a PELTV table so skip
 858	 * configuration on them.
 859	 */
 860	if (phb->type != PNV_PHB_NPU_OCAPI)
 861		pnv_ioda_set_peltv(phb, pe, true);
 862
 863	/* Setup reverse map */
 864	for (rid = pe->rid; rid < rid_end; rid++)
 865		phb->ioda.pe_rmap[rid] = pe->pe_number;
 866
 867	pe->mve_number = 0;
 868
 869	return 0;
 870}
 871
 872static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 873{
 874	struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
 875	struct pci_dn *pdn = pci_get_pdn(dev);
 876	struct pnv_ioda_pe *pe;
 877
 878	if (!pdn) {
 879		pr_err("%s: Device tree node not associated properly\n",
 880			   pci_name(dev));
 881		return NULL;
 882	}
 883	if (pdn->pe_number != IODA_INVALID_PE)
 884		return NULL;
 885
 886	pe = pnv_ioda_alloc_pe(phb, 1);
 887	if (!pe) {
 888		pr_warn("%s: Not enough PE# available, disabling device\n",
 889			pci_name(dev));
 890		return NULL;
 891	}
 892
 893	/* NOTE: We don't get a reference for the pointer in the PE
 894	 * data structure, both the device and PE structures should be
 895	 * destroyed at the same time.
 896	 *
 897	 * At some point we want to remove the PDN completely anyways
 898	 */
 899	pdn->pe_number = pe->pe_number;
 900	pe->flags = PNV_IODA_PE_DEV;
 901	pe->pdev = dev;
 902	pe->pbus = NULL;
 903	pe->mve_number = -1;
 904	pe->rid = dev->bus->number << 8 | pdn->devfn;
 905	pe->device_count++;
 906
 907	pe_info(pe, "Associated device to PE\n");
 908
 909	if (pnv_ioda_configure_pe(phb, pe)) {
 910		/* XXX What do we do here ? */
 911		pnv_ioda_free_pe(pe);
 912		pdn->pe_number = IODA_INVALID_PE;
 913		pe->pdev = NULL;
 914		return NULL;
 915	}
 916
 917	/* Put PE to the list */
 918	mutex_lock(&phb->ioda.pe_list_mutex);
 919	list_add_tail(&pe->list, &phb->ioda.pe_list);
 920	mutex_unlock(&phb->ioda.pe_list_mutex);
 921	return pe;
 922}
 923
 924/*
 925 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
 926 * single PCI bus. Another one that contains the primary PCI bus and its
 927 * subordinate PCI devices and buses. The second type of PE is normally
 928 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
 929 */
 930static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
 931{
 932	struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
 933	struct pnv_ioda_pe *pe = NULL;
 934	unsigned int pe_num;
 935
 936	/*
 937	 * In partial hotplug case, the PE instance might be still alive.
 938	 * We should reuse it instead of allocating a new one.
 939	 */
 940	pe_num = phb->ioda.pe_rmap[bus->number << 8];
 941	if (WARN_ON(pe_num != IODA_INVALID_PE)) {
 942		pe = &phb->ioda.pe_array[pe_num];
 943		return NULL;
 944	}
 945
 946	/* PE number for root bus should have been reserved */
 947	if (pci_is_root_bus(bus))
 948		pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
 949
 950	/* Check if PE is determined by M64 */
 951	if (!pe)
 952		pe = pnv_ioda_pick_m64_pe(bus, all);
 953
 954	/* The PE number isn't pinned by M64 */
 955	if (!pe)
 956		pe = pnv_ioda_alloc_pe(phb, 1);
 957
 958	if (!pe) {
 959		pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
 960			__func__, pci_domain_nr(bus), bus->number);
 961		return NULL;
 962	}
 963
 964	pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
 965	pe->pbus = bus;
 966	pe->pdev = NULL;
 967	pe->mve_number = -1;
 968	pe->rid = bus->busn_res.start << 8;
 969
 970	if (all)
 971		pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
 972			&bus->busn_res.start, &bus->busn_res.end,
 973			pe->pe_number);
 974	else
 975		pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
 976			&bus->busn_res.start, pe->pe_number);
 977
 978	if (pnv_ioda_configure_pe(phb, pe)) {
 979		/* XXX What do we do here ? */
 980		pnv_ioda_free_pe(pe);
 981		pe->pbus = NULL;
 982		return NULL;
 983	}
 984
 985	/* Put PE to the list */
 986	list_add_tail(&pe->list, &phb->ioda.pe_list);
 987
 988	return pe;
 989}
 990
 991static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)
 992{
 993	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
 994	struct pci_dn *pdn = pci_get_pdn(pdev);
 995	struct pnv_ioda_pe *pe;
 996
 997	/* Check if the BDFN for this device is associated with a PE yet */
 998	pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
 999	if (!pe) {
1000		/* VF PEs should be pre-configured in pnv_pci_sriov_enable() */
1001		if (WARN_ON(pdev->is_virtfn))
1002			return;
1003
1004		pnv_pci_configure_bus(pdev->bus);
1005		pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
1006		pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff);
1007
1008
1009		/*
1010		 * If we can't setup the IODA PE something has gone horribly
1011		 * wrong and we can't enable DMA for the device.
1012		 */
1013		if (WARN_ON(!pe))
1014			return;
1015	} else {
1016		pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number);
1017	}
1018
1019	/*
1020	 * We assume that bridges *probably* don't need to do any DMA so we can
1021	 * skip allocating a TCE table, etc unless we get a non-bridge device.
1022	 */
1023	if (!pe->dma_setup_done && !pci_is_bridge(pdev)) {
1024		switch (phb->type) {
1025		case PNV_PHB_IODA2:
1026			pnv_pci_ioda2_setup_dma_pe(phb, pe);
1027			break;
1028		default:
1029			pr_warn("%s: No DMA for PHB#%x (type %d)\n",
1030				__func__, phb->hose->global_number, phb->type);
1031		}
1032	}
1033
1034	if (pdn)
1035		pdn->pe_number = pe->pe_number;
1036	pe->device_count++;
1037
1038	WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1039	pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1040	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1041
1042	/* PEs with a DMA weight of zero won't have a group */
1043	if (pe->table_group.group)
1044		iommu_add_device(&pe->table_group, &pdev->dev);
1045}
1046
1047/*
1048 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1049 *
1050 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1051 * Devices can only access more than that if bit 59 of the PCI address is set
1052 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1053 * Many PCI devices are not capable of addressing that many bits, and as a
1054 * result are limited to the 4GB of virtual memory made available to 32-bit
1055 * devices in TVE#0.
1056 *
1057 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1058 * devices by configuring the virtual memory past the first 4GB inaccessible
1059 * by 64-bit DMAs.  This should only be used by devices that want more than
1060 * 4GB, and only on PEs that have no 32-bit devices.
1061 *
1062 * Currently this will only work on PHB3 (POWER8).
1063 */
1064static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1065{
1066	u64 window_size, table_size, tce_count, addr;
1067	struct page *table_pages;
1068	u64 tce_order = 28; /* 256MB TCEs */
1069	__be64 *tces;
1070	s64 rc;
1071
1072	/*
1073	 * Window size needs to be a power of two, but needs to account for
1074	 * shifting memory by the 4GB offset required to skip 32bit space.
1075	 */
1076	window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1077	tce_count = window_size >> tce_order;
1078	table_size = tce_count << 3;
1079
1080	if (table_size < PAGE_SIZE)
1081		table_size = PAGE_SIZE;
1082
1083	table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1084				       get_order(table_size));
1085	if (!table_pages)
1086		goto err;
1087
1088	tces = page_address(table_pages);
1089	if (!tces)
1090		goto err;
1091
1092	memset(tces, 0, table_size);
1093
1094	for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1095		tces[(addr + (1ULL << 32)) >> tce_order] =
1096			cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1097	}
1098
1099	rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1100					pe->pe_number,
1101					/* reconfigure window 0 */
1102					(pe->pe_number << 1) + 0,
1103					1,
1104					__pa(tces),
1105					table_size,
1106					1 << tce_order);
1107	if (rc == OPAL_SUCCESS) {
1108		pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1109		return 0;
1110	}
1111err:
1112	pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1113	return -EIO;
1114}
1115
1116static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1117		u64 dma_mask)
1118{
1119	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
1120	struct pci_dn *pdn = pci_get_pdn(pdev);
1121	struct pnv_ioda_pe *pe;
1122
1123	if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1124		return false;
1125
1126	pe = &phb->ioda.pe_array[pdn->pe_number];
1127	if (pe->tce_bypass_enabled) {
1128		u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1129		if (dma_mask >= top)
1130			return true;
1131	}
1132
1133	/*
1134	 * If the device can't set the TCE bypass bit but still wants
1135	 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1136	 * bypass the 32-bit region and be usable for 64-bit DMAs.
1137	 * The device needs to be able to address all of this space.
1138	 */
1139	if (dma_mask >> 32 &&
1140	    dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1141	    /* pe->pdev should be set if it's a single device, pe->pbus if not */
1142	    (pe->device_count == 1 || !pe->pbus) &&
1143	    phb->model == PNV_PHB_MODEL_PHB3) {
1144		/* Configure the bypass mode */
1145		s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1146		if (rc)
1147			return false;
1148		/* 4GB offset bypasses 32-bit space */
1149		pdev->dev.archdata.dma_offset = (1ULL << 32);
1150		return true;
1151	}
1152
1153	return false;
1154}
1155
1156static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb)
1157{
1158	return phb->regs + 0x210;
1159}
1160
1161#ifdef CONFIG_IOMMU_API
1162/* Common for IODA1 and IODA2 */
1163static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1164		unsigned long *hpa, enum dma_data_direction *direction)
1165{
1166	return pnv_tce_xchg(tbl, index, hpa, direction);
1167}
1168#endif
1169
1170#define PHB3_TCE_KILL_INVAL_ALL		PPC_BIT(0)
1171#define PHB3_TCE_KILL_INVAL_PE		PPC_BIT(1)
1172#define PHB3_TCE_KILL_INVAL_ONE		PPC_BIT(2)
1173
1174static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1175{
1176	/* 01xb - invalidate TCEs that match the specified PE# */
1177	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1178	unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1179
1180	mb(); /* Ensure above stores are visible */
1181	__raw_writeq_be(val, invalidate);
1182}
1183
1184static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe,
1185					unsigned shift, unsigned long index,
1186					unsigned long npages)
1187{
1188	__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1189	unsigned long start, end, inc;
1190
1191	/* We'll invalidate DMA address in PE scope */
1192	start = PHB3_TCE_KILL_INVAL_ONE;
1193	start |= (pe->pe_number & 0xFF);
1194	end = start;
1195
1196	/* Figure out the start, end and step */
1197	start |= (index << shift);
1198	end |= ((index + npages - 1) << shift);
1199	inc = (0x1ull << shift);
1200	mb();
1201
1202	while (start <= end) {
1203		__raw_writeq_be(start, invalidate);
1204		start += inc;
1205	}
1206}
1207
1208static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1209{
1210	struct pnv_phb *phb = pe->phb;
1211
1212	if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1213		pnv_pci_phb3_tce_invalidate_pe(pe);
1214	else
1215		opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1216				  pe->pe_number, 0, 0, 0);
1217}
1218
1219static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1220		unsigned long index, unsigned long npages)
1221{
1222	struct iommu_table_group_link *tgl;
1223
1224	list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
1225		struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1226				struct pnv_ioda_pe, table_group);
1227		struct pnv_phb *phb = pe->phb;
1228		unsigned int shift = tbl->it_page_shift;
1229
1230		if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1231			pnv_pci_phb3_tce_invalidate(pe, shift,
1232						    index, npages);
1233		else
1234			opal_pci_tce_kill(phb->opal_id,
1235					  OPAL_PCI_TCE_KILL_PAGES,
1236					  pe->pe_number, 1u << shift,
1237					  index << shift, npages);
1238	}
1239}
1240
1241static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1242		long npages, unsigned long uaddr,
1243		enum dma_data_direction direction,
1244		unsigned long attrs)
1245{
1246	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1247			attrs);
1248
1249	if (!ret)
1250		pnv_pci_ioda2_tce_invalidate(tbl, index, npages);
1251
1252	return ret;
1253}
1254
1255static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1256		long npages)
1257{
1258	pnv_tce_free(tbl, index, npages);
1259
1260	pnv_pci_ioda2_tce_invalidate(tbl, index, npages);
1261}
1262
1263static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1264	.set = pnv_ioda2_tce_build,
1265#ifdef CONFIG_IOMMU_API
1266	.xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1267	.tce_kill = pnv_pci_ioda2_tce_invalidate,
1268	.useraddrptr = pnv_tce_useraddrptr,
1269#endif
1270	.clear = pnv_ioda2_tce_free,
1271	.get = pnv_tce_get,
1272	.free = pnv_pci_ioda2_table_free_pages,
1273};
1274
1275static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1276		int num, struct iommu_table *tbl)
1277{
1278	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1279			table_group);
1280	struct pnv_phb *phb = pe->phb;
1281	int64_t rc;
1282	const unsigned long size = tbl->it_indirect_levels ?
1283			tbl->it_level_size : tbl->it_size;
1284	const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1285	const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1286
1287	pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
1288		num, start_addr, start_addr + win_size - 1,
1289		IOMMU_PAGE_SIZE(tbl));
1290
1291	/*
1292	 * Map TCE table through TVT. The TVE index is the PE number
1293	 * shifted by 1 bit for 32-bits DMA space.
1294	 */
1295	rc = opal_pci_map_pe_dma_window(phb->opal_id,
1296			pe->pe_number,
1297			(pe->pe_number << 1) + num,
1298			tbl->it_indirect_levels + 1,
1299			__pa(tbl->it_base),
1300			size << 3,
1301			IOMMU_PAGE_SIZE(tbl));
1302	if (rc) {
1303		pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
1304		return rc;
1305	}
1306
1307	pnv_pci_link_table_and_group(phb->hose->node, num,
1308			tbl, &pe->table_group);
1309	pnv_pci_ioda2_tce_invalidate_pe(pe);
1310
1311	return 0;
1312}
1313
1314static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
1315{
1316	uint16_t window_id = (pe->pe_number << 1 ) + 1;
1317	int64_t rc;
1318
1319	pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1320	if (enable) {
1321		phys_addr_t top = memblock_end_of_DRAM();
1322
1323		top = roundup_pow_of_two(top);
1324		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1325						     pe->pe_number,
1326						     window_id,
1327						     pe->tce_bypass_base,
1328						     top);
1329	} else {
1330		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1331						     pe->pe_number,
1332						     window_id,
1333						     pe->tce_bypass_base,
1334						     0);
1335	}
1336	if (rc)
1337		pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1338	else
1339		pe->tce_bypass_enabled = enable;
1340}
1341
1342static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
1343		int num, __u32 page_shift, __u64 window_size, __u32 levels,
1344		bool alloc_userspace_copy, struct iommu_table **ptbl)
1345{
1346	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1347			table_group);
1348	int nid = pe->phb->hose->node;
1349	__u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
1350	long ret;
1351	struct iommu_table *tbl;
1352
1353	tbl = pnv_pci_table_alloc(nid);
1354	if (!tbl)
1355		return -ENOMEM;
1356
1357	tbl->it_ops = &pnv_ioda2_iommu_ops;
1358
1359	ret = pnv_pci_ioda2_table_alloc_pages(nid,
1360			bus_offset, page_shift, window_size,
1361			levels, alloc_userspace_copy, tbl);
1362	if (ret) {
1363		iommu_tce_table_put(tbl);
1364		return ret;
1365	}
1366
1367	*ptbl = tbl;
1368
1369	return 0;
1370}
1371
1372static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
1373{
1374	struct iommu_table *tbl = NULL;
1375	long rc;
1376	unsigned long res_start, res_end;
1377
1378	/*
1379	 * crashkernel= specifies the kdump kernel's maximum memory at
1380	 * some offset and there is no guaranteed the result is a power
1381	 * of 2, which will cause errors later.
1382	 */
1383	const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
1384
1385	/*
1386	 * In memory constrained environments, e.g. kdump kernel, the
1387	 * DMA window can be larger than available memory, which will
1388	 * cause errors later.
1389	 */
1390	const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_PAGE_ORDER);
1391
1392	/*
1393	 * We create the default window as big as we can. The constraint is
1394	 * the max order of allocation possible. The TCE table is likely to
1395	 * end up being multilevel and with on-demand allocation in place,
1396	 * the initial use is not going to be huge as the default window aims
1397	 * to support crippled devices (i.e. not fully 64bit DMAble) only.
1398	 */
1399	/* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
1400	const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
1401	/* Each TCE level cannot exceed maxblock so go multilevel if needed */
1402	unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
1403	unsigned long tcelevel_order = ilog2(maxblock >> 3);
1404	unsigned int levels = tces_order / tcelevel_order;
1405
1406	if (tces_order % tcelevel_order)
1407		levels += 1;
1408	/*
1409	 * We try to stick to default levels (which is >1 at the moment) in
1410	 * order to save memory by relying on on-demain TCE level allocation.
1411	 */
1412	levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
1413
1414	rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
1415			window_size, levels, false, &tbl);
1416	if (rc) {
1417		pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
1418				rc);
1419		return rc;
1420	}
1421
1422	/* We use top part of 32bit space for MMIO so exclude it from DMA */
1423	res_start = 0;
1424	res_end = 0;
1425	if (window_size > pe->phb->ioda.m32_pci_base) {
1426		res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
1427		res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
1428	}
1429
1430	tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number;
1431	if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end))
1432		rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
1433	else
1434		rc = -ENOMEM;
1435	if (rc) {
1436		pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc);
1437		iommu_tce_table_put(tbl);
1438		tbl = NULL; /* This clears iommu_table_base below */
1439	}
1440	if (!pnv_iommu_bypass_disabled)
1441		pnv_pci_ioda2_set_bypass(pe, true);
1442
1443	/*
1444	 * Set table base for the case of IOMMU DMA use. Usually this is done
1445	 * from dma_dev_setup() which is not called when a device is returned
1446	 * from VFIO so do it here.
1447	 */
1448	if (pe->pdev)
1449		set_iommu_table_base(&pe->pdev->dev, tbl);
1450
1451	return 0;
1452}
1453
1454static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1455		int num)
1456{
1457	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1458			table_group);
1459	struct pnv_phb *phb = pe->phb;
1460	long ret;
1461
1462	pe_info(pe, "Removing DMA window #%d\n", num);
1463
1464	ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1465			(pe->pe_number << 1) + num,
1466			0/* levels */, 0/* table address */,
1467			0/* table size */, 0/* page size */);
1468	if (ret)
1469		pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
1470	else
1471		pnv_pci_ioda2_tce_invalidate_pe(pe);
1472
1473	pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
1474
1475	return ret;
1476}
1477
1478#ifdef CONFIG_IOMMU_API
1479unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
1480		__u64 window_size, __u32 levels)
1481{
1482	unsigned long bytes = 0;
1483	const unsigned window_shift = ilog2(window_size);
1484	unsigned entries_shift = window_shift - page_shift;
1485	unsigned table_shift = entries_shift + 3;
1486	unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
1487	unsigned long direct_table_size;
1488
1489	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
1490			!is_power_of_2(window_size))
1491		return 0;
1492
1493	/* Calculate a direct table size from window_size and levels */
1494	entries_shift = (entries_shift + levels - 1) / levels;
1495	table_shift = entries_shift + 3;
1496	table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
1497	direct_table_size =  1UL << table_shift;
1498
1499	for ( ; levels; --levels) {
1500		bytes += ALIGN(tce_table_size, direct_table_size);
1501
1502		tce_table_size /= direct_table_size;
1503		tce_table_size <<= 3;
1504		tce_table_size = max_t(unsigned long,
1505				tce_table_size, direct_table_size);
1506	}
1507
1508	return bytes + bytes; /* one for HW table, one for userspace copy */
1509}
1510
1511static long pnv_pci_ioda2_create_table_userspace(
1512		struct iommu_table_group *table_group,
1513		int num, __u32 page_shift, __u64 window_size, __u32 levels,
1514		struct iommu_table **ptbl)
1515{
1516	long ret = pnv_pci_ioda2_create_table(table_group,
1517			num, page_shift, window_size, levels, true, ptbl);
1518
1519	if (!ret)
1520		(*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
1521				page_shift, window_size, levels);
1522	return ret;
1523}
1524
1525static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1526{
1527	struct pci_dev *dev;
1528
1529	list_for_each_entry(dev, &bus->devices, bus_list) {
1530		set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1531		dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1532
1533		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1534			pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1535	}
1536}
1537
1538static long pnv_ioda2_take_ownership(struct iommu_table_group *table_group,
1539				     struct device *dev __maybe_unused)
1540{
1541	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1542						table_group);
1543	/* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
1544	struct iommu_table *tbl = pe->table_group.tables[0];
1545
1546	/*
1547	 * iommu_ops transfers the ownership per a device and we mode
1548	 * the group ownership with the first device in the group.
1549	 */
1550	if (!tbl)
1551		return 0;
1552
1553	pnv_pci_ioda2_set_bypass(pe, false);
1554	pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1555	if (pe->pbus)
1556		pnv_ioda_setup_bus_dma(pe, pe->pbus);
1557	else if (pe->pdev)
1558		set_iommu_table_base(&pe->pdev->dev, NULL);
1559	iommu_tce_table_put(tbl);
1560
1561	return 0;
1562}
1563
1564static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group,
1565					struct device *dev __maybe_unused)
1566{
1567	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1568						table_group);
1569
1570	/* See the comment about iommu_ops above */
1571	if (pe->table_group.tables[0])
1572		return;
1573	pnv_pci_ioda2_setup_default_config(pe);
1574	if (pe->pbus)
1575		pnv_ioda_setup_bus_dma(pe, pe->pbus);
1576}
1577
1578static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
1579	.get_table_size = pnv_pci_ioda2_get_table_size,
1580	.create_table = pnv_pci_ioda2_create_table_userspace,
1581	.set_window = pnv_pci_ioda2_set_window,
1582	.unset_window = pnv_pci_ioda2_unset_window,
1583	.take_ownership = pnv_ioda2_take_ownership,
1584	.release_ownership = pnv_ioda2_release_ownership,
1585};
1586#endif
1587
1588void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1589				struct pnv_ioda_pe *pe)
1590{
1591	int64_t rc;
1592
1593	/* TVE #1 is selected by PCI address bit 59 */
1594	pe->tce_bypass_base = 1ull << 59;
1595
1596	/* The PE will reserve all possible 32-bits space */
1597	pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
1598		phb->ioda.m32_pci_base);
1599
1600	/* Setup linux iommu table */
1601	pe->table_group.tce32_start = 0;
1602	pe->table_group.tce32_size = phb->ioda.m32_pci_base;
1603	pe->table_group.max_dynamic_windows_supported =
1604			IOMMU_TABLE_GROUP_MAX_TABLES;
1605	pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
1606	pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
1607
1608	rc = pnv_pci_ioda2_setup_default_config(pe);
1609	if (rc)
1610		return;
1611
1612#ifdef CONFIG_IOMMU_API
1613	pe->table_group.ops = &pnv_pci_ioda2_ops;
1614	iommu_register_group(&pe->table_group, phb->hose->global_number,
1615			     pe->pe_number);
1616#endif
1617	pe->dma_setup_done = true;
1618}
1619
1620/*
1621 * Called from KVM in real mode to EOI passthru interrupts. The ICP
1622 * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru().
1623 *
1624 * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call
1625 * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ
1626 * numbers of the in-the-middle MSI domain are vector numbers and it's
1627 * good enough for OPAL. Use that.
1628 */
1629int64_t pnv_opal_pci_msi_eoi(struct irq_data *d)
1630{
1631	struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data);
1632	struct pnv_phb *phb = hose->private_data;
1633
1634	return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq);
1635}
1636
1637static struct irq_chip pnv_pci_msi_irq_chip;
1638
1639/*
1640 * Returns true iff chip is something that we could call
1641 * pnv_opal_pci_msi_eoi for.
1642 */
1643bool is_pnv_opal_msi(struct irq_chip *chip)
1644{
1645	return chip == &pnv_pci_msi_irq_chip;
1646}
1647EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
1648
1649static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
1650				    unsigned int xive_num,
1651				    unsigned int is_64, struct msi_msg *msg)
1652{
1653	struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
1654	__be32 data;
1655	int rc;
1656
1657	dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__,
1658		is_64 ? "64" : "32", xive_num);
1659
1660	/* No PE assigned ? bail out ... no MSI for you ! */
1661	if (pe == NULL)
1662		return -ENXIO;
1663
1664	/* Check if we have an MVE */
1665	if (pe->mve_number < 0)
1666		return -ENXIO;
1667
1668	/* Force 32-bit MSI on some broken devices */
1669	if (dev->no_64bit_msi)
1670		is_64 = 0;
1671
1672	/* Assign XIVE to PE */
1673	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
1674	if (rc) {
1675		pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
1676			pci_name(dev), rc, xive_num);
1677		return -EIO;
1678	}
1679
1680	if (is_64) {
1681		__be64 addr64;
1682
1683		rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
1684				     &addr64, &data);
1685		if (rc) {
1686			pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
1687				pci_name(dev), rc);
1688			return -EIO;
1689		}
1690		msg->address_hi = be64_to_cpu(addr64) >> 32;
1691		msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
1692	} else {
1693		__be32 addr32;
1694
1695		rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
1696				     &addr32, &data);
1697		if (rc) {
1698			pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
1699				pci_name(dev), rc);
1700			return -EIO;
1701		}
1702		msg->address_hi = 0;
1703		msg->address_lo = be32_to_cpu(addr32);
1704	}
1705	msg->data = be32_to_cpu(data);
1706
1707	return 0;
1708}
1709
1710static void pnv_msi_shutdown(struct irq_data *d)
1711{
1712	d = d->parent_data;
1713	if (d->chip->irq_shutdown)
1714		d->chip->irq_shutdown(d);
1715}
1716
1717static bool pnv_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
1718				  struct irq_domain *real_parent, struct msi_domain_info *info)
1719{
1720	struct irq_chip *chip = info->chip;
1721
1722	if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
1723		return false;
1724
1725	chip->irq_shutdown = pnv_msi_shutdown;
1726	return true;
1727}
1728
1729#define PNV_PCI_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS		| \
1730				    MSI_FLAG_USE_DEF_CHIP_OPS		| \
1731				    MSI_FLAG_PCI_MSI_MASK_PARENT)
1732#define PNV_PCI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK		| \
1733				     MSI_FLAG_PCI_MSIX			| \
1734				     MSI_FLAG_MULTI_PCI_MSI)
1735
1736static const struct msi_parent_ops pnv_msi_parent_ops = {
1737	.required_flags		= PNV_PCI_MSI_FLAGS_REQUIRED,
1738	.supported_flags	= PNV_PCI_MSI_FLAGS_SUPPORTED,
1739	.chip_flags		= MSI_CHIP_FLAG_SET_EOI,
1740	.bus_select_token	= DOMAIN_BUS_NEXUS,
1741	.bus_select_mask	= MATCH_PCI_MSI,
1742	.prefix			= "PNV-",
1743	.init_dev_msi_info	= pnv_init_dev_msi_info,
1744};
1745
1746static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg)
1747{
1748	struct msi_desc *entry = irq_data_get_msi_desc(d);
1749	struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
1750	struct pci_controller *hose = irq_data_get_irq_chip_data(d);
1751	struct pnv_phb *phb = hose->private_data;
1752	int rc;
1753
1754	rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq,
1755				      entry->pci.msi_attrib.is_64, msg);
1756	if (rc)
1757		dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n",
1758			entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc);
1759}
1760
1761/*
1762 * The IRQ data is mapped in the MSI domain in which HW IRQ numbers
1763 * correspond to vector numbers.
1764 */
1765static void pnv_msi_eoi(struct irq_data *d)
1766{
1767	struct pci_controller *hose = irq_data_get_irq_chip_data(d);
1768	struct pnv_phb *phb = hose->private_data;
1769
1770	if (phb->model == PNV_PHB_MODEL_PHB3) {
1771		/*
1772		 * The EOI OPAL call takes an OPAL HW IRQ number but
1773		 * since it is translated into a vector number in
1774		 * OPAL, use that directly.
1775		 */
1776		WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq));
1777	}
1778
1779	irq_chip_eoi_parent(d);
1780}
1781
1782static struct irq_chip pnv_msi_irq_chip = {
1783	.name			= "PNV-MSI",
1784	.irq_shutdown		= pnv_msi_shutdown,
1785	.irq_mask		= irq_chip_mask_parent,
1786	.irq_unmask		= irq_chip_unmask_parent,
1787	.irq_eoi		= pnv_msi_eoi,
1788	.irq_set_affinity	= irq_chip_set_affinity_parent,
1789	.irq_compose_msi_msg	= pnv_msi_compose_msg,
1790};
1791
1792static int pnv_irq_parent_domain_alloc(struct irq_domain *domain,
1793				       unsigned int virq, int hwirq)
1794{
1795	struct irq_fwspec parent_fwspec;
1796	int ret;
1797
1798	parent_fwspec.fwnode = domain->parent->fwnode;
1799	parent_fwspec.param_count = 2;
1800	parent_fwspec.param[0] = hwirq;
1801	parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
1802
1803	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
1804	if (ret)
1805		return ret;
1806
1807	return 0;
1808}
1809
1810static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1811				unsigned int nr_irqs, void *arg)
1812{
1813	struct pci_controller *hose = domain->host_data;
1814	struct pnv_phb *phb = hose->private_data;
1815	msi_alloc_info_t *info = arg;
1816	struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc);
1817	int hwirq;
1818	int i, ret;
1819
1820	hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs);
1821	if (hwirq < 0) {
1822		dev_warn(&pdev->dev, "failed to find a free MSI\n");
1823		return -ENOSPC;
1824	}
1825
1826	dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__,
1827		hose->dn, virq, hwirq, nr_irqs);
1828
1829	for (i = 0; i < nr_irqs; i++) {
1830		ret = pnv_irq_parent_domain_alloc(domain, virq + i,
1831						  phb->msi_base + hwirq + i);
1832		if (ret)
1833			goto out;
1834
1835		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
1836					      &pnv_msi_irq_chip, hose);
1837	}
1838
1839	return 0;
1840
1841out:
1842	irq_domain_free_irqs_parent(domain, virq, i);
1843	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs);
1844	return ret;
1845}
1846
1847static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1848				unsigned int nr_irqs)
1849{
1850	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1851	struct pci_controller *hose = irq_data_get_irq_chip_data(d);
1852	struct pnv_phb *phb = hose->private_data;
1853
1854	pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn,
1855		 virq, d->hwirq, nr_irqs);
1856
1857	msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs);
1858	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1859}
1860
1861static const struct irq_domain_ops pnv_irq_domain_ops = {
1862	.select	= msi_lib_irq_domain_select,
1863	.alloc  = pnv_irq_domain_alloc,
1864	.free   = pnv_irq_domain_free,
1865};
1866
1867static int __init pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count)
1868{
1869	struct irq_domain *parent = irq_get_default_domain();
1870	struct irq_domain_info info = {
1871		.fwnode		= of_fwnode_handle(hose->dn),
1872		.ops		= &pnv_irq_domain_ops,
1873		.host_data	= hose,
1874		.size		= count,
1875		.parent		= parent,
1876	};
1877
1878	hose->dev_domain = msi_create_parent_irq_domain(&info, &pnv_msi_parent_ops);
1879	if (!hose->dev_domain) {
1880		pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n",
1881		       hose->dn, hose->global_number);
1882		return -ENOMEM;
1883	}
1884
1885	return 0;
1886}
1887
1888static void __init pnv_pci_init_ioda_msis(struct pnv_phb *phb)
1889{
1890	unsigned int count;
1891	const __be32 *prop = of_get_property(phb->hose->dn,
1892					     "ibm,opal-msi-ranges", NULL);
1893	if (!prop) {
1894		/* BML Fallback */
1895		prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
1896	}
1897	if (!prop)
1898		return;
1899
1900	phb->msi_base = be32_to_cpup(prop);
1901	count = be32_to_cpup(prop + 1);
1902	if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
1903		pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
1904		       phb->hose->global_number);
1905		return;
1906	}
1907
1908	pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
1909		count, phb->msi_base);
1910
1911	pnv_msi_allocate_domains(phb->hose, count);
1912}
1913
1914static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
1915				  struct resource *res)
1916{
1917	struct pnv_phb *phb = pe->phb;
1918	struct pci_bus_region region;
1919	int index;
1920	int64_t rc;
1921
1922	if (!res || !res->flags || res->start > res->end ||
1923	    res->flags & IORESOURCE_UNSET)
1924		return;
1925
1926	if (res->flags & IORESOURCE_IO) {
1927		region.start = res->start - phb->ioda.io_pci_base;
1928		region.end   = res->end - phb->ioda.io_pci_base;
1929		index = region.start / phb->ioda.io_segsize;
1930
1931		while (index < phb->ioda.total_pe_num &&
1932		       region.start <= region.end) {
1933			phb->ioda.io_segmap[index] = pe->pe_number;
1934			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1935				pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
1936			if (rc != OPAL_SUCCESS) {
1937				pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
1938				       __func__, rc, index, pe->pe_number);
1939				break;
1940			}
1941
1942			region.start += phb->ioda.io_segsize;
1943			index++;
1944		}
1945	} else if ((res->flags & IORESOURCE_MEM) &&
1946		   !pnv_pci_is_m64(phb, res)) {
1947		region.start = res->start -
1948			       phb->hose->mem_offset[0] -
1949			       phb->ioda.m32_pci_base;
1950		region.end   = res->end -
1951			       phb->hose->mem_offset[0] -
1952			       phb->ioda.m32_pci_base;
1953		index = region.start / phb->ioda.m32_segsize;
1954
1955		while (index < phb->ioda.total_pe_num &&
1956		       region.start <= region.end) {
1957			phb->ioda.m32_segmap[index] = pe->pe_number;
1958			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1959				pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
1960			if (rc != OPAL_SUCCESS) {
1961				pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
1962				       __func__, rc, index, pe->pe_number);
1963				break;
1964			}
1965
1966			region.start += phb->ioda.m32_segsize;
1967			index++;
1968		}
1969	}
1970}
1971
1972/*
1973 * This function is supposed to be called on basis of PE from top
1974 * to bottom style. So the I/O or MMIO segment assigned to
1975 * parent PE could be overridden by its child PEs if necessary.
1976 */
1977static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
1978{
1979	struct pci_dev *pdev;
1980	int i;
1981
1982	/*
1983	 * NOTE: We only care PCI bus based PE for now. For PCI
1984	 * device based PE, for example SRIOV sensitive VF should
1985	 * be figured out later.
1986	 */
1987	BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
1988
1989	list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1990		for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1991			pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
1992
1993		/*
1994		 * If the PE contains all subordinate PCI buses, the
1995		 * windows of the child bridges should be mapped to
1996		 * the PE as well.
1997		 */
1998		if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
1999			continue;
2000		for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
2001			pnv_ioda_setup_pe_res(pe,
2002				&pdev->resource[PCI_BRIDGE_RESOURCES + i]);
2003	}
2004}
2005
2006#ifdef CONFIG_DEBUG_FS
2007static int pnv_pci_diag_data_set(void *data, u64 val)
2008{
2009	struct pnv_phb *phb = data;
2010	s64 ret;
2011
2012	/* Retrieve the diag data from firmware */
2013	ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
2014					  phb->diag_data_size);
2015	if (ret != OPAL_SUCCESS)
2016		return -EIO;
2017
2018	/* Print the diag data to the kernel log */
2019	pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
2020	return 0;
2021}
2022
2023DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set,
2024			 "%llu\n");
2025
2026static int pnv_pci_ioda_pe_dump(void *data, u64 val)
2027{
2028	struct pnv_phb *phb = data;
2029	int pe_num;
2030
2031	for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
2032		struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];
2033
2034		if (!test_bit(pe_num, phb->ioda.pe_alloc))
2035			continue;
2036
2037		pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",
2038			pe->rid, pe->device_count,
2039			(pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",
2040			(pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",
2041			(pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",
2042			(pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",
2043			(pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",
2044			(pe->flags & PNV_IODA_PE_VF) ? "vf " : "");
2045	}
2046
2047	return 0;
2048}
2049
2050DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL,
2051			 pnv_pci_ioda_pe_dump, "%llu\n");
2052
2053#endif /* CONFIG_DEBUG_FS */
2054
2055static void pnv_pci_ioda_create_dbgfs(void)
2056{
2057#ifdef CONFIG_DEBUG_FS
2058	struct pci_controller *hose, *tmp;
2059	struct pnv_phb *phb;
2060	char name[16];
2061
2062	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2063		phb = hose->private_data;
2064
2065		sprintf(name, "PCI%04x", hose->global_number);
2066		phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir);
2067
2068		debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs,
2069					   phb, &pnv_pci_diag_data_fops);
2070		debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs,
2071					   phb, &pnv_pci_ioda_pe_dump_fops);
2072	}
2073#endif /* CONFIG_DEBUG_FS */
2074}
2075
2076static void pnv_pci_enable_bridge(struct pci_bus *bus)
2077{
2078	struct pci_dev *dev = bus->self;
2079	struct pci_bus *child;
2080
2081	/* Empty bus ? bail */
2082	if (list_empty(&bus->devices))
2083		return;
2084
2085	/*
2086	 * If there's a bridge associated with that bus enable it. This works
2087	 * around races in the generic code if the enabling is done during
2088	 * parallel probing. This can be removed once those races have been
2089	 * fixed.
2090	 */
2091	if (dev) {
2092		int rc = pci_enable_device(dev);
2093		if (rc)
2094			pci_err(dev, "Error enabling bridge (%d)\n", rc);
2095		pci_set_master(dev);
2096	}
2097
2098	/* Perform the same to child busses */
2099	list_for_each_entry(child, &bus->children, node)
2100		pnv_pci_enable_bridge(child);
2101}
2102
2103static void pnv_pci_enable_bridges(void)
2104{
2105	struct pci_controller *hose;
2106
2107	list_for_each_entry(hose, &hose_list, list_node)
2108		pnv_pci_enable_bridge(hose->bus);
2109}
2110
2111static void pnv_pci_ioda_fixup(void)
2112{
2113	pnv_pci_ioda_create_dbgfs();
2114
2115	pnv_pci_enable_bridges();
2116
2117#ifdef CONFIG_EEH
2118	pnv_eeh_post_init();
2119#endif
2120}
2121
2122/*
2123 * Returns the alignment for I/O or memory windows for P2P
2124 * bridges. That actually depends on how PEs are segmented.
2125 * For now, we return I/O or M32 segment size for PE sensitive
2126 * P2P bridges. Otherwise, the default values (4KiB for I/O,
2127 * 1MiB for memory) will be returned.
2128 *
2129 * The current PCI bus might be put into one PE, which was
2130 * create against the parent PCI bridge. For that case, we
2131 * needn't enlarge the alignment so that we can save some
2132 * resources.
2133 */
2134static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2135						unsigned long type)
2136{
2137	struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2138	int num_pci_bridges = 0;
2139	struct pci_dev *bridge;
2140
2141	bridge = bus->self;
2142	while (bridge) {
2143		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2144			num_pci_bridges++;
2145			if (num_pci_bridges >= 2)
2146				return 1;
2147		}
2148
2149		bridge = bridge->bus->self;
2150	}
2151
2152	/*
2153	 * We fall back to M32 if M64 isn't supported. We enforce the M64
2154	 * alignment for any 64-bit resource, PCIe doesn't care and
2155	 * bridges only do 64-bit prefetchable anyway.
2156	 */
2157	if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
2158		return phb->ioda.m64_segsize;
2159	if (type & IORESOURCE_MEM)
2160		return phb->ioda.m32_segsize;
2161
2162	return phb->ioda.io_segsize;
2163}
2164
2165/*
2166 * We are updating root port or the upstream port of the
2167 * bridge behind the root port with PHB's windows in order
2168 * to accommodate the changes on required resources during
2169 * PCI (slot) hotplug, which is connected to either root
2170 * port or the downstream ports of PCIe switch behind the
2171 * root port.
2172 */
2173static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
2174					   unsigned long type)
2175{
2176	struct pci_controller *hose = pci_bus_to_host(bus);
2177	struct pnv_phb *phb = hose->private_data;
2178	struct pci_dev *bridge = bus->self;
2179	struct resource *r, *w;
2180	bool msi_region = false;
2181	int i;
2182
2183	/* Check if we need apply fixup to the bridge's windows */
2184	if (!pci_is_root_bus(bridge->bus) &&
2185	    !pci_is_root_bus(bridge->bus->self->bus))
2186		return;
2187
2188	/* Fixup the resources */
2189	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
2190		r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
2191		if (!r->flags || !r->parent)
2192			continue;
2193
2194		w = NULL;
2195		if (r->flags & type & IORESOURCE_IO)
2196			w = &hose->io_resource;
2197		else if (pnv_pci_is_m64(phb, r) &&
2198			 (type & IORESOURCE_PREFETCH) &&
2199			 phb->ioda.m64_segsize)
2200			w = &hose->mem_resources[1];
2201		else if (r->flags & type & IORESOURCE_MEM) {
2202			w = &hose->mem_resources[0];
2203			msi_region = true;
2204		}
2205
2206		r->start = w->start;
2207		r->end = w->end;
2208
2209		/* The 64KB 32-bits MSI region shouldn't be included in
2210		 * the 32-bits bridge window. Otherwise, we can see strange
2211		 * issues. One of them is EEH error observed on Garrison.
2212		 *
2213		 * Exclude top 1MB region which is the minimal alignment of
2214		 * 32-bits bridge window.
2215		 */
2216		if (msi_region) {
2217			r->end += 0x10000;
2218			r->end -= 0x100000;
2219		}
2220	}
2221}
2222
2223static void pnv_pci_configure_bus(struct pci_bus *bus)
2224{
2225	struct pci_dev *bridge = bus->self;
2226	struct pnv_ioda_pe *pe;
2227	bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
2228
2229	dev_info(&bus->dev, "Configuring PE for bus\n");
2230
2231	/* Don't assign PE to PCI bus, which doesn't have subordinate devices */
2232	if (WARN_ON(list_empty(&bus->devices)))
2233		return;
2234
2235	/* Reserve PEs according to used M64 resources */
2236	pnv_ioda_reserve_m64_pe(bus, NULL, all);
2237
2238	/*
2239	 * Assign PE. We might run here because of partial hotplug.
2240	 * For the case, we just pick up the existing PE and should
2241	 * not allocate resources again.
2242	 */
2243	pe = pnv_ioda_setup_bus_PE(bus, all);
2244	if (!pe)
2245		return;
2246
2247	pnv_ioda_setup_pe_seg(pe);
2248}
2249
2250static resource_size_t pnv_pci_default_alignment(void)
2251{
2252	return PAGE_SIZE;
2253}
2254
2255/* Prevent enabling devices for which we couldn't properly
2256 * assign a PE
2257 */
2258static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
2259{
2260	struct pci_dn *pdn;
2261
2262	pdn = pci_get_pdn(dev);
2263	if (!pdn || pdn->pe_number == IODA_INVALID_PE) {
2264		pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n");
2265		return false;
2266	}
2267
2268	return true;
2269}
2270
2271static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev)
2272{
2273	struct pci_dn *pdn;
2274	struct pnv_ioda_pe *pe;
2275
2276	pdn = pci_get_pdn(dev);
2277	if (!pdn)
2278		return false;
2279
2280	if (pdn->pe_number == IODA_INVALID_PE) {
2281		pe = pnv_ioda_setup_dev_PE(dev);
2282		if (!pe)
2283			return false;
2284	}
2285	return true;
2286}
2287
2288void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
2289{
2290	struct iommu_table *tbl = pe->table_group.tables[0];
2291	int64_t rc;
2292
2293	if (!pe->dma_setup_done)
2294		return;
2295
2296	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2297	if (rc)
2298		pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
2299
2300	pnv_pci_ioda2_set_bypass(pe, false);
2301	if (pe->table_group.group) {
2302		iommu_group_put(pe->table_group.group);
2303		WARN_ON(pe->table_group.group);
2304	}
2305
2306	iommu_tce_table_put(tbl);
2307}
2308
2309static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
2310				 unsigned short win,
2311				 unsigned int *map)
2312{
2313	struct pnv_phb *phb = pe->phb;
2314	int idx;
2315	int64_t rc;
2316
2317	for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
2318		if (map[idx] != pe->pe_number)
2319			continue;
2320
2321		rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2322				phb->ioda.reserved_pe_idx, win, 0, idx);
2323
2324		if (rc != OPAL_SUCCESS)
2325			pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
2326				rc, win, idx);
2327
2328		map[idx] = IODA_INVALID_PE;
2329	}
2330}
2331
2332static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
2333{
2334	struct pnv_phb *phb = pe->phb;
2335
2336	if (phb->type == PNV_PHB_IODA2) {
2337		pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2338				     phb->ioda.m32_segmap);
2339	}
2340}
2341
2342static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
2343{
2344	struct pnv_phb *phb = pe->phb;
2345	struct pnv_ioda_pe *slave, *tmp;
2346
2347	pe_info(pe, "Releasing PE\n");
2348
2349	mutex_lock(&phb->ioda.pe_list_mutex);
2350	list_del(&pe->list);
2351	mutex_unlock(&phb->ioda.pe_list_mutex);
2352
2353	switch (phb->type) {
2354	case PNV_PHB_IODA2:
2355		pnv_pci_ioda2_release_pe_dma(pe);
2356		break;
2357	case PNV_PHB_NPU_OCAPI:
2358		break;
2359	default:
2360		WARN_ON(1);
2361	}
2362
2363	pnv_ioda_release_pe_seg(pe);
2364	pnv_ioda_deconfigure_pe(pe->phb, pe);
2365
2366	/* Release slave PEs in the compound PE */
2367	if (pe->flags & PNV_IODA_PE_MASTER) {
2368		list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
2369			list_del(&slave->list);
2370			pnv_ioda_free_pe(slave);
2371		}
2372	}
2373
2374	/*
2375	 * The PE for root bus can be removed because of hotplug in EEH
2376	 * recovery for fenced PHB error. We need to mark the PE dead so
2377	 * that it can be populated again in PCI hot add path. The PE
2378	 * shouldn't be destroyed as it's the global reserved resource.
2379	 */
2380	if (phb->ioda.root_pe_idx == pe->pe_number)
2381		return;
2382
2383	pnv_ioda_free_pe(pe);
2384}
2385
2386static void pnv_pci_release_device(struct pci_dev *pdev)
2387{
2388	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
2389	struct pci_dn *pdn = pci_get_pdn(pdev);
2390	struct pnv_ioda_pe *pe;
2391
2392	/* The VF PE state is torn down when sriov_disable() is called */
2393	if (pdev->is_virtfn)
2394		return;
2395
2396	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2397		return;
2398
2399#ifdef CONFIG_PCI_IOV
2400	/*
2401	 * FIXME: Try move this to sriov_disable(). It's here since we allocate
2402	 * the iov state at probe time since we need to fiddle with the IOV
2403	 * resources.
2404	 */
2405	if (pdev->is_physfn)
2406		kfree(pdev->dev.archdata.iov_data);
2407#endif
2408
2409	/*
2410	 * PCI hotplug can happen as part of EEH error recovery. The @pdn
2411	 * isn't removed and added afterwards in this scenario. We should
2412	 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
2413	 * device count is decreased on removing devices while failing to
2414	 * be increased on adding devices. It leads to unbalanced PE's device
2415	 * count and eventually make normal PCI hotplug path broken.
2416	 */
2417	pe = &phb->ioda.pe_array[pdn->pe_number];
2418	pdn->pe_number = IODA_INVALID_PE;
2419
2420	WARN_ON(--pe->device_count < 0);
2421	if (pe->device_count == 0)
2422		pnv_ioda_release_pe(pe);
2423}
2424
2425static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
2426{
2427	struct pnv_phb *phb = hose->private_data;
2428
2429	opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
2430		       OPAL_ASSERT_RESET);
2431}
2432
2433static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus)
2434{
2435	struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2436	struct pnv_ioda_pe *pe;
2437
2438	list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2439		if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
2440			continue;
2441
2442		if (!pe->pbus)
2443			continue;
2444
2445		if (bus->number == ((pe->rid >> 8) & 0xFF)) {
2446			pe->pbus = bus;
2447			break;
2448		}
2449	}
2450}
2451
2452#ifdef CONFIG_IOMMU_API
2453static struct iommu_group *pnv_pci_device_group(struct pci_controller *hose,
2454						struct pci_dev *pdev)
2455{
2456	struct pnv_phb *phb = hose->private_data;
2457	struct pnv_ioda_pe *pe;
2458
2459	if (WARN_ON(!phb))
2460		return ERR_PTR(-ENODEV);
2461
2462	pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
2463	if (!pe)
2464		return ERR_PTR(-ENODEV);
2465
2466	if (!pe->table_group.group)
2467		return ERR_PTR(-ENODEV);
2468
2469	return iommu_group_ref_get(pe->table_group.group);
2470}
2471#endif
2472
2473static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
2474	.dma_dev_setup		= pnv_pci_ioda_dma_dev_setup,
2475	.dma_bus_setup		= pnv_pci_ioda_dma_bus_setup,
2476	.iommu_bypass_supported	= pnv_pci_ioda_iommu_bypass_supported,
2477	.enable_device_hook	= pnv_pci_enable_device_hook,
2478	.release_device		= pnv_pci_release_device,
2479	.window_alignment	= pnv_pci_window_alignment,
2480	.setup_bridge		= pnv_pci_fixup_bridge_resources,
2481	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
2482	.shutdown		= pnv_pci_ioda_shutdown,
2483#ifdef CONFIG_IOMMU_API
2484	.device_group		= pnv_pci_device_group,
2485#endif
2486};
2487
2488static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
2489	.enable_device_hook	= pnv_ocapi_enable_device_hook,
2490	.release_device		= pnv_pci_release_device,
2491	.window_alignment	= pnv_pci_window_alignment,
2492	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
2493	.shutdown		= pnv_pci_ioda_shutdown,
2494};
2495
2496static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2497					 u64 hub_id, int ioda_type)
2498{
2499	struct pci_controller *hose;
2500	struct pnv_phb *phb;
2501	unsigned long size, m64map_off, m32map_off, pemap_off;
2502	struct pnv_ioda_pe *root_pe;
2503	struct resource r;
2504	const __be64 *prop64;
2505	const __be32 *prop32;
2506	int len;
2507	unsigned int segno;
2508	u64 phb_id;
2509	void *aux;
2510	long rc;
2511
2512	if (!of_device_is_available(np))
2513		return;
2514
2515	pr_info("Initializing %s PHB (%pOF)\n",	pnv_phb_names[ioda_type], np);
2516
2517	prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
2518	if (!prop64) {
2519		pr_err("  Missing \"ibm,opal-phbid\" property !\n");
2520		return;
2521	}
2522	phb_id = be64_to_cpup(prop64);
2523	pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
2524
2525	phb = kzalloc(sizeof(*phb), GFP_KERNEL);
2526	if (!phb)
2527		panic("%s: Failed to allocate %zu bytes\n", __func__,
2528		      sizeof(*phb));
2529
2530	/* Allocate PCI controller */
2531	phb->hose = hose = pcibios_alloc_controller(np);
2532	if (!phb->hose) {
2533		pr_err("  Can't allocate PCI controller for %pOF\n",
2534		       np);
2535		memblock_free(phb, sizeof(struct pnv_phb));
2536		return;
2537	}
2538
2539	spin_lock_init(&phb->lock);
2540	prop32 = of_get_property(np, "bus-range", &len);
2541	if (prop32 && len == 8) {
2542		hose->first_busno = be32_to_cpu(prop32[0]);
2543		hose->last_busno = be32_to_cpu(prop32[1]);
2544	} else {
2545		pr_warn("  Broken <bus-range> on %pOF\n", np);
2546		hose->first_busno = 0;
2547		hose->last_busno = 0xff;
2548	}
2549	hose->private_data = phb;
2550	phb->hub_id = hub_id;
2551	phb->opal_id = phb_id;
2552	phb->type = ioda_type;
2553	mutex_init(&phb->ioda.pe_alloc_mutex);
2554
2555	/* Detect specific models for error handling */
2556	if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
2557		phb->model = PNV_PHB_MODEL_P7IOC;
2558	else if (of_device_is_compatible(np, "ibm,power8-pciex"))
2559		phb->model = PNV_PHB_MODEL_PHB3;
2560	else
2561		phb->model = PNV_PHB_MODEL_UNKNOWN;
2562
2563	/* Initialize diagnostic data buffer */
2564	prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
2565	if (prop32)
2566		phb->diag_data_size = be32_to_cpup(prop32);
2567	else
2568		phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
2569
2570	phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL);
2571	if (!phb->diag_data)
2572		panic("%s: Failed to allocate %u bytes\n", __func__,
2573		      phb->diag_data_size);
2574
2575	/* Parse 32-bit and IO ranges (if any) */
2576	pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
2577
2578	/* Get registers */
2579	if (!of_address_to_resource(np, 0, &r)) {
2580		phb->regs_phys = r.start;
2581		phb->regs = ioremap(r.start, resource_size(&r));
2582		if (phb->regs == NULL)
2583			pr_err("  Failed to map registers !\n");
2584	}
2585
2586	/* Initialize more IODA stuff */
2587	phb->ioda.total_pe_num = 1;
2588	prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
2589	if (prop32)
2590		phb->ioda.total_pe_num = be32_to_cpup(prop32);
2591	prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
2592	if (prop32)
2593		phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
2594
2595	/* Invalidate RID to PE# mapping */
2596	for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
2597		phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
2598
2599	/* Parse 64-bit MMIO range */
2600	pnv_ioda_parse_m64_window(phb);
2601
2602	phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
2603	/* FW Has already off top 64k of M32 space (MSI space) */
2604	phb->ioda.m32_size += 0x10000;
2605
2606	phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
2607	phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
2608	phb->ioda.io_size = hose->pci_io_size;
2609	phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
2610	phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
2611
2612	/* Allocate aux data & arrays. We don't have IO ports on PHB3 */
2613	size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
2614			sizeof(unsigned long));
2615	m64map_off = size;
2616	size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
2617	m32map_off = size;
2618	size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
2619	pemap_off = size;
2620	size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
2621	aux = kzalloc(size, GFP_KERNEL);
2622	if (!aux)
2623		panic("%s: Failed to allocate %lu bytes\n", __func__, size);
2624
2625	phb->ioda.pe_alloc = aux;
2626	phb->ioda.m64_segmap = aux + m64map_off;
2627	phb->ioda.m32_segmap = aux + m32map_off;
2628	for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
2629		phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
2630		phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
2631	}
2632	phb->ioda.pe_array = aux + pemap_off;
2633
2634	/*
2635	 * Choose PE number for root bus, which shouldn't have
2636	 * M64 resources consumed by its child devices. To pick
2637	 * the PE number adjacent to the reserved one if possible.
2638	 */
2639	pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
2640	if (phb->ioda.reserved_pe_idx == 0) {
2641		phb->ioda.root_pe_idx = 1;
2642		pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
2643	} else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
2644		phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
2645		pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
2646	} else {
2647		/* otherwise just allocate one */
2648		root_pe = pnv_ioda_alloc_pe(phb, 1);
2649		phb->ioda.root_pe_idx = root_pe->pe_number;
2650	}
2651
2652	INIT_LIST_HEAD(&phb->ioda.pe_list);
2653	mutex_init(&phb->ioda.pe_list_mutex);
2654
2655#if 0 /* We should really do that ... */
2656	rc = opal_pci_set_phb_mem_window(opal->phb_id,
2657					 window_type,
2658					 window_num,
2659					 starting_real_address,
2660					 starting_pci_address,
2661					 segment_size);
2662#endif
2663
2664	pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
2665		phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
2666		phb->ioda.m32_size, phb->ioda.m32_segsize);
2667	if (phb->ioda.m64_size)
2668		pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
2669			phb->ioda.m64_size, phb->ioda.m64_segsize);
2670	if (phb->ioda.io_size)
2671		pr_info("                  IO: 0x%x [segment=0x%x]\n",
2672			phb->ioda.io_size, phb->ioda.io_segsize);
2673
2674
2675	phb->hose->ops = &pnv_pci_ops;
2676	phb->get_pe_state = pnv_ioda_get_pe_state;
2677	phb->freeze_pe = pnv_ioda_freeze_pe;
2678	phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
2679
2680	/* Setup MSI support */
2681	pnv_pci_init_ioda_msis(phb);
2682
2683	/*
2684	 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
2685	 * to let the PCI core do resource assignment. It's supposed
2686	 * that the PCI core will do correct I/O and MMIO alignment
2687	 * for the P2P bridge bars so that each PCI bus (excluding
2688	 * the child P2P bridges) can form individual PE.
2689	 */
2690	ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
2691
2692	switch (phb->type) {
2693	case PNV_PHB_NPU_OCAPI:
2694		hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
2695		break;
2696	default:
2697		hose->controller_ops = pnv_pci_ioda_controller_ops;
2698	}
2699
2700	ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
2701
2702#ifdef CONFIG_PCI_IOV
2703	ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
2704	ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
2705	ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
2706	ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
2707#endif
2708
2709	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
2710
2711	/* Reset IODA tables to a clean state */
2712	rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
2713	if (rc)
2714		pr_warn("  OPAL Error %ld performing IODA table reset !\n", rc);
2715
2716	/*
2717	 * If we're running in kdump kernel, the previous kernel never
2718	 * shutdown PCI devices correctly. We already got IODA table
2719	 * cleaned out. So we have to issue PHB reset to stop all PCI
2720	 * transactions from previous kernel. The ppc_pci_reset_phbs
2721	 * kernel parameter will force this reset too. Additionally,
2722	 * if the IODA reset above failed then use a bigger hammer.
2723	 * This can happen if we get a PHB fatal error in very early
2724	 * boot.
2725	 */
2726	if (is_kdump_kernel() || pci_reset_phbs || rc) {
2727		pr_info("  Issue PHB reset ...\n");
2728		pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
2729		pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
2730	}
2731
2732	/* Remove M64 resource if we can't configure it successfully */
2733	if (!phb->init_m64 || phb->init_m64(phb))
2734		hose->mem_resources[1].flags = 0;
2735
2736	/* create pci_dn's for DT nodes under this PHB */
2737	pci_devs_phb_init_dynamic(hose);
2738}
2739
2740void __init pnv_pci_init_ioda2_phb(struct device_node *np)
2741{
2742	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
2743}
2744
2745void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
2746{
2747	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
2748}
2749
2750static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
2751{
2752	struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
2753
2754	if (!machine_is(powernv))
2755		return;
2756
2757	if (phb->type == PNV_PHB_NPU_OCAPI)
2758		dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
2759}
2760DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);