pic.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 *  Support for the interrupt controllers found on Power Macintosh,
  4 *  currently Apple's "Grand Central" interrupt controller in all
  5 *  its incarnations. OpenPIC support used on newer machines is
  6 *  in a separate file
  7 *
  8 *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
  9 *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 10 *                     IBM, Corp.
 11 */
 12
 13#include <linux/stddef.h>
 14#include <linux/init.h>
 15#include <linux/sched.h>
 16#include <linux/signal.h>
 17#include <linux/pci.h>
 18#include <linux/interrupt.h>
 19#include <linux/syscore_ops.h>
 20#include <linux/adb.h>
 21#include <linux/minmax.h>
 22#include <linux/pmu.h>
 23#include <linux/irqdomain.h>
 24#include <linux/of_address.h>
 25#include <linux/of_irq.h>
 26
 27#include <asm/sections.h>
 28#include <asm/io.h>
 29#include <asm/smp.h>
 30#include <asm/pci-bridge.h>
 31#include <asm/time.h>
 32#include <asm/pmac_feature.h>
 33#include <asm/mpic.h>
 34#include <asm/xmon.h>
 35
 36#include "pmac.h"
 37
 38#ifdef CONFIG_PPC32
 39struct pmac_irq_hw {
 40        unsigned int    event;
 41        unsigned int    enable;
 42        unsigned int    ack;
 43        unsigned int    level;
 44};
 45
 46/* Workaround flags for 32bit powermac machines */
 47unsigned int of_irq_workarounds;
 48struct device_node *of_irq_dflt_pic;
 49
 50/* Default addresses */
 51static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
 52
 53static int max_irqs;
 54static int max_real_irqs;
 55
 56static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
 57
 58/* The max irq number this driver deals with is 128; see max_irqs */
 59static DECLARE_BITMAP(ppc_lost_interrupts, 128);
 60static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
 61static int pmac_irq_cascade = -1;
 62static struct irq_domain *pmac_pic_host;
 63
 64static void __pmac_retrigger(unsigned int irq_nr)
 65{
 66	if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
 67		__set_bit(irq_nr, ppc_lost_interrupts);
 68		irq_nr = pmac_irq_cascade;
 69		mb();
 70	}
 71	if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
 72		atomic_inc(&ppc_n_lost_interrupts);
 73		set_dec(1);
 74	}
 75}
 76
 77static void pmac_mask_and_ack_irq(struct irq_data *d)
 78{
 79	unsigned int src = irqd_to_hwirq(d);
 80        unsigned long bit = 1UL << (src & 0x1f);
 81        int i = src >> 5;
 82        unsigned long flags;
 83
 84	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
 85        __clear_bit(src, ppc_cached_irq_mask);
 86        if (__test_and_clear_bit(src, ppc_lost_interrupts))
 87                atomic_dec(&ppc_n_lost_interrupts);
 88        out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 89        out_le32(&pmac_irq_hw[i]->ack, bit);
 90        do {
 91                /* make sure ack gets to controller before we enable
 92                   interrupts */
 93                mb();
 94        } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 95                != (ppc_cached_irq_mask[i] & bit));
 96	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 97}
 98
 99static void pmac_ack_irq(struct irq_data *d)
100{
101	unsigned int src = irqd_to_hwirq(d);
102        unsigned long bit = 1UL << (src & 0x1f);
103        int i = src >> 5;
104        unsigned long flags;
105
106	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
107	if (__test_and_clear_bit(src, ppc_lost_interrupts))
108                atomic_dec(&ppc_n_lost_interrupts);
109        out_le32(&pmac_irq_hw[i]->ack, bit);
110        (void)in_le32(&pmac_irq_hw[i]->ack);
111	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
112}
113
114static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
115{
116        unsigned long bit = 1UL << (irq_nr & 0x1f);
117        int i = irq_nr >> 5;
118
119        if ((unsigned)irq_nr >= max_irqs)
120                return;
121
122        /* enable unmasked interrupts */
123        out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
124
125        do {
126                /* make sure mask gets to controller before we
127                   return to user */
128                mb();
129        } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
130                != (ppc_cached_irq_mask[i] & bit));
131
132        /*
133         * Unfortunately, setting the bit in the enable register
134         * when the device interrupt is already on *doesn't* set
135         * the bit in the flag register or request another interrupt.
136         */
137        if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
138		__pmac_retrigger(irq_nr);
139}
140
141/* When an irq gets requested for the first client, if it's an
142 * edge interrupt, we clear any previous one on the controller
143 */
144static unsigned int pmac_startup_irq(struct irq_data *d)
145{
146	unsigned long flags;
147	unsigned int src = irqd_to_hwirq(d);
148        unsigned long bit = 1UL << (src & 0x1f);
149        int i = src >> 5;
150
151	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
152	if (!irqd_is_level_type(d))
153		out_le32(&pmac_irq_hw[i]->ack, bit);
154        __set_bit(src, ppc_cached_irq_mask);
155        __pmac_set_irq_mask(src, 0);
156	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
157
158	return 0;
159}
160
161static void pmac_mask_irq(struct irq_data *d)
162{
163	unsigned long flags;
164	unsigned int src = irqd_to_hwirq(d);
165
166	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
167        __clear_bit(src, ppc_cached_irq_mask);
168        __pmac_set_irq_mask(src, 1);
169	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
170}
171
172static void pmac_unmask_irq(struct irq_data *d)
173{
174	unsigned long flags;
175	unsigned int src = irqd_to_hwirq(d);
176
177	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
178	__set_bit(src, ppc_cached_irq_mask);
179        __pmac_set_irq_mask(src, 0);
180	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
181}
182
183static int pmac_retrigger(struct irq_data *d)
184{
185	unsigned long flags;
186
187	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
188	__pmac_retrigger(irqd_to_hwirq(d));
189	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
190	return 1;
191}
192
193static struct irq_chip pmac_pic = {
194	.name		= "PMAC-PIC",
195	.irq_startup	= pmac_startup_irq,
196	.irq_mask	= pmac_mask_irq,
197	.irq_ack	= pmac_ack_irq,
198	.irq_mask_ack	= pmac_mask_and_ack_irq,
199	.irq_unmask	= pmac_unmask_irq,
200	.irq_retrigger	= pmac_retrigger,
201};
202
203static irqreturn_t gatwick_action(int cpl, void *dev_id)
204{
205	unsigned long flags;
206	int irq, bits;
207	int rc = IRQ_NONE;
208
209	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
210	for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
211		int i = irq >> 5;
212		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
213		bits |= in_le32(&pmac_irq_hw[i]->level);
214		bits &= ppc_cached_irq_mask[i];
215		if (bits == 0)
216			continue;
217		irq += __ilog2(bits);
218		raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
219		generic_handle_irq(irq);
220		raw_spin_lock_irqsave(&pmac_pic_lock, flags);
221		rc = IRQ_HANDLED;
222	}
223	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
224	return rc;
225}
226
227static unsigned int pmac_pic_get_irq(void)
228{
229	int irq;
230	unsigned long bits = 0;
231	unsigned long flags;
232
233#ifdef CONFIG_PPC_PMAC32_PSURGE
234	/* IPI's are a hack on the powersurge -- Cort */
235	if (smp_processor_id() != 0) {
236		return  psurge_secondary_virq;
237        }
238#endif /* CONFIG_PPC_PMAC32_PSURGE */
239	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
240	for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
241		int i = irq >> 5;
242		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
243		bits |= in_le32(&pmac_irq_hw[i]->level);
244		bits &= ppc_cached_irq_mask[i];
245		if (bits == 0)
246			continue;
247		irq += __ilog2(bits);
248		break;
249	}
250	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
251	if (unlikely(irq < 0))
252		return 0;
253	return irq_find_mapping(pmac_pic_host, irq);
254}
255
256static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node,
257			       enum irq_domain_bus_token bus_token)
258{
259	/* We match all, we don't always have a node anyway */
260	return 1;
261}
262
263static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
264			     irq_hw_number_t hw)
265{
266	if (hw >= max_irqs)
267		return -EINVAL;
268
269	/* Mark level interrupts, set delayed disable for edge ones and set
270	 * handlers
271	 */
272	irq_set_status_flags(virq, IRQ_LEVEL);
273	irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
274	return 0;
275}
276
277static const struct irq_domain_ops pmac_pic_host_ops = {
278	.match = pmac_pic_host_match,
279	.map = pmac_pic_host_map,
280	.xlate = irq_domain_xlate_onecell,
281};
282
283static void __init pmac_pic_probe_oldstyle(void)
284{
285        int i;
286        struct device_node *master = NULL;
287	struct device_node *slave = NULL;
288	u8 __iomem *addr;
289	struct resource r;
290
291	/* Set our get_irq function */
292	ppc_md.get_irq = pmac_pic_get_irq;
293
294	/*
295	 * Find the interrupt controller type & node
296	 */
297
298	if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
299		max_irqs = max_real_irqs = 32;
300	} else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
301		max_irqs = max_real_irqs = 32;
302		/* We might have a second cascaded ohare */
303		slave = of_find_node_by_name(NULL, "pci106b,7");
304		if (slave)
305			max_irqs = 64;
306	} else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
307		max_irqs = max_real_irqs = 64;
308
309		/* We might have a second cascaded heathrow */
310
311		/* Compensate for of_node_put() in of_find_node_by_name() */
312		of_node_get(master);
313		slave = of_find_node_by_name(master, "mac-io");
314
315		/* Check ordering of master & slave */
316		if (of_device_is_compatible(master, "gatwick")) {
317			BUG_ON(slave == NULL);
318			swap(master, slave);
319		}
320
321		/* We found a slave */
322		if (slave)
323			max_irqs = 128;
324	}
325	BUG_ON(master == NULL);
326
327	/*
328	 * Allocate an irq host
329	 */
330	pmac_pic_host = irq_domain_create_linear(of_fwnode_handle(master),
331						 max_irqs,
332						 &pmac_pic_host_ops, NULL);
333	BUG_ON(pmac_pic_host == NULL);
334	irq_set_default_domain(pmac_pic_host);
335
336	/* Get addresses of first controller if we have a node for it */
337	BUG_ON(of_address_to_resource(master, 0, &r));
338
339	/* Map interrupts of primary controller */
340	addr = (u8 __iomem *) ioremap(r.start, 0x40);
341	i = 0;
342	pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
343		(addr + 0x20);
344	if (max_real_irqs > 32)
345		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
346			(addr + 0x10);
347	of_node_put(master);
348
349	printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n",
350	       master, max_real_irqs);
351
352	/* Map interrupts of cascaded controller */
353	if (slave && !of_address_to_resource(slave, 0, &r)) {
354		addr = (u8 __iomem *)ioremap(r.start, 0x40);
355		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
356			(addr + 0x20);
357		if (max_irqs > 64)
358			pmac_irq_hw[i++] =
359				(volatile struct pmac_irq_hw __iomem *)
360				(addr + 0x10);
361		pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
362
363		printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs"
364		       " cascade: %d\n", slave,
365		       max_irqs - max_real_irqs, pmac_irq_cascade);
366	}
367	of_node_put(slave);
368
369	/* Disable all interrupts in all controllers */
370	for (i = 0; i * 32 < max_irqs; ++i)
371		out_le32(&pmac_irq_hw[i]->enable, 0);
372
373	/* Hookup cascade irq */
374	if (slave && pmac_irq_cascade) {
375		if (request_irq(pmac_irq_cascade, gatwick_action,
376				IRQF_NO_THREAD, "cascade", NULL))
377			pr_err("Failed to register cascade interrupt\n");
378	}
379
380	printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
381#ifdef CONFIG_XMON
382	i = irq_create_mapping(NULL, 20);
383	if (request_irq(i, xmon_irq, IRQF_NO_THREAD, "NMI - XMON", NULL))
384		pr_err("Failed to register NMI-XMON interrupt\n");
385#endif
386}
387
388int of_irq_parse_oldworld(const struct device_node *device, int index,
389			struct of_phandle_args *out_irq)
390{
391	const u32 *ints = NULL;
392	int intlen;
393
394	/*
395	 * Old machines just have a list of interrupt numbers
396	 * and no interrupt-controller nodes. We also have dodgy
397	 * cases where the APPL,interrupts property is completely
398	 * missing behind pci-pci bridges and we have to get it
399	 * from the parent (the bridge itself, as apple just wired
400	 * everything together on these)
401	 */
402	while (device) {
403		ints = of_get_property(device, "AAPL,interrupts", &intlen);
404		if (ints != NULL)
405			break;
406		device = device->parent;
407		if (!of_node_is_type(device, "pci"))
408			break;
409	}
410	if (ints == NULL)
411		return -EINVAL;
412	intlen /= sizeof(u32);
413
414	if (index >= intlen)
415		return -EINVAL;
416
417	out_irq->np = NULL;
418	out_irq->args[0] = ints[index];
419	out_irq->args_count = 1;
420
421	return 0;
422}
423#endif /* CONFIG_PPC32 */
424
425static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
426{
427#if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
428	struct device_node* pswitch;
429	int nmi_irq;
430
431	pswitch = of_find_node_by_name(NULL, "programmer-switch");
432	if (pswitch) {
433		nmi_irq = irq_of_parse_and_map(pswitch, 0);
434		if (nmi_irq) {
435			mpic_irq_set_priority(nmi_irq, 9);
436			if (request_irq(nmi_irq, xmon_irq, IRQF_NO_THREAD,
437					"NMI - XMON", NULL))
438				pr_err("Failed to register NMI-XMON interrupt\n");
439		}
440		of_node_put(pswitch);
441	}
442#endif	/* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
443}
444
445static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
446						int master)
447{
448	const char *name = master ? " MPIC 1   " : " MPIC 2   ";
449	struct mpic *mpic;
450	unsigned int flags = master ? 0 : MPIC_SECONDARY;
451
452	pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
453
454	if (of_property_read_bool(np, "big-endian"))
455		flags |= MPIC_BIG_ENDIAN;
456
457	/* Primary Big Endian means HT interrupts. This is quite dodgy
458	 * but works until I find a better way
459	 */
460	if (master && (flags & MPIC_BIG_ENDIAN))
461		flags |= MPIC_U3_HT_IRQS;
462
463	mpic = mpic_alloc(np, 0, flags, 0, 0, name);
464	if (mpic == NULL)
465		return NULL;
466
467	mpic_init(mpic);
468
469	return mpic;
470 }
471
472static int __init pmac_pic_probe_mpic(void)
473{
474	struct mpic *mpic1, *mpic2;
475	struct device_node *np, *master = NULL, *slave = NULL;
476
477	/* We can have up to 2 MPICs cascaded */
478	for_each_node_by_type(np, "open-pic") {
479		if (master == NULL && !of_property_present(np, "interrupts"))
480			master = of_node_get(np);
481		else if (slave == NULL)
482			slave = of_node_get(np);
483		if (master && slave) {
484			of_node_put(np);
485			break;
486		}
487	}
488
489	/* Check for bogus setups */
490	if (master == NULL && slave != NULL) {
491		master = slave;
492		slave = NULL;
493	}
494
495	/* Not found, default to good old pmac pic */
496	if (master == NULL)
497		return -ENODEV;
498
499	/* Set master handler */
500	ppc_md.get_irq = mpic_get_irq;
501
502	/* Setup master */
503	mpic1 = pmac_setup_one_mpic(master, 1);
504	BUG_ON(mpic1 == NULL);
505
506	/* Install NMI if any */
507	pmac_pic_setup_mpic_nmi(mpic1);
508
509	of_node_put(master);
510
511	/* Set up a cascaded controller, if present */
512	if (slave) {
513		mpic2 = pmac_setup_one_mpic(slave, 0);
514		if (mpic2 == NULL)
515			printk(KERN_ERR "Failed to setup slave MPIC\n");
516		of_node_put(slave);
517	}
518
519	return 0;
520}
521
522
523void __init pmac_pic_init(void)
524{
525	/* We configure the OF parsing based on our oldworld vs. newworld
526	 * platform type and whether we were booted by BootX.
527	 */
528#ifdef CONFIG_PPC32
529	if (!pmac_newworld)
530		of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
531	if (of_property_read_bool(of_chosen, "linux,bootx"))
532		of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
533
534	/* If we don't have phandles on a newworld, then try to locate a
535	 * default interrupt controller (happens when booting with BootX).
536	 * We do a first match here, hopefully, that only ever happens on
537	 * machines with one controller.
538	 */
539	if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
540		struct device_node *np;
541
542		for_each_node_with_property(np, "interrupt-controller") {
543			/* Skip /chosen/interrupt-controller */
544			if (of_node_name_eq(np, "chosen"))
545				continue;
546			/* It seems like at least one person wants
547			 * to use BootX on a machine with an AppleKiwi
548			 * controller which happens to pretend to be an
549			 * interrupt controller too. */
550			if (of_node_name_eq(np, "AppleKiwi"))
551				continue;
552			/* I think we found one ! */
553			of_irq_dflt_pic = np;
554			break;
555		}
556	}
557#endif /* CONFIG_PPC32 */
558
559	/* We first try to detect Apple's new Core99 chipset, since mac-io
560	 * is quite different on those machines and contains an IBM MPIC2.
561	 */
562	if (pmac_pic_probe_mpic() == 0)
563		return;
564
565#ifdef CONFIG_PPC32
566	pmac_pic_probe_oldstyle();
567#endif
568}
569
570#if defined(CONFIG_PM) && defined(CONFIG_PPC32)
571/*
572 * These procedures are used in implementing sleep on the powerbooks.
573 * sleep_save_intrs() saves the states of all interrupt enables
574 * and disables all interrupts except for the nominated one.
575 * sleep_restore_intrs() restores the states of all interrupt enables.
576 */
577unsigned long sleep_save_mask[2];
578
579/* This used to be passed by the PMU driver but that link got
580 * broken with the new driver model. We use this tweak for now...
581 * We really want to do things differently though...
582 */
583static int pmacpic_find_viaint(void)
584{
585	int viaint = -1;
586
587#ifdef CONFIG_ADB_PMU
588	struct device_node *np;
589
590	if (pmu_get_model() != PMU_OHARE_BASED)
591		goto not_found;
592	np = of_find_node_by_name(NULL, "via-pmu");
593	if (np == NULL)
594		goto not_found;
595	viaint = irq_of_parse_and_map(np, 0);
596	of_node_put(np);
597
598not_found:
599#endif /* CONFIG_ADB_PMU */
600	return viaint;
601}
602
603static int pmacpic_suspend(void *data)
604{
605	int viaint = pmacpic_find_viaint();
606
607	sleep_save_mask[0] = ppc_cached_irq_mask[0];
608	sleep_save_mask[1] = ppc_cached_irq_mask[1];
609	ppc_cached_irq_mask[0] = 0;
610	ppc_cached_irq_mask[1] = 0;
611	if (viaint > 0)
612		set_bit(viaint, ppc_cached_irq_mask);
613	out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
614	if (max_real_irqs > 32)
615		out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
616	(void)in_le32(&pmac_irq_hw[0]->event);
617	/* make sure mask gets to controller before we return to caller */
618	mb();
619        (void)in_le32(&pmac_irq_hw[0]->enable);
620
621        return 0;
622}
623
624static void pmacpic_resume(void *data)
625{
626	int i;
627
628	out_le32(&pmac_irq_hw[0]->enable, 0);
629	if (max_real_irqs > 32)
630		out_le32(&pmac_irq_hw[1]->enable, 0);
631	mb();
632	for (i = 0; i < max_real_irqs; ++i)
633		if (test_bit(i, sleep_save_mask))
634			pmac_unmask_irq(irq_get_irq_data(i));
635}
636
637static const struct syscore_ops pmacpic_syscore_ops = {
638	.suspend	= pmacpic_suspend,
639	.resume		= pmacpic_resume,
640};
641
642static struct syscore pmacpic_syscore = {
643	.ops = &pmacpic_syscore_ops,
644};
645
646static int __init init_pmacpic_syscore(void)
647{
648	if (pmac_irq_hw[0])
649		register_syscore(&pmacpic_syscore);
650	return 0;
651}
652
653machine_subsys_initcall(powermac, init_pmacpic_syscore);
654
655#endif /* CONFIG_PM && CONFIG_PPC32 */