mpc885ads_setup.c

  1/*
  2 * Platform setup for the Freescale mpc885ads board
  3 *
  4 * Vitaly Bordug <vbordug@ru.mvista.com>
  5 *
  6 * Copyright 2005 MontaVista Software Inc.
  7 *
  8 * Heavily modified by Scott Wood <scottwood@freescale.com>
  9 * Copyright 2007 Freescale Semiconductor, Inc.
 10 *
 11 * This file is licensed under the terms of the GNU General Public License
 12 * version 2. This program is licensed "as is" without any warranty of any
 13 * kind, whether express or implied.
 14 */
 15
 16#include <linux/init.h>
 17#include <linux/module.h>
 18#include <linux/param.h>
 19#include <linux/string.h>
 20#include <linux/ioport.h>
 21#include <linux/device.h>
 22#include <linux/delay.h>
 23
 24#include <linux/fsl_devices.h>
 25#include <linux/mii.h>
 26#include <linux/of_address.h>
 27#include <linux/of_fdt.h>
 28#include <linux/of_platform.h>
 29
 30#include <asm/delay.h>
 31#include <asm/io.h>
 32#include <asm/machdep.h>
 33#include <asm/page.h>
 34#include <asm/processor.h>
 35#include <asm/time.h>
 36#include <asm/8xx_immap.h>
 37#include <asm/cpm1.h>
 38#include <asm/udbg.h>
 39
 40#include "mpc885ads.h"
 41#include "mpc8xx.h"
 42#include "pic.h"
 43
 44static u32 __iomem *bcsr, *bcsr5;
 45
 46struct cpm_pin {
 47	int port, pin, flags;
 48};
 49
 50static struct cpm_pin mpc885ads_pins[] = {
 51	/* SMC1 */
 52	{CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
 53	{CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
 54
 55	/* SMC2 */
 56#ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
 57	{CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
 58	{CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
 59#endif
 60
 61	/* SCC3 */
 62	{CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
 63	{CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
 64	{CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
 65	{CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
 66	{CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
 67	{CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
 68	{CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
 69
 70	/* MII1 */
 71	{CPM_PORTA, 0, CPM_PIN_INPUT},
 72	{CPM_PORTA, 1, CPM_PIN_INPUT},
 73	{CPM_PORTA, 2, CPM_PIN_INPUT},
 74	{CPM_PORTA, 3, CPM_PIN_INPUT},
 75	{CPM_PORTA, 4, CPM_PIN_OUTPUT},
 76	{CPM_PORTA, 10, CPM_PIN_OUTPUT},
 77	{CPM_PORTA, 11, CPM_PIN_OUTPUT},
 78	{CPM_PORTB, 19, CPM_PIN_INPUT},
 79	{CPM_PORTB, 31, CPM_PIN_INPUT},
 80	{CPM_PORTC, 12, CPM_PIN_INPUT},
 81	{CPM_PORTC, 13, CPM_PIN_INPUT},
 82	{CPM_PORTE, 30, CPM_PIN_OUTPUT},
 83	{CPM_PORTE, 31, CPM_PIN_OUTPUT},
 84
 85	/* MII2 */
 86#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 87	{CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 88	{CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 89	{CPM_PORTE, 16, CPM_PIN_OUTPUT},
 90	{CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 91	{CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 92	{CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 93	{CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 94	{CPM_PORTE, 21, CPM_PIN_OUTPUT},
 95	{CPM_PORTE, 22, CPM_PIN_OUTPUT},
 96	{CPM_PORTE, 23, CPM_PIN_OUTPUT},
 97	{CPM_PORTE, 24, CPM_PIN_OUTPUT},
 98	{CPM_PORTE, 25, CPM_PIN_OUTPUT},
 99	{CPM_PORTE, 26, CPM_PIN_OUTPUT},
100	{CPM_PORTE, 27, CPM_PIN_OUTPUT},
101	{CPM_PORTE, 28, CPM_PIN_OUTPUT},
102	{CPM_PORTE, 29, CPM_PIN_OUTPUT},
103#endif
104	/* I2C */
105	{CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
106	{CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
107};
108
109static void __init init_ioports(void)
110{
111	int i;
112
113	for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
114		struct cpm_pin *pin = &mpc885ads_pins[i];
115		cpm1_set_pin(pin->port, pin->pin, pin->flags);
116	}
117
118	cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
119	cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
120	cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
121	cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
122
123	/* Set FEC1 and FEC2 to MII mode */
124	clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
125}
126
127static void __init mpc885ads_setup_arch(void)
128{
129	struct device_node *np;
130
131	cpm_reset();
132	init_ioports();
133
134	np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
135	if (!np) {
136		printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
137		return;
138	}
139
140	bcsr = of_iomap(np, 0);
141	bcsr5 = of_iomap(np, 1);
142	of_node_put(np);
143
144	if (!bcsr || !bcsr5) {
145		printk(KERN_CRIT "Could not remap BCSR\n");
146		return;
147	}
148
149	clrbits32(&bcsr[1], BCSR1_RS232EN_1);
150#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
151	setbits32(&bcsr[1], BCSR1_RS232EN_2);
152#else
153	clrbits32(&bcsr[1], BCSR1_RS232EN_2);
154#endif
155
156	clrbits32(bcsr5, BCSR5_MII1_EN);
157	setbits32(bcsr5, BCSR5_MII1_RST);
158	udelay(1000);
159	clrbits32(bcsr5, BCSR5_MII1_RST);
160
161#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
162	clrbits32(bcsr5, BCSR5_MII2_EN);
163	setbits32(bcsr5, BCSR5_MII2_RST);
164	udelay(1000);
165	clrbits32(bcsr5, BCSR5_MII2_RST);
166#else
167	setbits32(bcsr5, BCSR5_MII2_EN);
168#endif
169
170#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
171	clrbits32(&bcsr[4], BCSR4_ETH10_RST);
172	udelay(1000);
173	setbits32(&bcsr[4], BCSR4_ETH10_RST);
174
175	setbits32(&bcsr[1], BCSR1_ETHEN);
176
177	np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
178#else
179	np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
180#endif
181
182	/* The SCC3 enet registers overlap the SMC1 registers, so
183	 * one of the two must be removed from the device tree.
184	 */
185
186	if (np) {
187		of_detach_node(np);
188		of_node_put(np);
189	}
190}
191
192static const struct of_device_id of_bus_ids[] __initconst = {
193	{ .name = "soc", },
194	{ .name = "cpm", },
195	{ .name = "localbus", },
196	{},
197};
198
199static int __init declare_of_platform_devices(void)
200{
201	/* Publish the QE devices */
202	of_platform_bus_probe(NULL, of_bus_ids, NULL);
203
204	return 0;
205}
206machine_device_initcall(mpc885_ads, declare_of_platform_devices);
207
208define_machine(mpc885_ads) {
209	.name			= "Freescale MPC885 ADS",
210	.compatible		= "fsl,mpc885ads",
211	.setup_arch		= mpc885ads_setup_arch,
212	.init_IRQ		= mpc8xx_pic_init,
213	.get_irq		= mpc8xx_get_irq,
214	.restart		= mpc8xx_restart,
215	.calibrate_decr		= mpc8xx_calibrate_decr,
216	.progress		= udbg_progress,
217};