cpm1.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * General Purpose functions for the global management of the
  4 * Communication Processor Module.
  5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
  6 *
  7 * In addition to the individual control of the communication
  8 * channels, there are a few functions that globally affect the
  9 * communication processor.
 10 *
 11 * Buffer descriptors must be allocated from the dual ported memory
 12 * space.  The allocator for that is here.  When the communication
 13 * process is reset, we reclaim the memory available.  There is
 14 * currently no deallocator for this memory.
 15 * The amount of space available is platform dependent.  On the
 16 * MBX, the EPPC software loads additional microcode into the
 17 * communication processor, and uses some of the DP ram for this
 18 * purpose.  Current, the first 512 bytes and the last 256 bytes of
 19 * memory are used.  Right now I am conservative and only use the
 20 * memory that can never be used for microcode.  If there are
 21 * applications that require more DP ram, we can expand the boundaries
 22 * but then we have to be careful of any downloaded microcode.
 23 */
 24#include <linux/errno.h>
 25#include <linux/sched.h>
 26#include <linux/kernel.h>
 27#include <linux/dma-mapping.h>
 28#include <linux/param.h>
 29#include <linux/string.h>
 30#include <linux/mm.h>
 31#include <linux/interrupt.h>
 32#include <linux/irq.h>
 33#include <linux/module.h>
 34#include <linux/spinlock.h>
 35#include <linux/slab.h>
 36#include <linux/of_irq.h>
 37#include <asm/page.h>
 38#include <asm/8xx_immap.h>
 39#include <asm/cpm1.h>
 40#include <asm/io.h>
 41#include <asm/rheap.h>
 42#include <asm/cpm.h>
 43#include <asm/fixmap.h>
 44
 45#include <sysdev/fsl_soc.h>
 46
 47#ifdef CONFIG_8xx_GPIO
 48#include <linux/gpio/driver.h>
 49#endif
 50
 51#define CPM_MAP_SIZE    (0x4000)
 52
 53cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
 54immap_t __iomem *mpc8xx_immr = (void __iomem *)VIRT_IMMR_BASE;
 55
 56void __init cpm_reset(void)
 57{
 58	cpmp = &mpc8xx_immr->im_cpm;
 59
 60#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 61	/* Perform a reset. */
 62	out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 63
 64	/* Wait for it. */
 65	while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 66#endif
 67
 68#ifdef CONFIG_UCODE_PATCH
 69	cpm_load_patch(cpmp);
 70#endif
 71
 72	/*
 73	 * Set SDMA Bus Request priority 5.
 74	 * On 860T, this also enables FEC priority 6.  I am not sure
 75	 * this is what we really want for some applications, but the
 76	 * manual recommends it.
 77	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 78	 */
 79	if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
 80		out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 0x40);
 81	else
 82		out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 1);
 83}
 84
 85static DEFINE_SPINLOCK(cmd_lock);
 86
 87#define MAX_CR_CMD_LOOPS        10000
 88
 89int cpm_command(u32 command, u8 opcode)
 90{
 91	int i, ret;
 92	unsigned long flags;
 93
 94	if (command & 0xffffff03)
 95		return -EINVAL;
 96
 97	spin_lock_irqsave(&cmd_lock, flags);
 98
 99	ret = 0;
100	out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
101	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
102		if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
103			goto out;
104
105	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
106	ret = -EIO;
107out:
108	spin_unlock_irqrestore(&cmd_lock, flags);
109	return ret;
110}
111EXPORT_SYMBOL(cpm_command);
112
113/*
114 * Set a baud rate generator.  This needs lots of work.  There are
115 * four BRGs, any of which can be wired to any channel.
116 * The internal baud rate clock is the system clock divided by 16.
117 * This assumes the baudrate is 16x oversampled by the uart.
118 */
119#define BRG_INT_CLK		(get_brgfreq())
120#define BRG_UART_CLK		(BRG_INT_CLK/16)
121#define BRG_UART_CLK_DIV16	(BRG_UART_CLK/16)
122
123void
124cpm_setbrg(uint brg, uint rate)
125{
126	u32 __iomem *bp;
127
128	/* This is good enough to get SMCs running..... */
129	bp = &cpmp->cp_brgc1;
130	bp += brg;
131	/*
132	 * The BRG has a 12-bit counter.  For really slow baud rates (or
133	 * really fast processors), we may have to further divide by 16.
134	 */
135	if (((BRG_UART_CLK / rate) - 1) < 4096)
136		out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
137	else
138		out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
139			      CPM_BRG_EN | CPM_BRG_DIV16);
140}
141EXPORT_SYMBOL(cpm_setbrg);
142
143struct cpm_ioport16 {
144	__be16 dir, par, odr_sor, dat, intr;
145	__be16 res[3];
146};
147
148struct cpm_ioport32b {
149	__be32 dir, par, odr, dat;
150};
151
152struct cpm_ioport32e {
153	__be32 dir, par, sor, odr, dat;
154};
155
156static void __init cpm1_set_pin32(int port, int pin, int flags)
157{
158	struct cpm_ioport32e __iomem *iop;
159	pin = 1 << (31 - pin);
160
161	if (port == CPM_PORTB)
162		iop = (struct cpm_ioport32e __iomem *)
163		      &mpc8xx_immr->im_cpm.cp_pbdir;
164	else
165		iop = (struct cpm_ioport32e __iomem *)
166		      &mpc8xx_immr->im_cpm.cp_pedir;
167
168	if (flags & CPM_PIN_OUTPUT)
169		setbits32(&iop->dir, pin);
170	else
171		clrbits32(&iop->dir, pin);
172
173	if (!(flags & CPM_PIN_GPIO))
174		setbits32(&iop->par, pin);
175	else
176		clrbits32(&iop->par, pin);
177
178	if (port == CPM_PORTB) {
179		if (flags & CPM_PIN_OPENDRAIN)
180			setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
181		else
182			clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
183	}
184
185	if (port == CPM_PORTE) {
186		if (flags & CPM_PIN_SECONDARY)
187			setbits32(&iop->sor, pin);
188		else
189			clrbits32(&iop->sor, pin);
190
191		if (flags & CPM_PIN_OPENDRAIN)
192			setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
193		else
194			clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
195	}
196}
197
198static void __init cpm1_set_pin16(int port, int pin, int flags)
199{
200	struct cpm_ioport16 __iomem *iop =
201		(struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
202
203	pin = 1 << (15 - pin);
204
205	if (port != 0)
206		iop += port - 1;
207
208	if (flags & CPM_PIN_OUTPUT)
209		setbits16(&iop->dir, pin);
210	else
211		clrbits16(&iop->dir, pin);
212
213	if (!(flags & CPM_PIN_GPIO))
214		setbits16(&iop->par, pin);
215	else
216		clrbits16(&iop->par, pin);
217
218	if (port == CPM_PORTA) {
219		if (flags & CPM_PIN_OPENDRAIN)
220			setbits16(&iop->odr_sor, pin);
221		else
222			clrbits16(&iop->odr_sor, pin);
223	}
224	if (port == CPM_PORTC) {
225		if (flags & CPM_PIN_SECONDARY)
226			setbits16(&iop->odr_sor, pin);
227		else
228			clrbits16(&iop->odr_sor, pin);
229		if (flags & CPM_PIN_FALLEDGE)
230			setbits16(&iop->intr, pin);
231		else
232			clrbits16(&iop->intr, pin);
233	}
234}
235
236void __init cpm1_set_pin(enum cpm_port port, int pin, int flags)
237{
238	if (port == CPM_PORTB || port == CPM_PORTE)
239		cpm1_set_pin32(port, pin, flags);
240	else
241		cpm1_set_pin16(port, pin, flags);
242}
243
244int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
245{
246	int shift;
247	int i, bits = 0;
248	u32 __iomem *reg;
249	u32 mask = 7;
250
251	u8 clk_map[][3] = {
252		{CPM_CLK_SCC1, CPM_BRG1, 0},
253		{CPM_CLK_SCC1, CPM_BRG2, 1},
254		{CPM_CLK_SCC1, CPM_BRG3, 2},
255		{CPM_CLK_SCC1, CPM_BRG4, 3},
256		{CPM_CLK_SCC1, CPM_CLK1, 4},
257		{CPM_CLK_SCC1, CPM_CLK2, 5},
258		{CPM_CLK_SCC1, CPM_CLK3, 6},
259		{CPM_CLK_SCC1, CPM_CLK4, 7},
260
261		{CPM_CLK_SCC2, CPM_BRG1, 0},
262		{CPM_CLK_SCC2, CPM_BRG2, 1},
263		{CPM_CLK_SCC2, CPM_BRG3, 2},
264		{CPM_CLK_SCC2, CPM_BRG4, 3},
265		{CPM_CLK_SCC2, CPM_CLK1, 4},
266		{CPM_CLK_SCC2, CPM_CLK2, 5},
267		{CPM_CLK_SCC2, CPM_CLK3, 6},
268		{CPM_CLK_SCC2, CPM_CLK4, 7},
269
270		{CPM_CLK_SCC3, CPM_BRG1, 0},
271		{CPM_CLK_SCC3, CPM_BRG2, 1},
272		{CPM_CLK_SCC3, CPM_BRG3, 2},
273		{CPM_CLK_SCC3, CPM_BRG4, 3},
274		{CPM_CLK_SCC3, CPM_CLK5, 4},
275		{CPM_CLK_SCC3, CPM_CLK6, 5},
276		{CPM_CLK_SCC3, CPM_CLK7, 6},
277		{CPM_CLK_SCC3, CPM_CLK8, 7},
278
279		{CPM_CLK_SCC4, CPM_BRG1, 0},
280		{CPM_CLK_SCC4, CPM_BRG2, 1},
281		{CPM_CLK_SCC4, CPM_BRG3, 2},
282		{CPM_CLK_SCC4, CPM_BRG4, 3},
283		{CPM_CLK_SCC4, CPM_CLK5, 4},
284		{CPM_CLK_SCC4, CPM_CLK6, 5},
285		{CPM_CLK_SCC4, CPM_CLK7, 6},
286		{CPM_CLK_SCC4, CPM_CLK8, 7},
287
288		{CPM_CLK_SMC1, CPM_BRG1, 0},
289		{CPM_CLK_SMC1, CPM_BRG2, 1},
290		{CPM_CLK_SMC1, CPM_BRG3, 2},
291		{CPM_CLK_SMC1, CPM_BRG4, 3},
292		{CPM_CLK_SMC1, CPM_CLK1, 4},
293		{CPM_CLK_SMC1, CPM_CLK2, 5},
294		{CPM_CLK_SMC1, CPM_CLK3, 6},
295		{CPM_CLK_SMC1, CPM_CLK4, 7},
296
297		{CPM_CLK_SMC2, CPM_BRG1, 0},
298		{CPM_CLK_SMC2, CPM_BRG2, 1},
299		{CPM_CLK_SMC2, CPM_BRG3, 2},
300		{CPM_CLK_SMC2, CPM_BRG4, 3},
301		{CPM_CLK_SMC2, CPM_CLK5, 4},
302		{CPM_CLK_SMC2, CPM_CLK6, 5},
303		{CPM_CLK_SMC2, CPM_CLK7, 6},
304		{CPM_CLK_SMC2, CPM_CLK8, 7},
305	};
306
307	switch (target) {
308	case CPM_CLK_SCC1:
309		reg = &mpc8xx_immr->im_cpm.cp_sicr;
310		shift = 0;
311		break;
312
313	case CPM_CLK_SCC2:
314		reg = &mpc8xx_immr->im_cpm.cp_sicr;
315		shift = 8;
316		break;
317
318	case CPM_CLK_SCC3:
319		reg = &mpc8xx_immr->im_cpm.cp_sicr;
320		shift = 16;
321		break;
322
323	case CPM_CLK_SCC4:
324		reg = &mpc8xx_immr->im_cpm.cp_sicr;
325		shift = 24;
326		break;
327
328	case CPM_CLK_SMC1:
329		reg = &mpc8xx_immr->im_cpm.cp_simode;
330		shift = 12;
331		break;
332
333	case CPM_CLK_SMC2:
334		reg = &mpc8xx_immr->im_cpm.cp_simode;
335		shift = 28;
336		break;
337
338	default:
339		printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
340		return -EINVAL;
341	}
342
343	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
344		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
345			bits = clk_map[i][2];
346			break;
347		}
348	}
349
350	if (i == ARRAY_SIZE(clk_map)) {
351		printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
352		return -EINVAL;
353	}
354
355	bits <<= shift;
356	mask <<= shift;
357
358	if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
359		if (mode == CPM_CLK_RTX) {
360			bits |= bits << 3;
361			mask |= mask << 3;
362		} else if (mode == CPM_CLK_RX) {
363			bits <<= 3;
364			mask <<= 3;
365		}
366	}
367
368	out_be32(reg, (in_be32(reg) & ~mask) | bits);
369
370	return 0;
371}
372
373/*
374 * GPIO LIB API implementation
375 */
376#ifdef CONFIG_8xx_GPIO
377
378struct cpm1_gpio16_chip {
379	struct gpio_chip gc;
380	void __iomem *regs;
381	spinlock_t lock;
382
383	/* shadowed data register to clear/set bits safely */
384	u16 cpdata;
385
386	/* IRQ associated with Pins when relevant */
387	int irq[16];
388};
389
390static void cpm1_gpio16_save_regs(struct cpm1_gpio16_chip *cpm1_gc)
391{
392	struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
393
394	cpm1_gc->cpdata = in_be16(&iop->dat);
395}
396
397static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
398{
399	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
400	struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
401	u16 pin_mask;
402
403	pin_mask = 1 << (15 - gpio);
404
405	return !!(in_be16(&iop->dat) & pin_mask);
406}
407
408static void __cpm1_gpio16_set(struct cpm1_gpio16_chip *cpm1_gc, u16 pin_mask, int value)
409{
410	struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
411
412	if (value)
413		cpm1_gc->cpdata |= pin_mask;
414	else
415		cpm1_gc->cpdata &= ~pin_mask;
416
417	out_be16(&iop->dat, cpm1_gc->cpdata);
418}
419
420static int cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
421{
422	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
423	unsigned long flags;
424	u16 pin_mask = 1 << (15 - gpio);
425
426	spin_lock_irqsave(&cpm1_gc->lock, flags);
427
428	__cpm1_gpio16_set(cpm1_gc, pin_mask, value);
429
430	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
431
432	return 0;
433}
434
435static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
436{
437	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
438
439	return cpm1_gc->irq[gpio] ? : -ENXIO;
440}
441
442static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
443{
444	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
445	struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
446	unsigned long flags;
447	u16 pin_mask = 1 << (15 - gpio);
448
449	spin_lock_irqsave(&cpm1_gc->lock, flags);
450
451	setbits16(&iop->dir, pin_mask);
452	__cpm1_gpio16_set(cpm1_gc, pin_mask, val);
453
454	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
455
456	return 0;
457}
458
459static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
460{
461	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
462	struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
463	unsigned long flags;
464	u16 pin_mask = 1 << (15 - gpio);
465
466	spin_lock_irqsave(&cpm1_gc->lock, flags);
467
468	clrbits16(&iop->dir, pin_mask);
469
470	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
471
472	return 0;
473}
474
475int cpm1_gpiochip_add16(struct device *dev)
476{
477	struct device_node *np = dev->of_node;
478	struct cpm1_gpio16_chip *cpm1_gc;
479	struct gpio_chip *gc;
480	u16 mask;
481
482	cpm1_gc = devm_kzalloc(dev, sizeof(*cpm1_gc), GFP_KERNEL);
483	if (!cpm1_gc)
484		return -ENOMEM;
485
486	spin_lock_init(&cpm1_gc->lock);
487
488	if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
489		int i, j;
490
491		for (i = 0, j = 0; i < 16; i++)
492			if (mask & (1 << (15 - i)))
493				cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
494	}
495
496	gc = &cpm1_gc->gc;
497	gc->base = -1;
498	gc->ngpio = 16;
499	gc->direction_input = cpm1_gpio16_dir_in;
500	gc->direction_output = cpm1_gpio16_dir_out;
501	gc->get = cpm1_gpio16_get;
502	gc->set = cpm1_gpio16_set;
503	gc->to_irq = cpm1_gpio16_to_irq;
504	gc->parent = dev;
505	gc->owner = THIS_MODULE;
506
507	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
508	if (!gc->label)
509		return -ENOMEM;
510
511	cpm1_gc->regs = devm_of_iomap(dev, np, 0, NULL);
512	if (IS_ERR(cpm1_gc->regs))
513		return PTR_ERR(cpm1_gc->regs);
514
515	cpm1_gpio16_save_regs(cpm1_gc);
516
517	return devm_gpiochip_add_data(dev, gc, cpm1_gc);
518}
519
520struct cpm1_gpio32_chip {
521	struct gpio_chip gc;
522	void __iomem *regs;
523	spinlock_t lock;
524
525	/* shadowed data register to clear/set bits safely */
526	u32 cpdata;
527};
528
529static void cpm1_gpio32_save_regs(struct cpm1_gpio32_chip *cpm1_gc)
530{
531	struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
532
533	cpm1_gc->cpdata = in_be32(&iop->dat);
534}
535
536static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
537{
538	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
539	struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
540	u32 pin_mask;
541
542	pin_mask = 1 << (31 - gpio);
543
544	return !!(in_be32(&iop->dat) & pin_mask);
545}
546
547static void __cpm1_gpio32_set(struct cpm1_gpio32_chip *cpm1_gc, u32 pin_mask, int value)
548{
549	struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
550
551	if (value)
552		cpm1_gc->cpdata |= pin_mask;
553	else
554		cpm1_gc->cpdata &= ~pin_mask;
555
556	out_be32(&iop->dat, cpm1_gc->cpdata);
557}
558
559static int cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
560{
561	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
562	unsigned long flags;
563	u32 pin_mask = 1 << (31 - gpio);
564
565	spin_lock_irqsave(&cpm1_gc->lock, flags);
566
567	__cpm1_gpio32_set(cpm1_gc, pin_mask, value);
568
569	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
570
571	return 0;
572}
573
574static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
575{
576	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
577	struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
578	unsigned long flags;
579	u32 pin_mask = 1 << (31 - gpio);
580
581	spin_lock_irqsave(&cpm1_gc->lock, flags);
582
583	setbits32(&iop->dir, pin_mask);
584	__cpm1_gpio32_set(cpm1_gc, pin_mask, val);
585
586	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
587
588	return 0;
589}
590
591static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
592{
593	struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
594	struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
595	unsigned long flags;
596	u32 pin_mask = 1 << (31 - gpio);
597
598	spin_lock_irqsave(&cpm1_gc->lock, flags);
599
600	clrbits32(&iop->dir, pin_mask);
601
602	spin_unlock_irqrestore(&cpm1_gc->lock, flags);
603
604	return 0;
605}
606
607int cpm1_gpiochip_add32(struct device *dev)
608{
609	struct device_node *np = dev->of_node;
610	struct cpm1_gpio32_chip *cpm1_gc;
611	struct gpio_chip *gc;
612
613	cpm1_gc = devm_kzalloc(dev, sizeof(*cpm1_gc), GFP_KERNEL);
614	if (!cpm1_gc)
615		return -ENOMEM;
616
617	spin_lock_init(&cpm1_gc->lock);
618
619	gc = &cpm1_gc->gc;
620	gc->base = -1;
621	gc->ngpio = 32;
622	gc->direction_input = cpm1_gpio32_dir_in;
623	gc->direction_output = cpm1_gpio32_dir_out;
624	gc->get = cpm1_gpio32_get;
625	gc->set = cpm1_gpio32_set;
626	gc->parent = dev;
627	gc->owner = THIS_MODULE;
628
629	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
630	if (!gc->label)
631		return -ENOMEM;
632
633	cpm1_gc->regs = devm_of_iomap(dev, np, 0, NULL);
634	if (IS_ERR(cpm1_gc->regs))
635		return PTR_ERR(cpm1_gc->regs);
636
637	cpm1_gpio32_save_regs(cpm1_gc);
638
639	return devm_gpiochip_add_data(dev, gc, cpm1_gc);
640}
641
642#endif /* CONFIG_8xx_GPIO */