twr_p102x.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
  4 *
  5 * Author: Michael Johnston <michael.johnston@freescale.com>
  6 *
  7 * Description:
  8 * TWR-P102x Board Setup
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13#include <linux/errno.h>
 14#include <linux/fsl/guts.h>
 15#include <linux/pci.h>
 16#include <linux/of.h>
 17#include <linux/of_address.h>
 18
 19#include <asm/pci-bridge.h>
 20#include <asm/udbg.h>
 21#include <asm/mpic.h>
 22#include <soc/fsl/qe/qe.h>
 23
 24#include <sysdev/fsl_soc.h>
 25#include <sysdev/fsl_pci.h>
 26#include "smp.h"
 27
 28#include "mpc85xx.h"
 29
 30static void __init twr_p1025_pic_init(void)
 31{
 32	struct mpic *mpic;
 33
 34	mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
 35			MPIC_SINGLE_DEST_CPU,
 36			0, 256, " OpenPIC  ");
 37
 38	BUG_ON(mpic == NULL);
 39	mpic_init(mpic);
 40}
 41
 42/* ************************************************************************
 43 *
 44 * Setup the architecture
 45 *
 46 */
 47static void __init twr_p1025_setup_arch(void)
 48{
 49	if (ppc_md.progress)
 50		ppc_md.progress("twr_p1025_setup_arch()", 0);
 51
 52	mpc85xx_smp_init();
 53
 54	fsl_pci_assign_primary();
 55
 56#ifdef CONFIG_QUICC_ENGINE
 57	mpc85xx_qe_par_io_init();
 58
 59#if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
 60	if (machine_is(twr_p1025)) {
 61		struct ccsr_guts __iomem *guts;
 62		struct device_node *np;
 63
 64		np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
 65		if (np) {
 66			guts = of_iomap(np, 0);
 67			if (!guts)
 68				pr_err("twr_p1025: could not map global utilities register\n");
 69			else {
 70			/* P1025 has pins muxed for QE and other functions. To
 71			 * enable QE UEC mode, we need to set bit QE0 for UCC1
 72			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
 73			 * and QE12 for QE MII management signals in PMUXCR
 74			 * register.
 75			 * Set QE mux bits in PMUXCR */
 76			setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
 77					MPC85xx_PMUXCR_QE(3) |
 78					MPC85xx_PMUXCR_QE(9) |
 79					MPC85xx_PMUXCR_QE(12));
 80			iounmap(guts);
 81
 82#if IS_ENABLED(CONFIG_SERIAL_QE)
 83			/* On P1025TWR board, the UCC7 acted as UART port.
 84			 * However, The UCC7's CTS pin is low level in default,
 85			 * it will impact the transmission in full duplex
 86			 * communication. So disable the Flow control pin PA18.
 87			 * The UCC7 UART just can use RXD and TXD pins.
 88			 */
 89			par_io_config_pin(0, 18, 0, 0, 0, 0);
 90#endif
 91			/* Drive PB29 to CPLD low - CPLD will then change
 92			 * muxing from LBC to QE */
 93			par_io_config_pin(1, 29, 1, 0, 0, 0);
 94			par_io_data_set(1, 29, 0);
 95			}
 96			of_node_put(np);
 97		}
 98	}
 99#endif
100#endif	/* CONFIG_QUICC_ENGINE */
101
102	pr_info("TWR-P1025 board from Freescale Semiconductor\n");
103}
104
105machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
106
107define_machine(twr_p1025) {
108	.name			= "TWR-P1025",
109	.compatible		= "fsl,TWR-P1025",
110	.setup_arch		= twr_p1025_setup_arch,
111	.init_IRQ		= twr_p1025_pic_init,
112#ifdef CONFIG_PCI
113	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
114#endif
115	.get_irq		= mpic_get_irq,
116	.progress		= udbg_progress,
117};