media5200.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Support for 'media5200-platform' compatible boards.
  4 *
  5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6 *
  7 * Description:
  8 * This code implements support for the Freescape Media5200 platform
  9 * (built around the MPC5200 SoC).
 10 *
 11 * Notable characteristic of the Media5200 is the presence of an FPGA
 12 * that has all external IRQ lines routed through it.  This file implements
 13 * a cascaded interrupt controller driver which attaches itself to the
 14 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
 15 * is initialized.
 16 */
 17
 18#undef DEBUG
 19
 20#include <linux/irq.h>
 21#include <linux/interrupt.h>
 22#include <linux/io.h>
 23#include <linux/of_address.h>
 24#include <linux/of_irq.h>
 25#include <asm/time.h>
 26#include <asm/machdep.h>
 27#include <asm/mpc52xx.h>
 28
 29static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
 30	{ .compatible = "fsl,mpc5200-gpio", },
 31	{ .compatible = "mpc5200-gpio", },
 32	{}
 33};
 34
 35/* FPGA register set */
 36#define MEDIA5200_IRQ_ENABLE (0x40c)
 37#define MEDIA5200_IRQ_STATUS (0x410)
 38#define MEDIA5200_NUM_IRQS   (6)
 39#define MEDIA5200_IRQ_SHIFT  (32 - MEDIA5200_NUM_IRQS)
 40
 41struct media5200_irq {
 42	void __iomem *regs;
 43	spinlock_t lock;
 44	struct irq_domain *irqhost;
 45};
 46struct media5200_irq media5200_irq;
 47
 48static void media5200_irq_unmask(struct irq_data *d)
 49{
 50	unsigned long flags;
 51	u32 val;
 52
 53	spin_lock_irqsave(&media5200_irq.lock, flags);
 54	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
 55	val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
 56	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
 57	spin_unlock_irqrestore(&media5200_irq.lock, flags);
 58}
 59
 60static void media5200_irq_mask(struct irq_data *d)
 61{
 62	unsigned long flags;
 63	u32 val;
 64
 65	spin_lock_irqsave(&media5200_irq.lock, flags);
 66	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
 67	val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
 68	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
 69	spin_unlock_irqrestore(&media5200_irq.lock, flags);
 70}
 71
 72static struct irq_chip media5200_irq_chip = {
 73	.name = "Media5200 FPGA",
 74	.irq_unmask = media5200_irq_unmask,
 75	.irq_mask = media5200_irq_mask,
 76	.irq_mask_ack = media5200_irq_mask,
 77};
 78
 79static void media5200_irq_cascade(struct irq_desc *desc)
 80{
 81	struct irq_chip *chip = irq_desc_get_chip(desc);
 82	int val;
 83	u32 status, enable;
 84
 85	/* Mask off the cascaded IRQ */
 86	raw_spin_lock(&desc->lock);
 87	chip->irq_mask(&desc->irq_data);
 88	raw_spin_unlock(&desc->lock);
 89
 90	/* Ask the FPGA for IRQ status.  If 'val' is 0, then no irqs
 91	 * are pending.  'ffs()' is 1 based */
 92	status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
 93	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
 94	val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
 95	if (val) {
 96		generic_handle_domain_irq(media5200_irq.irqhost, val - 1);
 97		/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i\n",
 98		 *          __func__, virq, status, enable, val - 1);
 99		 */
100	}
101
102	/* Processing done; can reenable the cascade now */
103	raw_spin_lock(&desc->lock);
104	chip->irq_ack(&desc->irq_data);
105	if (!irqd_irq_disabled(&desc->irq_data))
106		chip->irq_unmask(&desc->irq_data);
107	raw_spin_unlock(&desc->lock);
108}
109
110static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
111			     irq_hw_number_t hw)
112{
113	pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
114	irq_set_chip_data(virq, &media5200_irq);
115	irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
116	irq_set_status_flags(virq, IRQ_LEVEL);
117	return 0;
118}
119
120static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct,
121				 const u32 *intspec, unsigned int intsize,
122				 irq_hw_number_t *out_hwirq,
123				 unsigned int *out_flags)
124{
125	if (intsize != 2)
126		return -1;
127
128	pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
129	*out_hwirq = intspec[1];
130	*out_flags = IRQ_TYPE_NONE;
131	return 0;
132}
133
134static const struct irq_domain_ops media5200_irq_ops = {
135	.map = media5200_irq_map,
136	.xlate = media5200_irq_xlate,
137};
138
139/*
140 * Setup Media5200 IRQ mapping
141 */
142static void __init media5200_init_irq(void)
143{
144	struct device_node *fpga_np;
145	int cascade_virq;
146
147	/* First setup the regular MPC5200 interrupt controller */
148	mpc52xx_init_irq();
149
150	/* Now find the FPGA IRQ */
151	fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
152	if (!fpga_np)
153		goto out;
154	pr_debug("%s: found fpga node: %pOF\n", __func__, fpga_np);
155
156	media5200_irq.regs = of_iomap(fpga_np, 0);
157	if (!media5200_irq.regs)
158		goto out;
159	pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
160
161	cascade_virq = irq_of_parse_and_map(fpga_np, 0);
162	if (!cascade_virq)
163		goto out;
164	pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
165
166	/* Disable all FPGA IRQs */
167	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
168
169	spin_lock_init(&media5200_irq.lock);
170
171	media5200_irq.irqhost = irq_domain_create_linear(of_fwnode_handle(fpga_np),
172			MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
173	if (!media5200_irq.irqhost)
174		goto out;
175	pr_debug("%s: allocated irqhost\n", __func__);
176
177	of_node_put(fpga_np);
178
179	irq_set_handler_data(cascade_virq, &media5200_irq);
180	irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
181
182	return;
183
184 out:
185	pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
186	of_node_put(fpga_np);
187}
188
189/*
190 * Setup the architecture
191 */
192static void __init media5200_setup_arch(void)
193{
194
195	struct device_node *np;
196	struct mpc52xx_gpio __iomem *gpio;
197	u32 port_config;
198
199	if (ppc_md.progress)
200		ppc_md.progress("media5200_setup_arch()", 0);
201
202	/* Map important registers from the internal memory map */
203	mpc52xx_map_common_devices();
204
205	/* Some mpc5200 & mpc5200b related configuration */
206	mpc5200_setup_xlb_arbiter();
207
208	np = of_find_matching_node(NULL, mpc5200_gpio_ids);
209	gpio = of_iomap(np, 0);
210	of_node_put(np);
211	if (!gpio) {
212		printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
213		       __func__);
214		return;
215	}
216
217	/* Set port config */
218	port_config = in_be32(&gpio->port_config);
219
220	port_config &= ~0x03000000;	/* ATA CS is on csb_4/5		*/
221	port_config |=  0x01000000;
222
223	out_be32(&gpio->port_config, port_config);
224
225	/* Unmap zone */
226	iounmap(gpio);
227
228}
229
230define_machine(media5200_platform) {
231	.name		= "media5200-platform",
232	.compatible	= "fsl,media5200",
233	.setup_arch	= media5200_setup_arch,
234	.discover_phbs	= mpc52xx_setup_pci,
235	.init		= mpc52xx_declare_of_platform_devices,
236	.init_IRQ	= media5200_init_irq,
237	.get_irq	= mpc52xx_get_irq,
238	.restart	= mpc52xx_restart,
239};