core-book3s.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Performance event support - powerpc architecture code
   4 *
   5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   6 */
   7#include <linux/kernel.h>
   8#include <linux/sched.h>
   9#include <linux/sched/clock.h>
  10#include <linux/perf_event.h>
  11#include <linux/percpu.h>
  12#include <linux/hardirq.h>
  13#include <linux/uaccess.h>
  14#include <asm/reg.h>
  15#include <asm/pmc.h>
  16#include <asm/machdep.h>
  17#include <asm/firmware.h>
  18#include <asm/ptrace.h>
  19#include <asm/text-patching.h>
  20#include <asm/hw_irq.h>
  21#include <asm/interrupt.h>
  22
  23#ifdef CONFIG_PPC64
  24#include "internal.h"
  25#endif
  26
  27#define BHRB_MAX_ENTRIES	32
  28#define BHRB_TARGET		0x0000000000000002
  29#define BHRB_PREDICTION		0x0000000000000001
  30#define BHRB_EA			0xFFFFFFFFFFFFFFFCUL
  31
  32struct cpu_hw_events {
  33	int n_events;
  34	int n_percpu;
  35	int disabled;
  36	int n_added;
  37	int n_limited;
  38	u8  pmcs_enabled;
  39	struct perf_event *event[MAX_HWEVENTS];
  40	u64 events[MAX_HWEVENTS];
  41	unsigned int flags[MAX_HWEVENTS];
  42	struct mmcr_regs mmcr;
  43	struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
  44	u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
  45	u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
  46	unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
  47	unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
  48
  49	unsigned int txn_flags;
  50	int n_txn_start;
  51
  52	/* BHRB bits */
  53	u64				bhrb_filter;	/* BHRB HW branch filter */
  54	unsigned int			bhrb_users;
  55	void				*bhrb_context;
  56	struct	perf_branch_stack	bhrb_stack;
  57	struct	perf_branch_entry	bhrb_entries[BHRB_MAX_ENTRIES];
  58	u64				ic_init;
  59
  60	/* Store the PMC values */
  61	unsigned long pmcs[MAX_HWEVENTS];
  62};
  63
  64static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  65
  66static struct power_pmu *ppmu;
  67
  68/*
  69 * Normally, to ignore kernel events we set the FCS (freeze counters
  70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
  71 * hypervisor bit set in the MSR, or if we are running on a processor
  72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
  73 * then we need to use the FCHV bit to ignore kernel events.
  74 */
  75static unsigned int freeze_events_kernel = MMCR0_FCS;
  76
  77/*
  78 * 32-bit doesn't have MMCRA but does have an MMCR2,
  79 * and a few other names are different.
  80 * Also 32-bit doesn't have MMCR3, SIER2 and SIER3.
  81 * Define them as zero knowing that any code path accessing
  82 * these registers (via mtspr/mfspr) are done under ppmu flag
  83 * check for PPMU_ARCH_31 and we will not enter that code path
  84 * for 32-bit.
  85 */
  86#ifdef CONFIG_PPC32
  87
  88#define MMCR0_FCHV		0
  89#define MMCR0_PMCjCE		MMCR0_PMCnCE
  90#define MMCR0_FC56		0
  91#define MMCR0_PMAO		0
  92#define MMCR0_EBE		0
  93#define MMCR0_BHRBA		0
  94#define MMCR0_PMCC		0
  95#define MMCR0_PMCC_U6		0
  96
  97#define SPRN_MMCRA		SPRN_MMCR2
  98#define SPRN_MMCR3		0
  99#define SPRN_SIER2		0
 100#define SPRN_SIER3		0
 101#define MMCRA_SAMPLE_ENABLE	0
 102#define MMCRA_BHRB_DISABLE     0
 103#define MMCR0_PMCCEXT		0
 104
 105static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 106{
 107	return 0;
 108}
 109static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { }
 110static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 111{
 112	return 0;
 113}
 114static inline void perf_read_regs(struct pt_regs *regs)
 115{
 116	regs->result = 0;
 117}
 118
 119static inline int siar_valid(struct pt_regs *regs)
 120{
 121	return 1;
 122}
 123
 124static bool is_ebb_event(struct perf_event *event) { return false; }
 125static int ebb_event_check(struct perf_event *event) { return 0; }
 126static void ebb_event_add(struct perf_event *event) { }
 127static void ebb_switch_out(unsigned long mmcr0) { }
 128static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
 129{
 130	return cpuhw->mmcr.mmcr0;
 131}
 132
 133static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
 134static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
 135static void power_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
 136				 struct task_struct *task, bool sched_in)
 137{
 138}
 139static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {}
 140static void pmao_restore_workaround(bool ebb) { }
 141#endif /* CONFIG_PPC32 */
 142
 143bool is_sier_available(void)
 144{
 145	if (!ppmu)
 146		return false;
 147
 148	if (ppmu->flags & PPMU_HAS_SIER)
 149		return true;
 150
 151	return false;
 152}
 153
 154/*
 155 * Return PMC value corresponding to the
 156 * index passed.
 157 */
 158unsigned long get_pmcs_ext_regs(int idx)
 159{
 160	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
 161
 162	return cpuhw->pmcs[idx];
 163}
 164
 165static bool regs_use_siar(struct pt_regs *regs)
 166{
 167	/*
 168	 * When we take a performance monitor exception the regs are setup
 169	 * using perf_read_regs() which overloads some fields, in particular
 170	 * regs->result to tell us whether to use SIAR.
 171	 *
 172	 * However if the regs are from another exception, eg. a syscall, then
 173	 * they have not been setup using perf_read_regs() and so regs->result
 174	 * is something random.
 175	 */
 176	return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result);
 177}
 178
 179/*
 180 * Things that are specific to 64-bit implementations.
 181 */
 182#ifdef CONFIG_PPC64
 183
 184static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 185{
 186	unsigned long mmcra = regs->dsisr;
 187
 188	if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
 189		unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
 190		if (slot > 1)
 191			return 4 * (slot - 1);
 192	}
 193
 194	return 0;
 195}
 196
 197/*
 198 * The user wants a data address recorded.
 199 * If we're not doing instruction sampling, give them the SDAR
 200 * (sampled data address).  If we are doing instruction sampling, then
 201 * only give them the SDAR if it corresponds to the instruction
 202 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
 203 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
 204 */
 205static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp)
 206{
 207	unsigned long mmcra = regs->dsisr;
 208	bool sdar_valid;
 209
 210	if (ppmu->flags & PPMU_HAS_SIER)
 211		sdar_valid = regs->dar & SIER_SDAR_VALID;
 212	else {
 213		unsigned long sdsync;
 214
 215		if (ppmu->flags & PPMU_SIAR_VALID)
 216			sdsync = POWER7P_MMCRA_SDAR_VALID;
 217		else if (ppmu->flags & PPMU_ALT_SIPR)
 218			sdsync = POWER6_MMCRA_SDSYNC;
 219		else if (ppmu->flags & PPMU_NO_SIAR)
 220			sdsync = MMCRA_SAMPLE_ENABLE;
 221		else
 222			sdsync = MMCRA_SDSYNC;
 223
 224		sdar_valid = mmcra & sdsync;
 225	}
 226
 227	if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
 228		*addrp = mfspr(SPRN_SDAR);
 229
 230	if (is_kernel_addr(mfspr(SPRN_SDAR)) && event->attr.exclude_kernel)
 231		*addrp = 0;
 232}
 233
 234static bool regs_sihv(struct pt_regs *regs)
 235{
 236	unsigned long sihv = MMCRA_SIHV;
 237
 238	if (ppmu->flags & PPMU_HAS_SIER)
 239		return !!(regs->dar & SIER_SIHV);
 240
 241	if (ppmu->flags & PPMU_ALT_SIPR)
 242		sihv = POWER6_MMCRA_SIHV;
 243
 244	return !!(regs->dsisr & sihv);
 245}
 246
 247static bool regs_sipr(struct pt_regs *regs)
 248{
 249	unsigned long sipr = MMCRA_SIPR;
 250
 251	if (ppmu->flags & PPMU_HAS_SIER)
 252		return !!(regs->dar & SIER_SIPR);
 253
 254	if (ppmu->flags & PPMU_ALT_SIPR)
 255		sipr = POWER6_MMCRA_SIPR;
 256
 257	return !!(regs->dsisr & sipr);
 258}
 259
 260static inline u32 perf_flags_from_msr(struct pt_regs *regs)
 261{
 262	if (user_mode(regs))
 263		return PERF_RECORD_MISC_USER;
 264	if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
 265		return PERF_RECORD_MISC_HYPERVISOR;
 266	return PERF_RECORD_MISC_KERNEL;
 267}
 268
 269static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 270{
 271	bool use_siar = regs_use_siar(regs);
 272	unsigned long siar;
 273	unsigned long addr;
 274
 275	if (!use_siar)
 276		return perf_flags_from_msr(regs);
 277
 278	/*
 279	 * If we don't have flags in MMCRA, rather than using
 280	 * the MSR, we intuit the flags from the address in
 281	 * SIAR which should give slightly more reliable
 282	 * results
 283	 */
 284	if (ppmu->flags & PPMU_NO_SIPR) {
 285		siar = mfspr(SPRN_SIAR);
 286		if (is_kernel_addr(siar))
 287			return PERF_RECORD_MISC_KERNEL;
 288		return PERF_RECORD_MISC_USER;
 289	}
 290
 291	/* PR has priority over HV, so order below is important */
 292	if (regs_sipr(regs)) {
 293		if (!(ppmu->flags & PPMU_P10))
 294			return PERF_RECORD_MISC_USER;
 295	} else if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
 296		return PERF_RECORD_MISC_HYPERVISOR;
 297
 298	/*
 299	 * Check the address in SIAR to identify the
 300	 * privilege levels since the SIER[MSR_HV, MSR_PR]
 301	 * bits are not set correctly in power10 sometimes
 302	 */
 303	if (ppmu->flags & PPMU_P10) {
 304		siar = mfspr(SPRN_SIAR);
 305		addr = siar ? siar : regs->nip;
 306		if (!is_kernel_addr(addr))
 307			return PERF_RECORD_MISC_USER;
 308	}
 309
 310	return PERF_RECORD_MISC_KERNEL;
 311}
 312
 313/*
 314 * Overload regs->dsisr to store MMCRA so we only need to read it once
 315 * on each interrupt.
 316 * Overload regs->dar to store SIER if we have it.
 317 * Overload regs->result to specify whether we should use the MSR (result
 318 * is zero) or the SIAR (result is non zero).
 319 */
 320static inline void perf_read_regs(struct pt_regs *regs)
 321{
 322	unsigned long mmcra = mfspr(SPRN_MMCRA);
 323	int marked = mmcra & MMCRA_SAMPLE_ENABLE;
 324	int use_siar;
 325
 326	regs->dsisr = mmcra;
 327
 328	if (ppmu->flags & PPMU_HAS_SIER)
 329		regs->dar = mfspr(SPRN_SIER);
 330
 331	/*
 332	 * If this isn't a PMU exception (eg a software event) the SIAR is
 333	 * not valid. Use pt_regs.
 334	 *
 335	 * If it is a marked event use the SIAR.
 336	 *
 337	 * If the PMU doesn't update the SIAR for non marked events use
 338	 * pt_regs.
 339	 *
 340	 * If regs is a kernel interrupt, always use SIAR. Some PMUs have an
 341	 * issue with regs_sipr not being in synch with SIAR in interrupt entry
 342	 * and return sequences, which can result in regs_sipr being true for
 343	 * kernel interrupts and SIAR, which has the effect of causing samples
 344	 * to pile up at mtmsrd MSR[EE] 0->1 or pending irq replay around
 345	 * interrupt entry/exit.
 346	 *
 347	 * If the PMU has HV/PR flags then check to see if they
 348	 * place the exception in userspace. If so, use pt_regs. In
 349	 * continuous sampling mode the SIAR and the PMU exception are
 350	 * not synchronised, so they may be many instructions apart.
 351	 * This can result in confusing backtraces. We still want
 352	 * hypervisor samples as well as samples in the kernel with
 353	 * interrupts off hence the userspace check.
 354	 */
 355	if (TRAP(regs) != INTERRUPT_PERFMON)
 356		use_siar = 0;
 357	else if ((ppmu->flags & PPMU_NO_SIAR))
 358		use_siar = 0;
 359	else if (marked)
 360		use_siar = 1;
 361	else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
 362		use_siar = 0;
 363	else if (!user_mode(regs))
 364		use_siar = 1;
 365	else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
 366		use_siar = 0;
 367	else
 368		use_siar = 1;
 369
 370	regs->result = use_siar;
 371}
 372
 373/*
 374 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
 375 * must be sampled only if the SIAR-valid bit is set.
 376 *
 377 * For unmarked instructions and for processors that don't have the SIAR-Valid
 378 * bit, assume that SIAR is valid.
 379 */
 380static inline int siar_valid(struct pt_regs *regs)
 381{
 382	unsigned long mmcra = regs->dsisr;
 383	int marked = mmcra & MMCRA_SAMPLE_ENABLE;
 384
 385	if (marked) {
 386		/*
 387		 * SIER[SIAR_VALID] is not set for some
 388		 * marked events on power10 DD1, so drop
 389		 * the check for SIER[SIAR_VALID] and return true.
 390		 */
 391		if (ppmu->flags & PPMU_P10_DD1)
 392			return 0x1;
 393		else if (ppmu->flags & PPMU_HAS_SIER)
 394			return regs->dar & SIER_SIAR_VALID;
 395
 396		if (ppmu->flags & PPMU_SIAR_VALID)
 397			return mmcra & POWER7P_MMCRA_SIAR_VALID;
 398	}
 399
 400	return 1;
 401}
 402
 403
 404/* Reset all possible BHRB entries */
 405static void power_pmu_bhrb_reset(void)
 406{
 407	asm volatile(PPC_CLRBHRB);
 408}
 409
 410static void power_pmu_bhrb_enable(struct perf_event *event)
 411{
 412	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
 413
 414	if (!ppmu->bhrb_nr)
 415		return;
 416
 417	/* Clear BHRB if we changed task context to avoid data leaks */
 418	if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
 419		power_pmu_bhrb_reset();
 420		cpuhw->bhrb_context = event->ctx;
 421	}
 422	cpuhw->bhrb_users++;
 423	perf_sched_cb_inc(event->pmu);
 424}
 425
 426static void power_pmu_bhrb_disable(struct perf_event *event)
 427{
 428	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
 429
 430	if (!ppmu->bhrb_nr)
 431		return;
 432
 433	WARN_ON_ONCE(!cpuhw->bhrb_users);
 434	cpuhw->bhrb_users--;
 435	perf_sched_cb_dec(event->pmu);
 436
 437	if (!cpuhw->disabled && !cpuhw->bhrb_users) {
 438		/* BHRB cannot be turned off when other
 439		 * events are active on the PMU.
 440		 */
 441
 442		/* avoid stale pointer */
 443		cpuhw->bhrb_context = NULL;
 444	}
 445}
 446
 447/* Called from ctxsw to prevent one process's branch entries to
 448 * mingle with the other process's entries during context switch.
 449 */
 450static void power_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
 451				 struct task_struct *task, bool sched_in)
 452{
 453	if (!ppmu->bhrb_nr)
 454		return;
 455
 456	if (sched_in)
 457		power_pmu_bhrb_reset();
 458}
 459/* Calculate the to address for a branch */
 460static __u64 power_pmu_bhrb_to(u64 addr)
 461{
 462	unsigned int instr;
 463	__u64 target;
 464
 465	if (is_kernel_addr(addr)) {
 466		if (copy_from_kernel_nofault(&instr, (void *)addr,
 467				sizeof(instr)))
 468			return 0;
 469
 470		return branch_target(&instr);
 471	}
 472
 473	/* Userspace: need copy instruction here then translate it */
 474	if (copy_from_user_nofault(&instr, (unsigned int __user *)addr,
 475			sizeof(instr)))
 476		return 0;
 477
 478	target = branch_target(&instr);
 479	if ((!target) || (instr & BRANCH_ABSOLUTE))
 480		return target;
 481
 482	/* Translate relative branch target from kernel to user address */
 483	return target - (unsigned long)&instr + addr;
 484}
 485
 486/* Processing BHRB entries */
 487static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw)
 488{
 489	u64 val;
 490	u64 addr;
 491	int r_index, u_index, pred;
 492
 493	r_index = 0;
 494	u_index = 0;
 495	while (r_index < ppmu->bhrb_nr) {
 496		/* Assembly read function */
 497		val = read_bhrb(r_index++);
 498		if (!val)
 499			/* Terminal marker: End of valid BHRB entries */
 500			break;
 501		else {
 502			addr = val & BHRB_EA;
 503			pred = val & BHRB_PREDICTION;
 504
 505			if (!addr)
 506				/* invalid entry */
 507				continue;
 508
 509			/*
 510			 * BHRB rolling buffer could very much contain the kernel
 511			 * addresses at this point. Check the privileges before
 512			 * exporting it to userspace (avoid exposure of regions
 513			 * where we could have speculative execution)
 514			 * Incase of ISA v3.1, BHRB will capture only user-space
 515			 * addresses, hence include a check before filtering code
 516			 */
 517			if (!(ppmu->flags & PPMU_ARCH_31) &&
 518			    is_kernel_addr(addr) && event->attr.exclude_kernel)
 519				continue;
 520
 521			/* Branches are read most recent first (ie. mfbhrb 0 is
 522			 * the most recent branch).
 523			 * There are two types of valid entries:
 524			 * 1) a target entry which is the to address of a
 525			 *    computed goto like a blr,bctr,btar.  The next
 526			 *    entry read from the bhrb will be branch
 527			 *    corresponding to this target (ie. the actual
 528			 *    blr/bctr/btar instruction).
 529			 * 2) a from address which is an actual branch.  If a
 530			 *    target entry proceeds this, then this is the
 531			 *    matching branch for that target.  If this is not
 532			 *    following a target entry, then this is a branch
 533			 *    where the target is given as an immediate field
 534			 *    in the instruction (ie. an i or b form branch).
 535			 *    In this case we need to read the instruction from
 536			 *    memory to determine the target/to address.
 537			 */
 538
 539			if (val & BHRB_TARGET) {
 540				/* Target branches use two entries
 541				 * (ie. computed gotos/XL form)
 542				 */
 543				cpuhw->bhrb_entries[u_index].to = addr;
 544				cpuhw->bhrb_entries[u_index].mispred = pred;
 545				cpuhw->bhrb_entries[u_index].predicted = ~pred;
 546
 547				/* Get from address in next entry */
 548				val = read_bhrb(r_index++);
 549				addr = val & BHRB_EA;
 550				if (val & BHRB_TARGET) {
 551					/* Shouldn't have two targets in a
 552					   row.. Reset index and try again */
 553					r_index--;
 554					addr = 0;
 555				}
 556				cpuhw->bhrb_entries[u_index].from = addr;
 557			} else {
 558				/* Branches to immediate field 
 559				   (ie I or B form) */
 560				cpuhw->bhrb_entries[u_index].from = addr;
 561				cpuhw->bhrb_entries[u_index].to =
 562					power_pmu_bhrb_to(addr);
 563				cpuhw->bhrb_entries[u_index].mispred = pred;
 564				cpuhw->bhrb_entries[u_index].predicted = ~pred;
 565			}
 566			u_index++;
 567
 568		}
 569	}
 570	cpuhw->bhrb_stack.nr = u_index;
 571	cpuhw->bhrb_stack.hw_idx = -1ULL;
 572	return;
 573}
 574
 575static bool is_ebb_event(struct perf_event *event)
 576{
 577	/*
 578	 * This could be a per-PMU callback, but we'd rather avoid the cost. We
 579	 * check that the PMU supports EBB, meaning those that don't can still
 580	 * use bit 63 of the event code for something else if they wish.
 581	 */
 582	return (ppmu->flags & PPMU_ARCH_207S) &&
 583	       ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
 584}
 585
 586static int ebb_event_check(struct perf_event *event)
 587{
 588	struct perf_event *leader = event->group_leader;
 589
 590	/* Event and group leader must agree on EBB */
 591	if (is_ebb_event(leader) != is_ebb_event(event))
 592		return -EINVAL;
 593
 594	if (is_ebb_event(event)) {
 595		if (!(event->attach_state & PERF_ATTACH_TASK))
 596			return -EINVAL;
 597
 598		if (!leader->attr.pinned || !leader->attr.exclusive)
 599			return -EINVAL;
 600
 601		if (event->attr.freq ||
 602		    event->attr.inherit ||
 603		    event->attr.sample_type ||
 604		    event->attr.sample_period ||
 605		    event->attr.enable_on_exec)
 606			return -EINVAL;
 607	}
 608
 609	return 0;
 610}
 611
 612static void ebb_event_add(struct perf_event *event)
 613{
 614	if (!is_ebb_event(event) || current->thread.used_ebb)
 615		return;
 616
 617	/*
 618	 * IFF this is the first time we've added an EBB event, set
 619	 * PMXE in the user MMCR0 so we can detect when it's cleared by
 620	 * userspace. We need this so that we can context switch while
 621	 * userspace is in the EBB handler (where PMXE is 0).
 622	 */
 623	current->thread.used_ebb = 1;
 624	current->thread.mmcr0 |= MMCR0_PMXE;
 625}
 626
 627static void ebb_switch_out(unsigned long mmcr0)
 628{
 629	if (!(mmcr0 & MMCR0_EBE))
 630		return;
 631
 632	current->thread.siar  = mfspr(SPRN_SIAR);
 633	current->thread.sier  = mfspr(SPRN_SIER);
 634	current->thread.sdar  = mfspr(SPRN_SDAR);
 635	current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
 636	current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
 637	if (ppmu->flags & PPMU_ARCH_31) {
 638		current->thread.mmcr3 = mfspr(SPRN_MMCR3);
 639		current->thread.sier2 = mfspr(SPRN_SIER2);
 640		current->thread.sier3 = mfspr(SPRN_SIER3);
 641	}
 642}
 643
 644static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
 645{
 646	unsigned long mmcr0 = cpuhw->mmcr.mmcr0;
 647
 648	if (!ebb)
 649		goto out;
 650
 651	/* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
 652	mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
 653
 654	/*
 655	 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
 656	 * with pmao_restore_workaround() because we may add PMAO but we never
 657	 * clear it here.
 658	 */
 659	mmcr0 |= current->thread.mmcr0;
 660
 661	/*
 662	 * Be careful not to set PMXE if userspace had it cleared. This is also
 663	 * compatible with pmao_restore_workaround() because it has already
 664	 * cleared PMXE and we leave PMAO alone.
 665	 */
 666	if (!(current->thread.mmcr0 & MMCR0_PMXE))
 667		mmcr0 &= ~MMCR0_PMXE;
 668
 669	mtspr(SPRN_SIAR, current->thread.siar);
 670	mtspr(SPRN_SIER, current->thread.sier);
 671	mtspr(SPRN_SDAR, current->thread.sdar);
 672
 673	/*
 674	 * Merge the kernel & user values of MMCR2. The semantics we implement
 675	 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
 676	 * but not clear bits. If a task wants to be able to clear bits, ie.
 677	 * unfreeze counters, it should not set exclude_xxx in its events and
 678	 * instead manage the MMCR2 entirely by itself.
 679	 */
 680	mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2);
 681
 682	if (ppmu->flags & PPMU_ARCH_31) {
 683		mtspr(SPRN_MMCR3, current->thread.mmcr3);
 684		mtspr(SPRN_SIER2, current->thread.sier2);
 685		mtspr(SPRN_SIER3, current->thread.sier3);
 686	}
 687out:
 688	return mmcr0;
 689}
 690
 691static void pmao_restore_workaround(bool ebb)
 692{
 693	unsigned pmcs[6];
 694
 695	if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
 696		return;
 697
 698	/*
 699	 * On POWER8E there is a hardware defect which affects the PMU context
 700	 * switch logic, ie. power_pmu_disable/enable().
 701	 *
 702	 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
 703	 * by the hardware. Sometime later the actual PMU exception is
 704	 * delivered.
 705	 *
 706	 * If we context switch, or simply disable/enable, the PMU prior to the
 707	 * exception arriving, the exception will be lost when we clear PMAO.
 708	 *
 709	 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
 710	 * set, and this _should_ generate an exception. However because of the
 711	 * defect no exception is generated when we write PMAO, and we get
 712	 * stuck with no counters counting but no exception delivered.
 713	 *
 714	 * The workaround is to detect this case and tweak the hardware to
 715	 * create another pending PMU exception.
 716	 *
 717	 * We do that by setting up PMC6 (cycles) for an imminent overflow and
 718	 * enabling the PMU. That causes a new exception to be generated in the
 719	 * chip, but we don't take it yet because we have interrupts hard
 720	 * disabled. We then write back the PMU state as we want it to be seen
 721	 * by the exception handler. When we reenable interrupts the exception
 722	 * handler will be called and see the correct state.
 723	 *
 724	 * The logic is the same for EBB, except that the exception is gated by
 725	 * us having interrupts hard disabled as well as the fact that we are
 726	 * not in userspace. The exception is finally delivered when we return
 727	 * to userspace.
 728	 */
 729
 730	/* Only if PMAO is set and PMAO_SYNC is clear */
 731	if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
 732		return;
 733
 734	/* If we're doing EBB, only if BESCR[GE] is set */
 735	if (ebb && !(current->thread.bescr & BESCR_GE))
 736		return;
 737
 738	/*
 739	 * We are already soft-disabled in power_pmu_enable(). We need to hard
 740	 * disable to actually prevent the PMU exception from firing.
 741	 */
 742	hard_irq_disable();
 743
 744	/*
 745	 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
 746	 * Using read/write_pmc() in a for loop adds 12 function calls and
 747	 * almost doubles our code size.
 748	 */
 749	pmcs[0] = mfspr(SPRN_PMC1);
 750	pmcs[1] = mfspr(SPRN_PMC2);
 751	pmcs[2] = mfspr(SPRN_PMC3);
 752	pmcs[3] = mfspr(SPRN_PMC4);
 753	pmcs[4] = mfspr(SPRN_PMC5);
 754	pmcs[5] = mfspr(SPRN_PMC6);
 755
 756	/* Ensure all freeze bits are unset */
 757	mtspr(SPRN_MMCR2, 0);
 758
 759	/* Set up PMC6 to overflow in one cycle */
 760	mtspr(SPRN_PMC6, 0x7FFFFFFE);
 761
 762	/* Enable exceptions and unfreeze PMC6 */
 763	mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
 764
 765	/* Now we need to refreeze and restore the PMCs */
 766	mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
 767
 768	mtspr(SPRN_PMC1, pmcs[0]);
 769	mtspr(SPRN_PMC2, pmcs[1]);
 770	mtspr(SPRN_PMC3, pmcs[2]);
 771	mtspr(SPRN_PMC4, pmcs[3]);
 772	mtspr(SPRN_PMC5, pmcs[4]);
 773	mtspr(SPRN_PMC6, pmcs[5]);
 774}
 775
 776/*
 777 * If the perf subsystem wants performance monitor interrupts as soon as
 778 * possible (e.g., to sample the instruction address and stack chain),
 779 * this should return true. The IRQ masking code can then enable MSR[EE]
 780 * in some places (e.g., interrupt handlers) that allows PMI interrupts
 781 * through to improve accuracy of profiles, at the cost of some performance.
 782 *
 783 * The PMU counters can be enabled by other means (e.g., sysfs raw SPR
 784 * access), but in that case there is no need for prompt PMI handling.
 785 *
 786 * This currently returns true if any perf counter is being used. It
 787 * could possibly return false if only events are being counted rather than
 788 * samples being taken, but for now this is good enough.
 789 */
 790bool power_pmu_wants_prompt_pmi(void)
 791{
 792	struct cpu_hw_events *cpuhw;
 793
 794	/*
 795	 * This could simply test local_paca->pmcregs_in_use if that were not
 796	 * under ifdef KVM.
 797	 */
 798	if (!ppmu)
 799		return false;
 800
 801	cpuhw = this_cpu_ptr(&cpu_hw_events);
 802	return cpuhw->n_events;
 803}
 804#endif /* CONFIG_PPC64 */
 805
 806static void perf_event_interrupt(struct pt_regs *regs);
 807
 808/*
 809 * Read one performance monitor counter (PMC).
 810 */
 811static unsigned long read_pmc(int idx)
 812{
 813	unsigned long val;
 814
 815	switch (idx) {
 816	case 1:
 817		val = mfspr(SPRN_PMC1);
 818		break;
 819	case 2:
 820		val = mfspr(SPRN_PMC2);
 821		break;
 822	case 3:
 823		val = mfspr(SPRN_PMC3);
 824		break;
 825	case 4:
 826		val = mfspr(SPRN_PMC4);
 827		break;
 828	case 5:
 829		val = mfspr(SPRN_PMC5);
 830		break;
 831	case 6:
 832		val = mfspr(SPRN_PMC6);
 833		break;
 834#ifdef CONFIG_PPC64
 835	case 7:
 836		val = mfspr(SPRN_PMC7);
 837		break;
 838	case 8:
 839		val = mfspr(SPRN_PMC8);
 840		break;
 841#endif /* CONFIG_PPC64 */
 842	default:
 843		printk(KERN_ERR "oops trying to read PMC%d\n", idx);
 844		val = 0;
 845	}
 846	return val;
 847}
 848
 849/*
 850 * Write one PMC.
 851 */
 852static void write_pmc(int idx, unsigned long val)
 853{
 854	switch (idx) {
 855	case 1:
 856		mtspr(SPRN_PMC1, val);
 857		break;
 858	case 2:
 859		mtspr(SPRN_PMC2, val);
 860		break;
 861	case 3:
 862		mtspr(SPRN_PMC3, val);
 863		break;
 864	case 4:
 865		mtspr(SPRN_PMC4, val);
 866		break;
 867	case 5:
 868		mtspr(SPRN_PMC5, val);
 869		break;
 870	case 6:
 871		mtspr(SPRN_PMC6, val);
 872		break;
 873#ifdef CONFIG_PPC64
 874	case 7:
 875		mtspr(SPRN_PMC7, val);
 876		break;
 877	case 8:
 878		mtspr(SPRN_PMC8, val);
 879		break;
 880#endif /* CONFIG_PPC64 */
 881	default:
 882		printk(KERN_ERR "oops trying to write PMC%d\n", idx);
 883	}
 884}
 885
 886static int any_pmc_overflown(struct cpu_hw_events *cpuhw)
 887{
 888	int i, idx;
 889
 890	for (i = 0; i < cpuhw->n_events; i++) {
 891		idx = cpuhw->event[i]->hw.idx;
 892		if ((idx) && ((int)read_pmc(idx) < 0))
 893			return idx;
 894	}
 895
 896	return 0;
 897}
 898
 899/* Called from sysrq_handle_showregs() */
 900void perf_event_print_debug(void)
 901{
 902	unsigned long sdar, sier, flags;
 903	u32 pmcs[MAX_HWEVENTS];
 904	int i;
 905
 906	if (!ppmu) {
 907		pr_info("Performance monitor hardware not registered.\n");
 908		return;
 909	}
 910
 911	if (!ppmu->n_counter)
 912		return;
 913
 914	local_irq_save(flags);
 915
 916	pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
 917		 smp_processor_id(), ppmu->name, ppmu->n_counter);
 918
 919	for (i = 0; i < ppmu->n_counter; i++)
 920		pmcs[i] = read_pmc(i + 1);
 921
 922	for (; i < MAX_HWEVENTS; i++)
 923		pmcs[i] = 0xdeadbeef;
 924
 925	pr_info("PMC1:  %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
 926		 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
 927
 928	if (ppmu->n_counter > 4)
 929		pr_info("PMC5:  %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
 930			 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
 931
 932	pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
 933		mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
 934
 935	sdar = sier = 0;
 936#ifdef CONFIG_PPC64
 937	sdar = mfspr(SPRN_SDAR);
 938
 939	if (ppmu->flags & PPMU_HAS_SIER)
 940		sier = mfspr(SPRN_SIER);
 941
 942	if (ppmu->flags & PPMU_ARCH_207S) {
 943		pr_info("MMCR2: %016lx EBBHR: %016lx\n",
 944			mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
 945		pr_info("EBBRR: %016lx BESCR: %016lx\n",
 946			mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
 947	}
 948
 949	if (ppmu->flags & PPMU_ARCH_31) {
 950		pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n",
 951			mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3));
 952	}
 953#endif
 954	pr_info("SIAR:  %016lx SDAR:  %016lx SIER:  %016lx\n",
 955		mfspr(SPRN_SIAR), sdar, sier);
 956
 957	local_irq_restore(flags);
 958}
 959
 960/*
 961 * Check if a set of events can all go on the PMU at once.
 962 * If they can't, this will look at alternative codes for the events
 963 * and see if any combination of alternative codes is feasible.
 964 * The feasible set is returned in event_id[].
 965 */
 966static int power_check_constraints(struct cpu_hw_events *cpuhw,
 967				   u64 event_id[], unsigned int cflags[],
 968				   int n_ev, struct perf_event **event)
 969{
 970	unsigned long mask, value, nv;
 971	unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
 972	int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
 973	int i, j;
 974	unsigned long addf = ppmu->add_fields;
 975	unsigned long tadd = ppmu->test_adder;
 976	unsigned long grp_mask = ppmu->group_constraint_mask;
 977	unsigned long grp_val = ppmu->group_constraint_val;
 978
 979	if (n_ev > ppmu->n_counter)
 980		return -1;
 981
 982	/* First see if the events will go on as-is */
 983	for (i = 0; i < n_ev; ++i) {
 984		if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
 985		    && !ppmu->limited_pmc_event(event_id[i])) {
 986			ppmu->get_alternatives(event_id[i], cflags[i],
 987					       cpuhw->alternatives[i]);
 988			event_id[i] = cpuhw->alternatives[i][0];
 989		}
 990		if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
 991					 &cpuhw->avalues[i][0], event[i]->attr.config1))
 992			return -1;
 993	}
 994	value = mask = 0;
 995	for (i = 0; i < n_ev; ++i) {
 996		nv = (value | cpuhw->avalues[i][0]) +
 997			(value & cpuhw->avalues[i][0] & addf);
 998
 999		if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0)
1000			break;
1001
1002		if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0])
1003			& (~grp_mask)) != 0)
1004			break;
1005
1006		value = nv;
1007		mask |= cpuhw->amasks[i][0];
1008	}
1009	if (i == n_ev) {
1010		if ((value & mask & grp_mask) != (mask & grp_val))
1011			return -1;
1012		else
1013			return 0;	/* all OK */
1014	}
1015
1016	/* doesn't work, gather alternatives... */
1017	if (!ppmu->get_alternatives)
1018		return -1;
1019	for (i = 0; i < n_ev; ++i) {
1020		choice[i] = 0;
1021		n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
1022						  cpuhw->alternatives[i]);
1023		for (j = 1; j < n_alt[i]; ++j)
1024			ppmu->get_constraint(cpuhw->alternatives[i][j],
1025					     &cpuhw->amasks[i][j],
1026					     &cpuhw->avalues[i][j],
1027					     event[i]->attr.config1);
1028	}
1029
1030	/* enumerate all possibilities and see if any will work */
1031	i = 0;
1032	j = -1;
1033	value = mask = nv = 0;
1034	while (i < n_ev) {
1035		if (j >= 0) {
1036			/* we're backtracking, restore context */
1037			value = svalues[i];
1038			mask = smasks[i];
1039			j = choice[i];
1040		}
1041		/*
1042		 * See if any alternative k for event_id i,
1043		 * where k > j, will satisfy the constraints.
1044		 */
1045		while (++j < n_alt[i]) {
1046			nv = (value | cpuhw->avalues[i][j]) +
1047				(value & cpuhw->avalues[i][j] & addf);
1048			if ((((nv + tadd) ^ value) & mask) == 0 &&
1049			    (((nv + tadd) ^ cpuhw->avalues[i][j])
1050			     & cpuhw->amasks[i][j]) == 0)
1051				break;
1052		}
1053		if (j >= n_alt[i]) {
1054			/*
1055			 * No feasible alternative, backtrack
1056			 * to event_id i-1 and continue enumerating its
1057			 * alternatives from where we got up to.
1058			 */
1059			if (--i < 0)
1060				return -1;
1061		} else {
1062			/*
1063			 * Found a feasible alternative for event_id i,
1064			 * remember where we got up to with this event_id,
1065			 * go on to the next event_id, and start with
1066			 * the first alternative for it.
1067			 */
1068			choice[i] = j;
1069			svalues[i] = value;
1070			smasks[i] = mask;
1071			value = nv;
1072			mask |= cpuhw->amasks[i][j];
1073			++i;
1074			j = -1;
1075		}
1076	}
1077
1078	/* OK, we have a feasible combination, tell the caller the solution */
1079	for (i = 0; i < n_ev; ++i)
1080		event_id[i] = cpuhw->alternatives[i][choice[i]];
1081	return 0;
1082}
1083
1084/*
1085 * Check if newly-added events have consistent settings for
1086 * exclude_{user,kernel,hv} with each other and any previously
1087 * added events.
1088 */
1089static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
1090			  int n_prev, int n_new)
1091{
1092	int eu = 0, ek = 0, eh = 0;
1093	int i, n, first;
1094	struct perf_event *event;
1095
1096	/*
1097	 * If the PMU we're on supports per event exclude settings then we
1098	 * don't need to do any of this logic. NB. This assumes no PMU has both
1099	 * per event exclude and limited PMCs.
1100	 */
1101	if (ppmu->flags & PPMU_ARCH_207S)
1102		return 0;
1103
1104	n = n_prev + n_new;
1105	if (n <= 1)
1106		return 0;
1107
1108	first = 1;
1109	for (i = 0; i < n; ++i) {
1110		if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1111			cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1112			continue;
1113		}
1114		event = ctrs[i];
1115		if (first) {
1116			eu = event->attr.exclude_user;
1117			ek = event->attr.exclude_kernel;
1118			eh = event->attr.exclude_hv;
1119			first = 0;
1120		} else if (event->attr.exclude_user != eu ||
1121			   event->attr.exclude_kernel != ek ||
1122			   event->attr.exclude_hv != eh) {
1123			return -EAGAIN;
1124		}
1125	}
1126
1127	if (eu || ek || eh)
1128		for (i = 0; i < n; ++i)
1129			if (cflags[i] & PPMU_LIMITED_PMC_OK)
1130				cflags[i] |= PPMU_LIMITED_PMC_REQD;
1131
1132	return 0;
1133}
1134
1135static u64 check_and_compute_delta(u64 prev, u64 val)
1136{
1137	u64 delta = (val - prev) & 0xfffffffful;
1138
1139	/*
1140	 * POWER7 can roll back counter values, if the new value is smaller
1141	 * than the previous value it will cause the delta and the counter to
1142	 * have bogus values unless we rolled a counter over.  If a counter is
1143	 * rolled back, it will be smaller, but within 256, which is the maximum
1144	 * number of events to rollback at once.  If we detect a rollback
1145	 * return 0.  This can lead to a small lack of precision in the
1146	 * counters.
1147	 */
1148	if (prev > val && (prev - val) < 256)
1149		delta = 0;
1150
1151	return delta;
1152}
1153
1154static void power_pmu_read(struct perf_event *event)
1155{
1156	s64 val, delta, prev;
1157
1158	if (event->hw.state & PERF_HES_STOPPED)
1159		return;
1160
1161	if (!event->hw.idx)
1162		return;
1163
1164	if (is_ebb_event(event)) {
1165		val = read_pmc(event->hw.idx);
1166		local64_set(&event->hw.prev_count, val);
1167		return;
1168	}
1169
1170	/*
1171	 * Performance monitor interrupts come even when interrupts
1172	 * are soft-disabled, as long as interrupts are hard-enabled.
1173	 * Therefore we treat them like NMIs.
1174	 */
1175	do {
1176		prev = local64_read(&event->hw.prev_count);
1177		barrier();
1178		val = read_pmc(event->hw.idx);
1179		delta = check_and_compute_delta(prev, val);
1180		if (!delta)
1181			return;
1182	} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1183
1184	local64_add(delta, &event->count);
1185
1186	/*
1187	 * A number of places program the PMC with (0x80000000 - period_left).
1188	 * We never want period_left to be less than 1 because we will program
1189	 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1190	 * roll around to 0 before taking an exception. We have seen this
1191	 * on POWER8.
1192	 *
1193	 * To fix this, clamp the minimum value of period_left to 1.
1194	 */
1195	do {
1196		prev = local64_read(&event->hw.period_left);
1197		val = prev - delta;
1198		if (val < 1)
1199			val = 1;
1200	} while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1201}
1202
1203/*
1204 * On some machines, PMC5 and PMC6 can't be written, don't respect
1205 * the freeze conditions, and don't generate interrupts.  This tells
1206 * us if `event' is using such a PMC.
1207 */
1208static int is_limited_pmc(int pmcnum)
1209{
1210	return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1211		&& (pmcnum == 5 || pmcnum == 6);
1212}
1213
1214static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1215				    unsigned long pmc5, unsigned long pmc6)
1216{
1217	struct perf_event *event;
1218	u64 val, prev, delta;
1219	int i;
1220
1221	for (i = 0; i < cpuhw->n_limited; ++i) {
1222		event = cpuhw->limited_counter[i];
1223		if (!event->hw.idx)
1224			continue;
1225		val = (event->hw.idx == 5) ? pmc5 : pmc6;
1226		prev = local64_read(&event->hw.prev_count);
1227		event->hw.idx = 0;
1228		delta = check_and_compute_delta(prev, val);
1229		if (delta)
1230			local64_add(delta, &event->count);
1231	}
1232}
1233
1234static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1235				  unsigned long pmc5, unsigned long pmc6)
1236{
1237	struct perf_event *event;
1238	u64 val, prev;
1239	int i;
1240
1241	for (i = 0; i < cpuhw->n_limited; ++i) {
1242		event = cpuhw->limited_counter[i];
1243		event->hw.idx = cpuhw->limited_hwidx[i];
1244		val = (event->hw.idx == 5) ? pmc5 : pmc6;
1245		prev = local64_read(&event->hw.prev_count);
1246		if (check_and_compute_delta(prev, val))
1247			local64_set(&event->hw.prev_count, val);
1248		perf_event_update_userpage(event);
1249	}
1250}
1251
1252/*
1253 * Since limited events don't respect the freeze conditions, we
1254 * have to read them immediately after freezing or unfreezing the
1255 * other events.  We try to keep the values from the limited
1256 * events as consistent as possible by keeping the delay (in
1257 * cycles and instructions) between freezing/unfreezing and reading
1258 * the limited events as small and consistent as possible.
1259 * Therefore, if any limited events are in use, we read them
1260 * both, and always in the same order, to minimize variability,
1261 * and do it inside the same asm that writes MMCR0.
1262 */
1263static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1264{
1265	unsigned long pmc5, pmc6;
1266
1267	if (!cpuhw->n_limited) {
1268		mtspr(SPRN_MMCR0, mmcr0);
1269		return;
1270	}
1271
1272	/*
1273	 * Write MMCR0, then read PMC5 and PMC6 immediately.
1274	 * To ensure we don't get a performance monitor interrupt
1275	 * between writing MMCR0 and freezing/thawing the limited
1276	 * events, we first write MMCR0 with the event overflow
1277	 * interrupt enable bits turned off.
1278	 */
1279	asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1280		     : "=&r" (pmc5), "=&r" (pmc6)
1281		     : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1282		       "i" (SPRN_MMCR0),
1283		       "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1284
1285	if (mmcr0 & MMCR0_FC)
1286		freeze_limited_counters(cpuhw, pmc5, pmc6);
1287	else
1288		thaw_limited_counters(cpuhw, pmc5, pmc6);
1289
1290	/*
1291	 * Write the full MMCR0 including the event overflow interrupt
1292	 * enable bits, if necessary.
1293	 */
1294	if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1295		mtspr(SPRN_MMCR0, mmcr0);
1296}
1297
1298/*
1299 * Disable all events to prevent PMU interrupts and to allow
1300 * events to be added or removed.
1301 */
1302static void power_pmu_disable(struct pmu *pmu)
1303{
1304	struct cpu_hw_events *cpuhw;
1305	unsigned long flags, mmcr0, val, mmcra;
1306
1307	if (!ppmu)
1308		return;
1309	local_irq_save(flags);
1310	cpuhw = this_cpu_ptr(&cpu_hw_events);
1311
1312	if (!cpuhw->disabled) {
1313		/*
1314		 * Check if we ever enabled the PMU on this cpu.
1315		 */
1316		if (!cpuhw->pmcs_enabled) {
1317			ppc_enable_pmcs();
1318			cpuhw->pmcs_enabled = 1;
1319		}
1320
1321		/*
1322		 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1323		 * Also clear PMXE to disable PMI's getting triggered in some
1324		 * corner cases during PMU disable.
1325		 */
1326		val  = mmcr0 = mfspr(SPRN_MMCR0);
1327		val |= MMCR0_FC;
1328		val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1329			 MMCR0_PMXE | MMCR0_FC56);
1330		/* Set mmcr0 PMCCEXT for p10 */
1331		if (ppmu->flags & PPMU_ARCH_31)
1332			val |= MMCR0_PMCCEXT;
1333
1334		/*
1335		 * The barrier is to make sure the mtspr has been
1336		 * executed and the PMU has frozen the events etc.
1337		 * before we return.
1338		 */
1339		write_mmcr0(cpuhw, val);
1340		mb();
1341		isync();
1342
1343		/*
1344		 * Some corner cases could clear the PMU counter overflow
1345		 * while a masked PMI is pending. One such case is when
1346		 * a PMI happens during interrupt replay and perf counter
1347		 * values are cleared by PMU callbacks before replay.
1348		 *
1349		 * Disable the interrupt by clearing the paca bit for PMI
1350		 * since we are disabling the PMU now. Otherwise provide a
1351		 * warning if there is PMI pending, but no counter is found
1352		 * overflown.
1353		 *
1354		 * Since power_pmu_disable runs under local_irq_save, it
1355		 * could happen that code hits a PMC overflow without PMI
1356		 * pending in paca. Hence only clear PMI pending if it was
1357		 * set.
1358		 *
1359		 * If a PMI is pending, then MSR[EE] must be disabled (because
1360		 * the masked PMI handler disabling EE). So it is safe to
1361		 * call clear_pmi_irq_pending().
1362		 */
1363		if (pmi_irq_pending())
1364			clear_pmi_irq_pending();
1365
1366		val = mmcra = cpuhw->mmcr.mmcra;
1367
1368		/*
1369		 * Disable instruction sampling if it was enabled
1370		 */
1371		val &= ~MMCRA_SAMPLE_ENABLE;
1372
1373		/* Disable BHRB via mmcra (BHRBRD) for p10 */
1374		if (ppmu->flags & PPMU_ARCH_31)
1375			val |= MMCRA_BHRB_DISABLE;
1376
1377		/*
1378		 * Write SPRN_MMCRA if mmcra has either disabled
1379		 * instruction sampling or BHRB.
1380		 */
1381		if (val != mmcra) {
1382			mtspr(SPRN_MMCRA, val);
1383			mb();
1384			isync();
1385		}
1386
1387		cpuhw->disabled = 1;
1388		cpuhw->n_added = 0;
1389
1390		ebb_switch_out(mmcr0);
1391
1392#ifdef CONFIG_PPC64
1393		/*
1394		 * These are readable by userspace, may contain kernel
1395		 * addresses and are not switched by context switch, so clear
1396		 * them now to avoid leaking anything to userspace in general
1397		 * including to another process.
1398		 */
1399		if (ppmu->flags & PPMU_ARCH_207S) {
1400			mtspr(SPRN_SDAR, 0);
1401			mtspr(SPRN_SIAR, 0);
1402		}
1403#endif
1404	}
1405
1406	local_irq_restore(flags);
1407}
1408
1409/*
1410 * Re-enable all events if disable == 0.
1411 * If we were previously disabled and events were added, then
1412 * put the new config on the PMU.
1413 */
1414static void power_pmu_enable(struct pmu *pmu)
1415{
1416	struct perf_event *event;
1417	struct cpu_hw_events *cpuhw;
1418	unsigned long flags;
1419	long i;
1420	unsigned long val, mmcr0;
1421	s64 left;
1422	unsigned int hwc_index[MAX_HWEVENTS];
1423	int n_lim;
1424	int idx;
1425	bool ebb;
1426
1427	if (!ppmu)
1428		return;
1429	local_irq_save(flags);
1430
1431	cpuhw = this_cpu_ptr(&cpu_hw_events);
1432	if (!cpuhw->disabled)
1433		goto out;
1434
1435	if (cpuhw->n_events == 0) {
1436		ppc_set_pmu_inuse(0);
1437		goto out;
1438	}
1439
1440	cpuhw->disabled = 0;
1441
1442	/*
1443	 * EBB requires an exclusive group and all events must have the EBB
1444	 * flag set, or not set, so we can just check a single event. Also we
1445	 * know we have at least one event.
1446	 */
1447	ebb = is_ebb_event(cpuhw->event[0]);
1448
1449	/*
1450	 * If we didn't change anything, or only removed events,
1451	 * no need to recalculate MMCR* settings and reset the PMCs.
1452	 * Just reenable the PMU with the current MMCR* settings
1453	 * (possibly updated for removal of events).
1454	 */
1455	if (!cpuhw->n_added) {
1456		/*
1457		 * If there is any active event with an overflown PMC
1458		 * value, set back PACA_IRQ_PMI which would have been
1459		 * cleared in power_pmu_disable().
1460		 */
1461		hard_irq_disable();
1462		if (any_pmc_overflown(cpuhw))
1463			set_pmi_irq_pending();
1464
1465		mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
1466		mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);
1467		if (ppmu->flags & PPMU_ARCH_31)
1468			mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);
1469		goto out_enable;
1470	}
1471
1472	/*
1473	 * Clear all MMCR settings and recompute them for the new set of events.
1474	 */
1475	memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1476
1477	if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1478			       &cpuhw->mmcr, cpuhw->event, ppmu->flags)) {
1479		/* shouldn't ever get here */
1480		printk(KERN_ERR "oops compute_mmcr failed\n");
1481		goto out;
1482	}
1483
1484	if (!(ppmu->flags & PPMU_ARCH_207S)) {
1485		/*
1486		 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1487		 * bits for the first event. We have already checked that all
1488		 * events have the same value for these bits as the first event.
1489		 */
1490		event = cpuhw->event[0];
1491		if (event->attr.exclude_user)
1492			cpuhw->mmcr.mmcr0 |= MMCR0_FCP;
1493		if (event->attr.exclude_kernel)
1494			cpuhw->mmcr.mmcr0 |= freeze_events_kernel;
1495		if (event->attr.exclude_hv)
1496			cpuhw->mmcr.mmcr0 |= MMCR0_FCHV;
1497	}
1498
1499	/*
1500	 * Write the new configuration to MMCR* with the freeze
1501	 * bit set and set the hardware events to their initial values.
1502	 * Then unfreeze the events.
1503	 */
1504	ppc_set_pmu_inuse(1);
1505	mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
1506	mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);
1507	mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1508				| MMCR0_FC);
1509	if (ppmu->flags & PPMU_ARCH_207S)
1510		mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2);
1511
1512	if (ppmu->flags & PPMU_ARCH_31)
1513		mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);
1514
1515	/*
1516	 * Read off any pre-existing events that need to move
1517	 * to another PMC.
1518	 */
1519	for (i = 0; i < cpuhw->n_events; ++i) {
1520		event = cpuhw->event[i];
1521		if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1522			power_pmu_read(event);
1523			write_pmc(event->hw.idx, 0);
1524			event->hw.idx = 0;
1525		}
1526	}
1527
1528	/*
1529	 * Initialize the PMCs for all the new and moved events.
1530	 */
1531	cpuhw->n_limited = n_lim = 0;
1532	for (i = 0; i < cpuhw->n_events; ++i) {
1533		event = cpuhw->event[i];
1534		if (event->hw.idx)
1535			continue;
1536		idx = hwc_index[i] + 1;
1537		if (is_limited_pmc(idx)) {
1538			cpuhw->limited_counter[n_lim] = event;
1539			cpuhw->limited_hwidx[n_lim] = idx;
1540			++n_lim;
1541			continue;
1542		}
1543
1544		if (ebb)
1545			val = local64_read(&event->hw.prev_count);
1546		else {
1547			val = 0;
1548			if (event->hw.sample_period) {
1549				left = local64_read(&event->hw.period_left);
1550				if (left < 0x80000000L)
1551					val = 0x80000000L - left;
1552			}
1553			local64_set(&event->hw.prev_count, val);
1554		}
1555
1556		event->hw.idx = idx;
1557		if (event->hw.state & PERF_HES_STOPPED)
1558			val = 0;
1559		write_pmc(idx, val);
1560
1561		perf_event_update_userpage(event);
1562	}
1563	cpuhw->n_limited = n_lim;
1564	cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE;
1565
1566 out_enable:
1567	pmao_restore_workaround(ebb);
1568
1569	mmcr0 = ebb_switch_in(ebb, cpuhw);
1570
1571	mb();
1572	if (cpuhw->bhrb_users)
1573		ppmu->config_bhrb(cpuhw->bhrb_filter);
1574
1575	write_mmcr0(cpuhw, mmcr0);
1576
1577	/*
1578	 * Enable instruction sampling if necessary
1579	 */
1580	if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) {
1581		mb();
1582		mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra);
1583	}
1584
1585 out:
1586
1587	local_irq_restore(flags);
1588}
1589
1590static int collect_events(struct perf_event *group, int max_count,
1591			  struct perf_event *ctrs[], u64 *events,
1592			  unsigned int *flags)
1593{
1594	int n = 0;
1595	struct perf_event *event;
1596
1597	if (group->pmu->task_ctx_nr == perf_hw_context) {
1598		if (n >= max_count)
1599			return -1;
1600		ctrs[n] = group;
1601		flags[n] = group->hw.event_base;
1602		events[n++] = group->hw.config;
1603	}
1604	for_each_sibling_event(event, group) {
1605		if (event->pmu->task_ctx_nr == perf_hw_context &&
1606		    event->state != PERF_EVENT_STATE_OFF) {
1607			if (n >= max_count)
1608				return -1;
1609			ctrs[n] = event;
1610			flags[n] = event->hw.event_base;
1611			events[n++] = event->hw.config;
1612		}
1613	}
1614	return n;
1615}
1616
1617/*
1618 * Add an event to the PMU.
1619 * If all events are not already frozen, then we disable and
1620 * re-enable the PMU in order to get hw_perf_enable to do the
1621 * actual work of reconfiguring the PMU.
1622 */
1623static int power_pmu_add(struct perf_event *event, int ef_flags)
1624{
1625	struct cpu_hw_events *cpuhw;
1626	unsigned long flags;
1627	int n0;
1628	int ret = -EAGAIN;
1629
1630	local_irq_save(flags);
1631	perf_pmu_disable(event->pmu);
1632
1633	/*
1634	 * Add the event to the list (if there is room)
1635	 * and check whether the total set is still feasible.
1636	 */
1637	cpuhw = this_cpu_ptr(&cpu_hw_events);
1638	n0 = cpuhw->n_events;
1639	if (n0 >= ppmu->n_counter)
1640		goto out;
1641	cpuhw->event[n0] = event;
1642	cpuhw->events[n0] = event->hw.config;
1643	cpuhw->flags[n0] = event->hw.event_base;
1644
1645	/*
1646	 * This event may have been disabled/stopped in record_and_restart()
1647	 * because we exceeded the ->event_limit. If re-starting the event,
1648	 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1649	 * notification is re-enabled.
1650	 */
1651	if (!(ef_flags & PERF_EF_START))
1652		event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1653	else
1654		event->hw.state = 0;
1655
1656	/*
1657	 * If group events scheduling transaction was started,
1658	 * skip the schedulability test here, it will be performed
1659	 * at commit time(->commit_txn) as a whole
1660	 */
1661	if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1662		goto nocheck;
1663
1664	if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1665		goto out;
1666	if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1, cpuhw->event))
1667		goto out;
1668	event->hw.config = cpuhw->events[n0];
1669
1670nocheck:
1671	ebb_event_add(event);
1672
1673	++cpuhw->n_events;
1674	++cpuhw->n_added;
1675
1676	ret = 0;
1677 out:
1678	if (has_branch_stack(event)) {
1679		u64 bhrb_filter = -1;
1680
1681		if (ppmu->bhrb_filter_map)
1682			bhrb_filter = ppmu->bhrb_filter_map(
1683				event->attr.branch_sample_type);
1684
1685		if (bhrb_filter != -1) {
1686			cpuhw->bhrb_filter = bhrb_filter;
1687			power_pmu_bhrb_enable(event);
1688		}
1689	}
1690
1691	perf_pmu_enable(event->pmu);
1692	local_irq_restore(flags);
1693	return ret;
1694}
1695
1696/*
1697 * Remove an event from the PMU.
1698 */
1699static void power_pmu_del(struct perf_event *event, int ef_flags)
1700{
1701	struct cpu_hw_events *cpuhw;
1702	long i;
1703	unsigned long flags;
1704
1705	local_irq_save(flags);
1706	perf_pmu_disable(event->pmu);
1707
1708	power_pmu_read(event);
1709
1710	cpuhw = this_cpu_ptr(&cpu_hw_events);
1711	for (i = 0; i < cpuhw->n_events; ++i) {
1712		if (event == cpuhw->event[i]) {
1713			while (++i < cpuhw->n_events) {
1714				cpuhw->event[i-1] = cpuhw->event[i];
1715				cpuhw->events[i-1] = cpuhw->events[i];
1716				cpuhw->flags[i-1] = cpuhw->flags[i];
1717			}
1718			--cpuhw->n_events;
1719			ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr);
1720			if (event->hw.idx) {
1721				write_pmc(event->hw.idx, 0);
1722				event->hw.idx = 0;
1723			}
1724			perf_event_update_userpage(event);
1725			break;
1726		}
1727	}
1728	for (i = 0; i < cpuhw->n_limited; ++i)
1729		if (event == cpuhw->limited_counter[i])
1730			break;
1731	if (i < cpuhw->n_limited) {
1732		while (++i < cpuhw->n_limited) {
1733			cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1734			cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1735		}
1736		--cpuhw->n_limited;
1737	}
1738	if (cpuhw->n_events == 0) {
1739		/* disable exceptions if no events are running */
1740		cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE);
1741	}
1742
1743	if (has_branch_stack(event))
1744		power_pmu_bhrb_disable(event);
1745
1746	perf_pmu_enable(event->pmu);
1747	local_irq_restore(flags);
1748}
1749
1750/*
1751 * POWER-PMU does not support disabling individual counters, hence
1752 * program their cycle counter to their max value and ignore the interrupts.
1753 */
1754
1755static void power_pmu_start(struct perf_event *event, int ef_flags)
1756{
1757	unsigned long flags;
1758	s64 left;
1759	unsigned long val;
1760
1761	if (!event->hw.idx || !event->hw.sample_period)
1762		return;
1763
1764	if (!(event->hw.state & PERF_HES_STOPPED))
1765		return;
1766
1767	if (ef_flags & PERF_EF_RELOAD)
1768		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1769
1770	local_irq_save(flags);
1771	perf_pmu_disable(event->pmu);
1772
1773	event->hw.state = 0;
1774	left = local64_read(&event->hw.period_left);
1775
1776	val = 0;
1777	if (left < 0x80000000L)
1778		val = 0x80000000L - left;
1779
1780	write_pmc(event->hw.idx, val);
1781
1782	perf_event_update_userpage(event);
1783	perf_pmu_enable(event->pmu);
1784	local_irq_restore(flags);
1785}
1786
1787static void power_pmu_stop(struct perf_event *event, int ef_flags)
1788{
1789	unsigned long flags;
1790
1791	if (!event->hw.idx || !event->hw.sample_period)
1792		return;
1793
1794	if (event->hw.state & PERF_HES_STOPPED)
1795		return;
1796
1797	local_irq_save(flags);
1798	perf_pmu_disable(event->pmu);
1799
1800	power_pmu_read(event);
1801	event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1802	write_pmc(event->hw.idx, 0);
1803
1804	perf_event_update_userpage(event);
1805	perf_pmu_enable(event->pmu);
1806	local_irq_restore(flags);
1807}
1808
1809/*
1810 * Start group events scheduling transaction
1811 * Set the flag to make pmu::enable() not perform the
1812 * schedulability test, it will be performed at commit time
1813 *
1814 * We only support PERF_PMU_TXN_ADD transactions. Save the
1815 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1816 * transactions.
1817 */
1818static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1819{
1820	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1821
1822	WARN_ON_ONCE(cpuhw->txn_flags);		/* txn already in flight */
1823
1824	cpuhw->txn_flags = txn_flags;
1825	if (txn_flags & ~PERF_PMU_TXN_ADD)
1826		return;
1827
1828	perf_pmu_disable(pmu);
1829	cpuhw->n_txn_start = cpuhw->n_events;
1830}
1831
1832/*
1833 * Stop group events scheduling transaction
1834 * Clear the flag and pmu::enable() will perform the
1835 * schedulability test.
1836 */
1837static void power_pmu_cancel_txn(struct pmu *pmu)
1838{
1839	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1840	unsigned int txn_flags;
1841
1842	WARN_ON_ONCE(!cpuhw->txn_flags);	/* no txn in flight */
1843
1844	txn_flags = cpuhw->txn_flags;
1845	cpuhw->txn_flags = 0;
1846	if (txn_flags & ~PERF_PMU_TXN_ADD)
1847		return;
1848
1849	perf_pmu_enable(pmu);
1850}
1851
1852/*
1853 * Commit group events scheduling transaction
1854 * Perform the group schedulability test as a whole
1855 * Return 0 if success
1856 */
1857static int power_pmu_commit_txn(struct pmu *pmu)
1858{
1859	struct cpu_hw_events *cpuhw;
1860	long i, n;
1861
1862	if (!ppmu)
1863		return -EAGAIN;
1864
1865	cpuhw = this_cpu_ptr(&cpu_hw_events);
1866	WARN_ON_ONCE(!cpuhw->txn_flags);	/* no txn in flight */
1867
1868	if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1869		cpuhw->txn_flags = 0;
1870		return 0;
1871	}
1872
1873	n = cpuhw->n_events;
1874	if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1875		return -EAGAIN;
1876	i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n, cpuhw->event);
1877	if (i < 0)
1878		return -EAGAIN;
1879
1880	for (i = cpuhw->n_txn_start; i < n; ++i)
1881		cpuhw->event[i]->hw.config = cpuhw->events[i];
1882
1883	cpuhw->txn_flags = 0;
1884	perf_pmu_enable(pmu);
1885	return 0;
1886}
1887
1888/*
1889 * Return 1 if we might be able to put event on a limited PMC,
1890 * or 0 if not.
1891 * An event can only go on a limited PMC if it counts something
1892 * that a limited PMC can count, doesn't require interrupts, and
1893 * doesn't exclude any processor mode.
1894 */
1895static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1896				 unsigned int flags)
1897{
1898	int n;
1899	u64 alt[MAX_EVENT_ALTERNATIVES];
1900
1901	if (event->attr.exclude_user
1902	    || event->attr.exclude_kernel
1903	    || event->attr.exclude_hv
1904	    || event->attr.sample_period)
1905		return 0;
1906
1907	if (ppmu->limited_pmc_event(ev))
1908		return 1;
1909
1910	/*
1911	 * The requested event_id isn't on a limited PMC already;
1912	 * see if any alternative code goes on a limited PMC.
1913	 */
1914	if (!ppmu->get_alternatives)
1915		return 0;
1916
1917	flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1918	n = ppmu->get_alternatives(ev, flags, alt);
1919
1920	return n > 0;
1921}
1922
1923/*
1924 * Find an alternative event_id that goes on a normal PMC, if possible,
1925 * and return the event_id code, or 0 if there is no such alternative.
1926 * (Note: event_id code 0 is "don't count" on all machines.)
1927 */
1928static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1929{
1930	u64 alt[MAX_EVENT_ALTERNATIVES];
1931	int n;
1932
1933	flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1934	n = ppmu->get_alternatives(ev, flags, alt);
1935	if (!n)
1936		return 0;
1937	return alt[0];
1938}
1939
1940/* Number of perf_events counting hardware events */
1941static atomic_t num_events;
1942/* Used to avoid races in calling reserve/release_pmc_hardware */
1943static DEFINE_MUTEX(pmc_reserve_mutex);
1944
1945/*
1946 * Release the PMU if this is the last perf_event.
1947 */
1948static void hw_perf_event_destroy(struct perf_event *event)
1949{
1950	if (!atomic_add_unless(&num_events, -1, 1)) {
1951		mutex_lock(&pmc_reserve_mutex);
1952		if (atomic_dec_return(&num_events) == 0)
1953			release_pmc_hardware();
1954		mutex_unlock(&pmc_reserve_mutex);
1955	}
1956}
1957
1958/*
1959 * Translate a generic cache event_id config to a raw event_id code.
1960 */
1961static int hw_perf_cache_event(u64 config, u64 *eventp)
1962{
1963	unsigned long type, op, result;
1964	u64 ev;
1965
1966	if (!ppmu->cache_events)
1967		return -EINVAL;
1968
1969	/* unpack config */
1970	type = config & 0xff;
1971	op = (config >> 8) & 0xff;
1972	result = (config >> 16) & 0xff;
1973
1974	if (type >= PERF_COUNT_HW_CACHE_MAX ||
1975	    op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1976	    result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1977		return -EINVAL;
1978
1979	ev = (*ppmu->cache_events)[type][op][result];
1980	if (ev == 0)
1981		return -EOPNOTSUPP;
1982	if (ev == -1)
1983		return -EINVAL;
1984	*eventp = ev;
1985	return 0;
1986}
1987
1988static bool is_event_blacklisted(u64 ev)
1989{
1990	int i;
1991
1992	for (i=0; i < ppmu->n_blacklist_ev; i++) {
1993		if (ppmu->blacklist_ev[i] == ev)
1994			return true;
1995	}
1996
1997	return false;
1998}
1999
2000static int power_pmu_event_init(struct perf_event *event)
2001{
2002	u64 ev;
2003	unsigned long flags, irq_flags;
2004	struct perf_event *ctrs[MAX_HWEVENTS];
2005	u64 events[MAX_HWEVENTS];
2006	unsigned int cflags[MAX_HWEVENTS];
2007	int n;
2008	int err;
2009	struct cpu_hw_events *cpuhw;
2010
2011	if (!ppmu)
2012		return -ENOENT;
2013
2014	if (has_branch_stack(event)) {
2015	        /* PMU has BHRB enabled */
2016		if (!(ppmu->flags & PPMU_ARCH_207S))
2017			return -EOPNOTSUPP;
2018	}
2019
2020	switch (event->attr.type) {
2021	case PERF_TYPE_HARDWARE:
2022		ev = event->attr.config;
2023		if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
2024			return -EOPNOTSUPP;
2025
2026		if (ppmu->blacklist_ev && is_event_blacklisted(ev))
2027			return -EINVAL;
2028		ev = ppmu->generic_events[ev];
2029		break;
2030	case PERF_TYPE_HW_CACHE:
2031		err = hw_perf_cache_event(event->attr.config, &ev);
2032		if (err)
2033			return err;
2034
2035		if (ppmu->blacklist_ev && is_event_blacklisted(ev))
2036			return -EINVAL;
2037		break;
2038	case PERF_TYPE_RAW:
2039		ev = event->attr.config;
2040
2041		if (ppmu->blacklist_ev && is_event_blacklisted(ev))
2042			return -EINVAL;
2043		break;
2044	default:
2045		return -ENOENT;
2046	}
2047
2048	/*
2049	 * PMU config registers have fields that are
2050	 * reserved and some specific values for bit fields are reserved.
2051	 * For ex., MMCRA[61:62] is Random Sampling Mode (SM)
2052	 * and value of 0b11 to this field is reserved.
2053	 * Check for invalid values in attr.config.
2054	 */
2055	if (ppmu->check_attr_config &&
2056	    ppmu->check_attr_config(event))
2057		return -EINVAL;
2058
2059	event->hw.config_base = ev;
2060	event->hw.idx = 0;
2061
2062	/*
2063	 * If we are not running on a hypervisor, force the
2064	 * exclude_hv bit to 0 so that we don't care what
2065	 * the user set it to.
2066	 */
2067	if (!firmware_has_feature(FW_FEATURE_LPAR))
2068		event->attr.exclude_hv = 0;
2069
2070	/*
2071	 * If this is a per-task event, then we can use
2072	 * PM_RUN_* events interchangeably with their non RUN_*
2073	 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
2074	 * XXX we should check if the task is an idle task.
2075	 */
2076	flags = 0;
2077	if (event->attach_state & PERF_ATTACH_TASK)
2078		flags |= PPMU_ONLY_COUNT_RUN;
2079
2080	/*
2081	 * If this machine has limited events, check whether this
2082	 * event_id could go on a limited event.
2083	 */
2084	if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
2085		if (can_go_on_limited_pmc(event, ev, flags)) {
2086			flags |= PPMU_LIMITED_PMC_OK;
2087		} else if (ppmu->limited_pmc_event(ev)) {
2088			/*
2089			 * The requested event_id is on a limited PMC,
2090			 * but we can't use a limited PMC; see if any
2091			 * alternative goes on a normal PMC.
2092			 */
2093			ev = normal_pmc_alternative(ev, flags);
2094			if (!ev)
2095				return -EINVAL;
2096		}
2097	}
2098
2099	/* Extra checks for EBB */
2100	err = ebb_event_check(event);
2101	if (err)
2102		return err;
2103
2104	/*
2105	 * If this is in a group, check if it can go on with all the
2106	 * other hardware events in the group.  We assume the event
2107	 * hasn't been linked into its leader's sibling list at this point.
2108	 */
2109	n = 0;
2110	if (event->group_leader != event) {
2111		n = collect_events(event->group_leader, ppmu->n_counter - 1,
2112				   ctrs, events, cflags);
2113		if (n < 0)
2114			return -EINVAL;
2115	}
2116	events[n] = ev;
2117	ctrs[n] = event;
2118	cflags[n] = flags;
2119	if (check_excludes(ctrs, cflags, n, 1))
2120		return -EINVAL;
2121
2122	local_irq_save(irq_flags);
2123	cpuhw = this_cpu_ptr(&cpu_hw_events);
2124
2125	err = power_check_constraints(cpuhw, events, cflags, n + 1, ctrs);
2126
2127	if (has_branch_stack(event)) {
2128		u64 bhrb_filter = -1;
2129
2130		/*
2131		 * Currently no PMU supports having multiple branch filters
2132		 * at the same time. Branch filters are set via MMCRA IFM[32:33]
2133		 * bits for Power8 and above. Return EOPNOTSUPP when multiple
2134		 * branch filters are requested in the event attr.
2135		 *
2136		 * When opening event via perf_event_open(), branch_sample_type
2137		 * gets adjusted in perf_copy_attr(). Kernel will automatically
2138		 * adjust the branch_sample_type based on the event modifier
2139		 * settings to include PERF_SAMPLE_BRANCH_PLM_ALL. Hence drop
2140		 * the check for PERF_SAMPLE_BRANCH_PLM_ALL.
2141		 */
2142		if (hweight64(event->attr.branch_sample_type & ~PERF_SAMPLE_BRANCH_PLM_ALL) > 1) {
2143			local_irq_restore(irq_flags);
2144			return -EOPNOTSUPP;
2145		}
2146
2147		if (ppmu->bhrb_filter_map)
2148			bhrb_filter = ppmu->bhrb_filter_map(
2149					event->attr.branch_sample_type);
2150
2151		if (bhrb_filter == -1) {
2152			local_irq_restore(irq_flags);
2153			return -EOPNOTSUPP;
2154		}
2155		cpuhw->bhrb_filter = bhrb_filter;
2156	}
2157
2158	local_irq_restore(irq_flags);
2159	if (err)
2160		return -EINVAL;
2161
2162	event->hw.config = events[n];
2163	event->hw.event_base = cflags[n];
2164	event->hw.last_period = event->hw.sample_period;
2165	local64_set(&event->hw.period_left, event->hw.last_period);
2166
2167	/*
2168	 * For EBB events we just context switch the PMC value, we don't do any
2169	 * of the sample_period logic. We use hw.prev_count for this.
2170	 */
2171	if (is_ebb_event(event))
2172		local64_set(&event->hw.prev_count, 0);
2173
2174	/*
2175	 * See if we need to reserve the PMU.
2176	 * If no events are currently in use, then we have to take a
2177	 * mutex to ensure that we don't race with another task doing
2178	 * reserve_pmc_hardware or release_pmc_hardware.
2179	 */
2180	err = 0;
2181	if (!atomic_inc_not_zero(&num_events)) {
2182		mutex_lock(&pmc_reserve_mutex);
2183		if (atomic_read(&num_events) == 0 &&
2184		    reserve_pmc_hardware(perf_event_interrupt))
2185			err = -EBUSY;
2186		else
2187			atomic_inc(&num_events);
2188		mutex_unlock(&pmc_reserve_mutex);
2189	}
2190	event->destroy = hw_perf_event_destroy;
2191
2192	return err;
2193}
2194
2195static int power_pmu_event_idx(struct perf_event *event)
2196{
2197	return event->hw.idx;
2198}
2199
2200ssize_t power_events_sysfs_show(struct device *dev,
2201				struct device_attribute *attr, char *page)
2202{
2203	struct perf_pmu_events_attr *pmu_attr;
2204
2205	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2206
2207	return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2208}
2209
2210static struct pmu power_pmu = {
2211	.pmu_enable	= power_pmu_enable,
2212	.pmu_disable	= power_pmu_disable,
2213	.event_init	= power_pmu_event_init,
2214	.add		= power_pmu_add,
2215	.del		= power_pmu_del,
2216	.start		= power_pmu_start,
2217	.stop		= power_pmu_stop,
2218	.read		= power_pmu_read,
2219	.start_txn	= power_pmu_start_txn,
2220	.cancel_txn	= power_pmu_cancel_txn,
2221	.commit_txn	= power_pmu_commit_txn,
2222	.event_idx	= power_pmu_event_idx,
2223	.sched_task	= power_pmu_sched_task,
2224};
2225
2226#define PERF_SAMPLE_ADDR_TYPE  (PERF_SAMPLE_ADDR |		\
2227				PERF_SAMPLE_PHYS_ADDR |		\
2228				PERF_SAMPLE_DATA_PAGE_SIZE)
2229
2230#define SIER_TYPE_SHIFT	15
2231#define SIER_TYPE_MASK	(0x7ull << SIER_TYPE_SHIFT)
2232
2233/*
2234 * A counter has overflowed; update its count and record
2235 * things if requested.  Note that interrupts are hard-disabled
2236 * here so there is no possibility of being interrupted.
2237 */
2238static void record_and_restart(struct perf_event *event, unsigned long val,
2239			       struct pt_regs *regs)
2240{
2241	u64 period = event->hw.sample_period;
2242	const u64 last_period = event->hw.last_period;
2243	s64 prev, delta, left;
2244	int record = 0;
2245
2246	if (event->hw.state & PERF_HES_STOPPED) {
2247		write_pmc(event->hw.idx, 0);
2248		return;
2249	}
2250
2251	/* we don't have to worry about interrupts here */
2252	prev = local64_read(&event->hw.prev_count);
2253	delta = check_and_compute_delta(prev, val);
2254	local64_add(delta, &event->count);
2255
2256	/*
2257	 * See if the total period for this event has expired,
2258	 * and update for the next period.
2259	 */
2260	val = 0;
2261	left = local64_read(&event->hw.period_left) - delta;
2262	if (delta == 0)
2263		left++;
2264	if (period) {
2265		if (left <= 0) {
2266			left += period;
2267			if (left <= 0)
2268				left = period;
2269
2270			/*
2271			 * If address is not requested in the sample via
2272			 * PERF_SAMPLE_IP, just record that sample irrespective
2273			 * of SIAR valid check.
2274			 */
2275			if (event->attr.sample_type & PERF_SAMPLE_IP)
2276				record = siar_valid(regs);
2277			else
2278				record = 1;
2279
2280			event->hw.last_period = event->hw.sample_period;
2281		}
2282		if (left < 0x80000000LL)
2283			val = 0x80000000LL - left;
2284	}
2285
2286	write_pmc(event->hw.idx, val);
2287	local64_set(&event->hw.prev_count, val);
2288	local64_set(&event->hw.period_left, left);
2289	perf_event_update_userpage(event);
2290
2291	/*
2292	 * Due to hardware limitation, sometimes SIAR could sample a kernel
2293	 * address even when freeze on supervisor state (kernel) is set in
2294	 * MMCR2. Check attr.exclude_kernel and address to drop the sample in
2295	 * these cases.
2296	 */
2297	if (event->attr.exclude_kernel &&
2298	    (event->attr.sample_type & PERF_SAMPLE_IP) &&
2299	    is_kernel_addr(mfspr(SPRN_SIAR)))
2300		record = 0;
2301
2302	/*
2303	 * SIER[46-48] presents instruction type of the sampled instruction.
2304	 * In ISA v3.0 and before values "0" and "7" are considered reserved.
2305	 * In ISA v3.1, value "7" has been used to indicate "larx/stcx".
2306	 * Drop the sample if "type" has reserved values for this field with a
2307	 * ISA version check.
2308	 */
2309	if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2310			ppmu->get_mem_data_src) {
2311		val = (regs->dar & SIER_TYPE_MASK) >> SIER_TYPE_SHIFT;
2312		if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) {
2313			record = 0;
2314			atomic64_inc(&event->lost_samples);
2315		}
2316	}
2317
2318	/*
2319	 * Finally record data if requested.
2320	 */
2321	if (record) {
2322		struct perf_sample_data data;
2323
2324		perf_sample_data_init(&data, ~0ULL, last_period);
2325
2326		if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE)
2327			perf_get_data_addr(event, regs, &data.addr);
2328
2329		if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2330			struct cpu_hw_events *cpuhw;
2331			cpuhw = this_cpu_ptr(&cpu_hw_events);
2332			power_pmu_bhrb_read(event, cpuhw);
2333			perf_sample_save_brstack(&data, event, &cpuhw->bhrb_stack, NULL);
2334		}
2335
2336		if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2337						ppmu->get_mem_data_src) {
2338			ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2339			data.sample_flags |= PERF_SAMPLE_DATA_SRC;
2340		}
2341
2342		if (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE &&
2343						ppmu->get_mem_weight) {
2344			ppmu->get_mem_weight(&data.weight.full, event->attr.sample_type);
2345			data.sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
2346		}
2347		perf_event_overflow(event, &data, regs);
2348	} else if (period) {
2349		/* Account for interrupt in case of invalid SIAR */
2350		perf_event_account_interrupt(event);
2351	}
2352}
2353
2354/*
2355 * Called from generic code to get the misc flags (i.e. processor mode)
2356 * for an event_id.
2357 */
2358unsigned long perf_arch_misc_flags(struct pt_regs *regs)
2359{
2360	u32 flags = perf_get_misc_flags(regs);
2361
2362	if (flags)
2363		return flags;
2364	return user_mode(regs) ? PERF_RECORD_MISC_USER :
2365		PERF_RECORD_MISC_KERNEL;
2366}
2367
2368/*
2369 * Called from generic code to get the instruction pointer
2370 * for an event_id.
2371 */
2372unsigned long perf_arch_instruction_pointer(struct pt_regs *regs)
2373{
2374	unsigned long siar = mfspr(SPRN_SIAR);
2375
2376	if (regs_use_siar(regs) && siar_valid(regs) && siar)
2377		return siar + perf_ip_adjust(regs);
2378	else
2379		return regs->nip;
2380}
2381
2382static bool pmc_overflow_power7(unsigned long val)
2383{
2384	/*
2385	 * Events on POWER7 can roll back if a speculative event doesn't
2386	 * eventually complete. Unfortunately in some rare cases they will
2387	 * raise a performance monitor exception. We need to catch this to
2388	 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2389	 * cycles from overflow.
2390	 *
2391	 * We only do this if the first pass fails to find any overflowing
2392	 * PMCs because a user might set a period of less than 256 and we
2393	 * don't want to mistakenly reset them.
2394	 */
2395	if ((0x80000000 - val) <= 256)
2396		return true;
2397
2398	return false;
2399}
2400
2401static bool pmc_overflow(unsigned long val)
2402{
2403	if ((int)val < 0)
2404		return true;
2405
2406	return false;
2407}
2408
2409/*
2410 * Performance monitor interrupt stuff
2411 */
2412static void __perf_event_interrupt(struct pt_regs *regs)
2413{
2414	int i, j;
2415	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2416	struct perf_event *event;
2417	int found, active;
2418
2419	if (cpuhw->n_limited)
2420		freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2421					mfspr(SPRN_PMC6));
2422
2423	perf_read_regs(regs);
2424
2425	/* Read all the PMCs since we'll need them a bunch of times */
2426	for (i = 0; i < ppmu->n_counter; ++i)
2427		cpuhw->pmcs[i] = read_pmc(i + 1);
2428
2429	/* Try to find what caused the IRQ */
2430	found = 0;
2431	for (i = 0; i < ppmu->n_counter; ++i) {
2432		if (!pmc_overflow(cpuhw->pmcs[i]))
2433			continue;
2434		if (is_limited_pmc(i + 1))
2435			continue; /* these won't generate IRQs */
2436		/*
2437		 * We've found one that's overflowed.  For active
2438		 * counters we need to log this.  For inactive
2439		 * counters, we need to reset it anyway
2440		 */
2441		found = 1;
2442		active = 0;
2443		for (j = 0; j < cpuhw->n_events; ++j) {
2444			event = cpuhw->event[j];
2445			if (event->hw.idx == (i + 1)) {
2446				active = 1;
2447				record_and_restart(event, cpuhw->pmcs[i], regs);
2448				break;
2449			}
2450		}
2451
2452		/*
2453		 * Clear PACA_IRQ_PMI in case it was set by
2454		 * set_pmi_irq_pending() when PMU was enabled
2455		 * after accounting for interrupts.
2456		 */
2457		clear_pmi_irq_pending();
2458
2459		if (!active)
2460			/* reset non active counters that have overflowed */
2461			write_pmc(i + 1, 0);
2462	}
2463	if (!found && pvr_version_is(PVR_POWER7)) {
2464		/* check active counters for special buggy p7 overflow */
2465		for (i = 0; i < cpuhw->n_events; ++i) {
2466			event = cpuhw->event[i];
2467			if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2468				continue;
2469			if (pmc_overflow_power7(cpuhw->pmcs[event->hw.idx - 1])) {
2470				/* event has overflowed in a buggy way*/
2471				found = 1;
2472				record_and_restart(event,
2473						   cpuhw->pmcs[event->hw.idx - 1],
2474						   regs);
2475			}
2476		}
2477	}
2478
2479	/*
2480	 * During system wide profiling or while specific CPU is monitored for an
2481	 * event, some corner cases could cause PMC to overflow in idle path. This
2482	 * will trigger a PMI after waking up from idle. Since counter values are _not_
2483	 * saved/restored in idle path, can lead to below "Can't find PMC" message.
2484	 */
2485	if (unlikely(!found) && !arch_irq_disabled_regs(regs))
2486		printk_ratelimited(KERN_WARNING "Can't find PMC that caused IRQ\n");
2487
2488	/*
2489	 * Reset MMCR0 to its normal value.  This will set PMXE and
2490	 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2491	 * and thus allow interrupts to occur again.
2492	 * XXX might want to use MSR.PM to keep the events frozen until
2493	 * we get back out of this interrupt.
2494	 */
2495	write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0);
2496
2497	/* Clear the cpuhw->pmcs */
2498	memset(&cpuhw->pmcs, 0, sizeof(cpuhw->pmcs));
2499
2500}
2501
2502static void perf_event_interrupt(struct pt_regs *regs)
2503{
2504	u64 start_clock = sched_clock();
2505
2506	__perf_event_interrupt(regs);
2507	perf_sample_event_took(sched_clock() - start_clock);
2508}
2509
2510static int power_pmu_prepare_cpu(unsigned int cpu)
2511{
2512	struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2513
2514	if (ppmu) {
2515		memset(cpuhw, 0, sizeof(*cpuhw));
2516		cpuhw->mmcr.mmcr0 = MMCR0_FC;
2517	}
2518	return 0;
2519}
2520
2521static ssize_t pmu_name_show(struct device *cdev,
2522		struct device_attribute *attr,
2523		char *buf)
2524{
2525	if (ppmu)
2526		return sysfs_emit(buf, "%s", ppmu->name);
2527
2528	return 0;
2529}
2530
2531static DEVICE_ATTR_RO(pmu_name);
2532
2533static struct attribute *pmu_caps_attrs[] = {
2534	&dev_attr_pmu_name.attr,
2535	NULL
2536};
2537
2538static const struct attribute_group pmu_caps_group = {
2539	.name  = "caps",
2540	.attrs = pmu_caps_attrs,
2541};
2542
2543static const struct attribute_group *pmu_caps_groups[] = {
2544	&pmu_caps_group,
2545	NULL,
2546};
2547
2548int __init register_power_pmu(struct power_pmu *pmu)
2549{
2550	if (ppmu)
2551		return -EBUSY;		/* something's already registered */
2552
2553	ppmu = pmu;
2554	pr_info("%s performance monitor hardware support registered\n",
2555		pmu->name);
2556
2557	power_pmu.attr_groups = ppmu->attr_groups;
2558
2559	if (ppmu->flags & PPMU_ARCH_207S)
2560		power_pmu.attr_update = pmu_caps_groups;
2561
2562	power_pmu.capabilities |= (ppmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS);
2563
2564#ifdef MSR_HV
2565	/*
2566	 * Use FCHV to ignore kernel events if MSR.HV is set.
2567	 */
2568	if (mfmsr() & MSR_HV)
2569		freeze_events_kernel = MMCR0_FCHV;
2570#endif /* CONFIG_PPC64 */
2571
2572	perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2573	cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2574			  power_pmu_prepare_cpu, NULL);
2575	return 0;
2576}
2577
2578#ifdef CONFIG_PPC64
2579static bool pmu_override = false;
2580static unsigned long pmu_override_val;
2581static void do_pmu_override(void *data)
2582{
2583	ppc_set_pmu_inuse(1);
2584	if (pmu_override_val)
2585		mtspr(SPRN_MMCR1, pmu_override_val);
2586	mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC);
2587}
2588
2589static int __init init_ppc64_pmu(void)
2590{
2591	if (cpu_has_feature(CPU_FTR_HVMODE) && pmu_override) {
2592		pr_warn("disabling perf due to pmu_override= command line option.\n");
2593		on_each_cpu(do_pmu_override, NULL, 1);
2594		return 0;
2595	}
2596
2597	/* run through all the pmu drivers one at a time */
2598	if (!init_power5_pmu())
2599		return 0;
2600	else if (!init_power5p_pmu())
2601		return 0;
2602	else if (!init_power6_pmu())
2603		return 0;
2604	else if (!init_power7_pmu())
2605		return 0;
2606	else if (!init_power8_pmu())
2607		return 0;
2608	else if (!init_power9_pmu())
2609		return 0;
2610	else if (!init_power10_pmu())
2611		return 0;
2612	else if (!init_power11_pmu())
2613		return 0;
2614	else if (!init_ppc970_pmu())
2615		return 0;
2616	else
2617		return init_generic_compat_pmu();
2618}
2619early_initcall(init_ppc64_pmu);
2620
2621static int __init pmu_setup(char *str)
2622{
2623	unsigned long val;
2624
2625	if (!early_cpu_has_feature(CPU_FTR_HVMODE))
2626		return 0;
2627
2628	pmu_override = true;
2629
2630	if (kstrtoul(str, 0, &val))
2631		val = 0;
2632
2633	pmu_override_val = val;
2634
2635	return 1;
2636}
2637__setup("pmu_override=", pmu_setup);
2638
2639#endif