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book3s_pr.c
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linux-6.19.14/arch/powerpc/kvm/book3s_pr.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. 4 * 5 * Authors: 6 * Alexander Graf <agraf@suse.de> 7 * Kevin Wolf <mail@kevin-wolf.de> 8 * Paul Mackerras <paulus@samba.org> 9 * 10 * Description: 11 * Functions relating to running KVM on Book 3S processors where 12 * we don't have access to hypervisor mode, and we run the guest 13 * in problem state (user mode). 14 * 15 * This file is derived from arch/powerpc/kvm/44x.c, 16 * by Hollis Blanchard <hollisb@us.ibm.com>. 17 */ 18 19#include <linux/kvm_host.h> 20#include <linux/export.h> 21#include <linux/err.h> 22#include <linux/slab.h> 23 24#include <asm/reg.h> 25#include <asm/cputable.h> 26#include <asm/cacheflush.h> 27#include <linux/uaccess.h> 28#include <asm/interrupt.h> 29#include <asm/io.h> 30#include <asm/kvm_ppc.h> 31#include <asm/kvm_book3s.h> 32#include <asm/mmu_context.h> 33#include <asm/switch_to.h> 34#include <asm/firmware.h> 35#include <asm/setup.h> 36#include <linux/gfp.h> 37#include <linux/sched.h> 38#include <linux/vmalloc.h> 39#include <linux/highmem.h> 40#include <linux/module.h> 41#include <linux/miscdevice.h> 42#include <asm/asm-prototypes.h> 43#include <asm/tm.h> 44 45#include "book3s.h" 46 47#define CREATE_TRACE_POINTS 48#include "trace_pr.h" 49 50/* #define EXIT_DEBUG */ 51/* #define DEBUG_EXT */ 52 53static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 54 ulong msr); 55#ifdef CONFIG_PPC_BOOK3S_64 56static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac); 57#endif 58 59/* Some compatibility defines */ 60#ifdef CONFIG_PPC_BOOK3S_32 61#define MSR_USER32 MSR_USER 62#define MSR_USER64 MSR_USER 63#define HW_PAGE_SIZE PAGE_SIZE 64#define HPTE_R_M _PAGE_COHERENT 65#endif 66 67static bool kvmppc_is_split_real(struct kvm_vcpu *vcpu) 68{ 69 ulong msr = kvmppc_get_msr(vcpu); 70 return (msr & (MSR_IR|MSR_DR)) == MSR_DR; 71} 72 73static void kvmppc_fixup_split_real(struct kvm_vcpu *vcpu) 74{ 75 ulong msr = kvmppc_get_msr(vcpu); 76 ulong pc = kvmppc_get_pc(vcpu); 77 78 /* We are in DR only split real mode */ 79 if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) 80 return; 81 82 /* We have not fixed up the guest already */ 83 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) 84 return; 85 86 /* The code is in fixupable address space */ 87 if (pc & SPLIT_HACK_MASK) 88 return; 89 90 vcpu->arch.hflags |= BOOK3S_HFLAG_SPLIT_HACK; 91 kvmppc_set_pc(vcpu, pc | SPLIT_HACK_OFFS); 92} 93 94static void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu) 95{ 96 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) { 97 ulong pc = kvmppc_get_pc(vcpu); 98 ulong lr = kvmppc_get_lr(vcpu); 99 if ((pc & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) 100 kvmppc_set_pc(vcpu, pc & ~SPLIT_HACK_MASK); 101 if ((lr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) 102 kvmppc_set_lr(vcpu, lr & ~SPLIT_HACK_MASK); 103 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SPLIT_HACK; 104 } 105} 106 107static void kvmppc_inject_interrupt_pr(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 108{ 109 unsigned long msr, pc, new_msr, new_pc; 110 111 kvmppc_unfixup_split_real(vcpu); 112 113 msr = kvmppc_get_msr(vcpu); 114 pc = kvmppc_get_pc(vcpu); 115 new_msr = vcpu->arch.intr_msr; 116 new_pc = to_book3s(vcpu)->hior + vec; 117 118#ifdef CONFIG_PPC_BOOK3S_64 119 /* If transactional, change to suspend mode on IRQ delivery */ 120 if (MSR_TM_TRANSACTIONAL(msr)) 121 new_msr |= MSR_TS_S; 122 else 123 new_msr |= msr & MSR_TS_MASK; 124#endif 125 126 kvmppc_set_srr0(vcpu, pc); 127 kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 128 kvmppc_set_pc(vcpu, new_pc); 129 kvmppc_set_msr(vcpu, new_msr); 130} 131 132static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) 133{ 134#ifdef CONFIG_PPC_BOOK3S_64 135 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 136 memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb)); 137 svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max; 138 svcpu->in_use = 0; 139 svcpu_put(svcpu); 140 141 /* Disable AIL if supported */ 142 if (cpu_has_feature(CPU_FTR_HVMODE)) { 143 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 144 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_AIL); 145 if (cpu_has_feature(CPU_FTR_ARCH_300) && (current->thread.fscr & FSCR_SCV)) 146 mtspr(SPRN_FSCR, mfspr(SPRN_FSCR) & ~FSCR_SCV); 147 } 148#endif 149 150 vcpu->cpu = smp_processor_id(); 151#ifdef CONFIG_PPC_BOOK3S_32 152 current->thread.kvm_shadow_vcpu = vcpu->arch.shadow_vcpu; 153#endif 154 155 if (kvmppc_is_split_real(vcpu)) 156 kvmppc_fixup_split_real(vcpu); 157 158 kvmppc_restore_tm_pr(vcpu); 159} 160 161static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) 162{ 163#ifdef CONFIG_PPC_BOOK3S_64 164 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 165 if (svcpu->in_use) { 166 kvmppc_copy_from_svcpu(vcpu); 167 } 168 memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb)); 169 to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max; 170 svcpu_put(svcpu); 171 172 /* Enable AIL if supported */ 173 if (cpu_has_feature(CPU_FTR_HVMODE)) { 174 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 175 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_AIL_3); 176 if (cpu_has_feature(CPU_FTR_ARCH_300) && (current->thread.fscr & FSCR_SCV)) 177 mtspr(SPRN_FSCR, mfspr(SPRN_FSCR) | FSCR_SCV); 178 } 179#endif 180 181 if (kvmppc_is_split_real(vcpu)) 182 kvmppc_unfixup_split_real(vcpu); 183 184 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 185 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 186 kvmppc_save_tm_pr(vcpu); 187 188 vcpu->cpu = -1; 189} 190 191/* Copy data needed by real-mode code from vcpu to shadow vcpu */ 192void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu) 193{ 194 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 195 196 svcpu->gpr[0] = vcpu->arch.regs.gpr[0]; 197 svcpu->gpr[1] = vcpu->arch.regs.gpr[1]; 198 svcpu->gpr[2] = vcpu->arch.regs.gpr[2]; 199 svcpu->gpr[3] = vcpu->arch.regs.gpr[3]; 200 svcpu->gpr[4] = vcpu->arch.regs.gpr[4]; 201 svcpu->gpr[5] = vcpu->arch.regs.gpr[5]; 202 svcpu->gpr[6] = vcpu->arch.regs.gpr[6]; 203 svcpu->gpr[7] = vcpu->arch.regs.gpr[7]; 204 svcpu->gpr[8] = vcpu->arch.regs.gpr[8]; 205 svcpu->gpr[9] = vcpu->arch.regs.gpr[9]; 206 svcpu->gpr[10] = vcpu->arch.regs.gpr[10]; 207 svcpu->gpr[11] = vcpu->arch.regs.gpr[11]; 208 svcpu->gpr[12] = vcpu->arch.regs.gpr[12]; 209 svcpu->gpr[13] = vcpu->arch.regs.gpr[13]; 210 svcpu->cr = vcpu->arch.regs.ccr; 211 svcpu->xer = vcpu->arch.regs.xer; 212 svcpu->ctr = vcpu->arch.regs.ctr; 213 svcpu->lr = vcpu->arch.regs.link; 214 svcpu->pc = vcpu->arch.regs.nip; 215#ifdef CONFIG_PPC_BOOK3S_64 216 svcpu->shadow_fscr = vcpu->arch.shadow_fscr; 217#endif 218 /* 219 * Now also save the current time base value. We use this 220 * to find the guest purr and spurr value. 221 */ 222 vcpu->arch.entry_tb = get_tb(); 223 vcpu->arch.entry_vtb = get_vtb(); 224 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 225 vcpu->arch.entry_ic = mfspr(SPRN_IC); 226 svcpu->in_use = true; 227 228 svcpu_put(svcpu); 229} 230 231static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) 232{ 233 ulong guest_msr = kvmppc_get_msr(vcpu); 234 ulong smsr = guest_msr; 235 236 /* Guest MSR values */ 237#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 238 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | 239 MSR_TM | MSR_TS_MASK; 240#else 241 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; 242#endif 243 /* Process MSR values */ 244 smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; 245 /* External providers the guest reserved */ 246 smsr |= (guest_msr & vcpu->arch.guest_owned_ext); 247 /* 64-bit Process MSR values */ 248#ifdef CONFIG_PPC_BOOK3S_64 249 smsr |= MSR_HV; 250#endif 251#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 252 /* 253 * in guest privileged state, we want to fail all TM transactions. 254 * So disable MSR TM bit so that all tbegin. will be able to be 255 * trapped into host. 256 */ 257 if (!(guest_msr & MSR_PR)) 258 smsr &= ~MSR_TM; 259#endif 260 vcpu->arch.shadow_msr = smsr; 261} 262 263/* Copy data touched by real-mode code from shadow vcpu back to vcpu */ 264void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu) 265{ 266 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 267#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 268 ulong old_msr; 269#endif 270 271 /* 272 * Maybe we were already preempted and synced the svcpu from 273 * our preempt notifiers. Don't bother touching this svcpu then. 274 */ 275 if (!svcpu->in_use) 276 goto out; 277 278 vcpu->arch.regs.gpr[0] = svcpu->gpr[0]; 279 vcpu->arch.regs.gpr[1] = svcpu->gpr[1]; 280 vcpu->arch.regs.gpr[2] = svcpu->gpr[2]; 281 vcpu->arch.regs.gpr[3] = svcpu->gpr[3]; 282 vcpu->arch.regs.gpr[4] = svcpu->gpr[4]; 283 vcpu->arch.regs.gpr[5] = svcpu->gpr[5]; 284 vcpu->arch.regs.gpr[6] = svcpu->gpr[6]; 285 vcpu->arch.regs.gpr[7] = svcpu->gpr[7]; 286 vcpu->arch.regs.gpr[8] = svcpu->gpr[8]; 287 vcpu->arch.regs.gpr[9] = svcpu->gpr[9]; 288 vcpu->arch.regs.gpr[10] = svcpu->gpr[10]; 289 vcpu->arch.regs.gpr[11] = svcpu->gpr[11]; 290 vcpu->arch.regs.gpr[12] = svcpu->gpr[12]; 291 vcpu->arch.regs.gpr[13] = svcpu->gpr[13]; 292 vcpu->arch.regs.ccr = svcpu->cr; 293 vcpu->arch.regs.xer = svcpu->xer; 294 vcpu->arch.regs.ctr = svcpu->ctr; 295 vcpu->arch.regs.link = svcpu->lr; 296 vcpu->arch.regs.nip = svcpu->pc; 297 vcpu->arch.shadow_srr1 = svcpu->shadow_srr1; 298 vcpu->arch.fault_dar = svcpu->fault_dar; 299 vcpu->arch.fault_dsisr = svcpu->fault_dsisr; 300 vcpu->arch.last_inst = svcpu->last_inst; 301#ifdef CONFIG_PPC_BOOK3S_64 302 vcpu->arch.shadow_fscr = svcpu->shadow_fscr; 303#endif 304 /* 305 * Update purr and spurr using time base on exit. 306 */ 307 vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb; 308 vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb; 309 to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb; 310 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 311 vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic; 312 313#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 314 /* 315 * Unlike other MSR bits, MSR[TS]bits can be changed at guest without 316 * notifying host: 317 * modified by unprivileged instructions like "tbegin"/"tend"/ 318 * "tresume"/"tsuspend" in PR KVM guest. 319 * 320 * It is necessary to sync here to calculate a correct shadow_msr. 321 * 322 * privileged guest's tbegin will be failed at present. So we 323 * only take care of problem state guest. 324 */ 325 old_msr = kvmppc_get_msr(vcpu); 326 if (unlikely((old_msr & MSR_PR) && 327 (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) != 328 (old_msr & (MSR_TS_MASK)))) { 329 old_msr &= ~(MSR_TS_MASK); 330 old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)); 331 kvmppc_set_msr_fast(vcpu, old_msr); 332 kvmppc_recalc_shadow_msr(vcpu); 333 } 334#endif 335 336 svcpu->in_use = false; 337 338out: 339 svcpu_put(svcpu); 340} 341 342#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 343void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) 344{ 345 tm_enable(); 346 vcpu->arch.tfhar = mfspr(SPRN_TFHAR); 347 vcpu->arch.texasr = mfspr(SPRN_TEXASR); 348 vcpu->arch.tfiar = mfspr(SPRN_TFIAR); 349 tm_disable(); 350} 351 352void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) 353{ 354 tm_enable(); 355 mtspr(SPRN_TFHAR, vcpu->arch.tfhar); 356 mtspr(SPRN_TEXASR, vcpu->arch.texasr); 357 mtspr(SPRN_TFIAR, vcpu->arch.tfiar); 358 tm_disable(); 359} 360 361/* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at 362 * hardware. 363 */ 364static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu) 365{ 366 ulong exit_nr; 367 ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) & 368 (MSR_FP | MSR_VEC | MSR_VSX); 369 370 if (!ext_diff) 371 return; 372 373 if (ext_diff == MSR_FP) 374 exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL; 375 else if (ext_diff == MSR_VEC) 376 exit_nr = BOOK3S_INTERRUPT_ALTIVEC; 377 else 378 exit_nr = BOOK3S_INTERRUPT_VSX; 379 380 kvmppc_handle_ext(vcpu, exit_nr, ext_diff); 381} 382 383void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) 384{ 385 if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) { 386 kvmppc_save_tm_sprs(vcpu); 387 return; 388 } 389 390 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 391 kvmppc_giveup_ext(vcpu, MSR_VSX); 392 393 preempt_disable(); 394 _kvmppc_save_tm_pr(vcpu, mfmsr()); 395 preempt_enable(); 396} 397 398void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) 399{ 400 if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { 401 kvmppc_restore_tm_sprs(vcpu); 402 if (kvmppc_get_msr(vcpu) & MSR_TM) { 403 kvmppc_handle_lost_math_exts(vcpu); 404 if (vcpu->arch.fscr & FSCR_TAR) 405 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 406 } 407 return; 408 } 409 410 preempt_disable(); 411 _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu)); 412 preempt_enable(); 413 414 if (kvmppc_get_msr(vcpu) & MSR_TM) { 415 kvmppc_handle_lost_math_exts(vcpu); 416 if (vcpu->arch.fscr & FSCR_TAR) 417 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 418 } 419} 420#endif 421 422static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu) 423{ 424 int r = 1; /* Indicate we want to get back into the guest */ 425 426 /* We misuse TLB_FLUSH to indicate that we want to clear 427 all shadow cache entries */ 428 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 429 kvmppc_mmu_pte_flush(vcpu, 0, 0); 430 431 return r; 432} 433 434/************* MMU Notifiers *************/ 435static bool do_kvm_unmap_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 436{ 437 unsigned long i; 438 struct kvm_vcpu *vcpu; 439 440 kvm_for_each_vcpu(i, vcpu, kvm) 441 kvmppc_mmu_pte_pflush(vcpu, range->start << PAGE_SHIFT, 442 range->end << PAGE_SHIFT); 443 444 return false; 445} 446 447static bool kvm_unmap_gfn_range_pr(struct kvm *kvm, struct kvm_gfn_range *range) 448{ 449 return do_kvm_unmap_gfn(kvm, range); 450} 451 452static bool kvm_age_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 453{ 454 /* XXX could be more clever ;) */ 455 return false; 456} 457 458static bool kvm_test_age_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 459{ 460 /* XXX could be more clever ;) */ 461 return false; 462} 463 464/*****************************************/ 465 466static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) 467{ 468 ulong old_msr; 469 470 /* For PAPR guest, make sure MSR reflects guest mode */ 471 if (vcpu->arch.papr_enabled) 472 msr = (msr & ~MSR_HV) | MSR_ME; 473 474#ifdef EXIT_DEBUG 475 printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); 476#endif 477 478#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 479 /* We should never target guest MSR to TS=10 && PR=0, 480 * since we always fail transaction for guest privilege 481 * state. 482 */ 483 if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr)) 484 kvmppc_emulate_tabort(vcpu, 485 TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT); 486#endif 487 488 old_msr = kvmppc_get_msr(vcpu); 489 msr &= to_book3s(vcpu)->msr_mask; 490 kvmppc_set_msr_fast(vcpu, msr); 491 kvmppc_recalc_shadow_msr(vcpu); 492 493 if (msr & MSR_POW) { 494 if (!vcpu->arch.pending_exceptions) { 495 kvm_vcpu_halt(vcpu); 496 vcpu->stat.generic.halt_wakeup++; 497 498 /* Unset POW bit after we woke up */ 499 msr &= ~MSR_POW; 500 kvmppc_set_msr_fast(vcpu, msr); 501 } 502 } 503 504 if (kvmppc_is_split_real(vcpu)) 505 kvmppc_fixup_split_real(vcpu); 506 else 507 kvmppc_unfixup_split_real(vcpu); 508 509 if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) != 510 (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { 511 kvmppc_mmu_flush_segments(vcpu); 512 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 513 514 /* Preload magic page segment when in kernel mode */ 515 if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) { 516 struct kvm_vcpu_arch *a = &vcpu->arch; 517 518 if (msr & MSR_DR) 519 kvmppc_mmu_map_segment(vcpu, a->magic_page_ea); 520 else 521 kvmppc_mmu_map_segment(vcpu, a->magic_page_pa); 522 } 523 } 524 525 /* 526 * When switching from 32 to 64-bit, we may have a stale 32-bit 527 * magic page around, we need to flush it. Typically 32-bit magic 528 * page will be instantiated when calling into RTAS. Note: We 529 * assume that such transition only happens while in kernel mode, 530 * ie, we never transition from user 32-bit to kernel 64-bit with 531 * a 32-bit magic page around. 532 */ 533 if (vcpu->arch.magic_page_pa && 534 !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { 535 /* going from RTAS to normal kernel code */ 536 kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa, 537 ~0xFFFUL); 538 } 539 540 /* Preload FPU if it's enabled */ 541 if (kvmppc_get_msr(vcpu) & MSR_FP) 542 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 543 544#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 545 if (kvmppc_get_msr(vcpu) & MSR_TM) 546 kvmppc_handle_lost_math_exts(vcpu); 547#endif 548} 549 550static void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr) 551{ 552 u32 host_pvr; 553 554 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; 555 vcpu->arch.pvr = pvr; 556#ifdef CONFIG_PPC_BOOK3S_64 557 if ((pvr >= 0x330000) && (pvr < 0x70330000)) { 558 kvmppc_mmu_book3s_64_init(vcpu); 559 if (!to_book3s(vcpu)->hior_explicit) 560 to_book3s(vcpu)->hior = 0xfff00000; 561 to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; 562 vcpu->arch.cpu_type = KVM_CPU_3S_64; 563 } else 564#endif 565 { 566 kvmppc_mmu_book3s_32_init(vcpu); 567 if (!to_book3s(vcpu)->hior_explicit) 568 to_book3s(vcpu)->hior = 0; 569 to_book3s(vcpu)->msr_mask = 0xffffffffULL; 570 vcpu->arch.cpu_type = KVM_CPU_3S_32; 571 } 572 573 kvmppc_sanity_check(vcpu); 574 575 /* If we are in hypervisor level on 970, we can tell the CPU to 576 * treat DCBZ as 32 bytes store */ 577 vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; 578 if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && 579 !strcmp(cur_cpu_spec->platform, "ppc970")) 580 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 581 582 /* Cell performs badly if MSR_FEx are set. So let's hope nobody 583 really needs them in a VM on Cell and force disable them. */ 584 if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) 585 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); 586 587 /* 588 * If they're asking for POWER6 or later, set the flag 589 * indicating that we can do multiple large page sizes 590 * and 1TB segments. 591 * Also set the flag that indicates that tlbie has the large 592 * page bit in the RB operand instead of the instruction. 593 */ 594 switch (PVR_VER(pvr)) { 595 case PVR_POWER6: 596 case PVR_POWER7: 597 case PVR_POWER7p: 598 case PVR_POWER8: 599 case PVR_POWER8E: 600 case PVR_POWER8NVL: 601 case PVR_HX_C2000: 602 case PVR_POWER9: 603 vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE | 604 BOOK3S_HFLAG_NEW_TLBIE; 605 break; 606 } 607 608#ifdef CONFIG_PPC_BOOK3S_32 609 /* 32 bit Book3S always has 32 byte dcbz */ 610 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 611#endif 612 613 /* On some CPUs we can execute paired single operations natively */ 614 asm ( "mfpvr %0" : "=r"(host_pvr)); 615 switch (host_pvr) { 616 case 0x00080200: /* lonestar 2.0 */ 617 case 0x00088202: /* lonestar 2.2 */ 618 case 0x70000100: /* gekko 1.0 */ 619 case 0x00080100: /* gekko 2.0 */ 620 case 0x00083203: /* gekko 2.3a */ 621 case 0x00083213: /* gekko 2.3b */ 622 case 0x00083204: /* gekko 2.4 */ 623 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ 624 case 0x00087200: /* broadway */ 625 vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; 626 /* Enable HID2.PSE - in case we need it later */ 627 mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29)); 628 } 629} 630 631/* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To 632 * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to 633 * emulate 32 bytes dcbz length. 634 * 635 * The Book3s_64 inventors also realized this case and implemented a special bit 636 * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. 637 * 638 * My approach here is to patch the dcbz instruction on executing pages. 639 */ 640static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) 641{ 642 struct kvm_host_map map; 643 u64 hpage_offset; 644 u32 *page; 645 int i, r; 646 647 r = kvm_vcpu_map(vcpu, pte->raddr >> PAGE_SHIFT, &map); 648 if (r) 649 return; 650 651 hpage_offset = pte->raddr & ~PAGE_MASK; 652 hpage_offset &= ~0xFFFULL; 653 hpage_offset /= 4; 654 655 page = map.hva; 656 657 /* patch dcbz into reserved instruction, so we trap */ 658 for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) 659 if ((be32_to_cpu(page[i]) & 0xff0007ff) == INS_DCBZ) 660 page[i] &= cpu_to_be32(0xfffffff7); 661 662 kvm_vcpu_unmap(vcpu, &map); 663} 664 665static bool kvmppc_visible_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 666{ 667 ulong mp_pa = vcpu->arch.magic_page_pa; 668 669 if (!(kvmppc_get_msr(vcpu) & MSR_SF)) 670 mp_pa = (uint32_t)mp_pa; 671 672 gpa &= ~0xFFFULL; 673 if (unlikely(mp_pa) && unlikely((mp_pa & KVM_PAM) == (gpa & KVM_PAM))) { 674 return true; 675 } 676 677 return kvm_is_visible_gfn(vcpu->kvm, gpa >> PAGE_SHIFT); 678} 679 680static int kvmppc_handle_pagefault(struct kvm_vcpu *vcpu, 681 ulong eaddr, int vec) 682{ 683 bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE); 684 bool iswrite = false; 685 int r = RESUME_GUEST; 686 int relocated; 687 int page_found = 0; 688 struct kvmppc_pte pte = { 0 }; 689 bool dr = (kvmppc_get_msr(vcpu) & MSR_DR) ? true : false; 690 bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false; 691 u64 vsid; 692 693 relocated = data ? dr : ir; 694 if (data && (vcpu->arch.fault_dsisr & DSISR_ISSTORE)) 695 iswrite = true; 696 697 /* Resolve real address if translation turned on */ 698 if (relocated) { 699 page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data, iswrite); 700 } else { 701 pte.may_execute = true; 702 pte.may_read = true; 703 pte.may_write = true; 704 pte.raddr = eaddr & KVM_PAM; 705 pte.eaddr = eaddr; 706 pte.vpage = eaddr >> 12; 707 pte.page_size = MMU_PAGE_64K; 708 pte.wimg = HPTE_R_M; 709 } 710 711 switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) { 712 case 0: 713 pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12)); 714 break; 715 case MSR_DR: 716 if (!data && 717 (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) && 718 ((pte.raddr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS)) 719 pte.raddr &= ~SPLIT_HACK_MASK; 720 fallthrough; 721 case MSR_IR: 722 vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); 723 724 if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR) 725 pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12)); 726 else 727 pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12)); 728 pte.vpage |= vsid; 729 730 if (vsid == -1) 731 page_found = -EINVAL; 732 break; 733 } 734 735 if (vcpu->arch.mmu.is_dcbz32(vcpu) && 736 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 737 /* 738 * If we do the dcbz hack, we have to NX on every execution, 739 * so we can patch the executing code. This renders our guest 740 * NX-less. 741 */ 742 pte.may_execute = !data; 743 } 744 745 if (page_found == -ENOENT || page_found == -EPERM) { 746 /* Page not found in guest PTE entries, or protection fault */ 747 u64 flags; 748 749 if (page_found == -EPERM) 750 flags = DSISR_PROTFAULT; 751 else 752 flags = DSISR_NOHPTE; 753 if (data) { 754 flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE; 755 kvmppc_core_queue_data_storage(vcpu, 0, eaddr, flags); 756 } else { 757 kvmppc_core_queue_inst_storage(vcpu, flags); 758 } 759 } else if (page_found == -EINVAL) { 760 /* Page not found in guest SLB */ 761 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 762 kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); 763 } else if (kvmppc_visible_gpa(vcpu, pte.raddr)) { 764 if (data && !(vcpu->arch.fault_dsisr & DSISR_NOHPTE)) { 765 /* 766 * There is already a host HPTE there, presumably 767 * a read-only one for a page the guest thinks 768 * is writable, so get rid of it first. 769 */ 770 kvmppc_mmu_unmap_page(vcpu, &pte); 771 } 772 /* The guest's PTE is not mapped yet. Map on the host */ 773 if (kvmppc_mmu_map_page(vcpu, &pte, iswrite) == -EIO) { 774 /* Exit KVM if mapping failed */ 775 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 776 return RESUME_HOST; 777 } 778 if (data) 779 vcpu->stat.sp_storage++; 780 else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 781 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) 782 kvmppc_patch_dcbz(vcpu, &pte); 783 } else { 784 /* MMIO */ 785 vcpu->stat.mmio_exits++; 786 vcpu->arch.paddr_accessed = pte.raddr; 787 vcpu->arch.vaddr_accessed = pte.eaddr; 788 r = kvmppc_emulate_mmio(vcpu); 789 if ( r == RESUME_HOST_NV ) 790 r = RESUME_HOST; 791 } 792 793 return r; 794} 795 796/* Give up external provider (FPU, Altivec, VSX) */ 797void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) 798{ 799 struct thread_struct *t = ¤t->thread; 800 801 /* 802 * VSX instructions can access FP and vector registers, so if 803 * we are giving up VSX, make sure we give up FP and VMX as well. 804 */ 805 if (msr & MSR_VSX) 806 msr |= MSR_FP | MSR_VEC; 807 808 msr &= vcpu->arch.guest_owned_ext; 809 if (!msr) 810 return; 811 812#ifdef DEBUG_EXT 813 printk(KERN_INFO "Giving up ext 0x%lx\n", msr); 814#endif 815 816 if (msr & MSR_FP) { 817 /* 818 * Note that on CPUs with VSX, giveup_fpu stores 819 * both the traditional FP registers and the added VSX 820 * registers into thread.fp_state.fpr[]. 821 */ 822 if (t->regs->msr & MSR_FP) 823 giveup_fpu(current); 824 t->fp_save_area = NULL; 825 } 826 827#ifdef CONFIG_ALTIVEC 828 if (msr & MSR_VEC) { 829 if (current->thread.regs->msr & MSR_VEC) 830 giveup_altivec(current); 831 t->vr_save_area = NULL; 832 } 833#endif 834 835 vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX); 836 kvmppc_recalc_shadow_msr(vcpu); 837} 838 839/* Give up facility (TAR / EBB / DSCR) */ 840void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) 841{ 842#ifdef CONFIG_PPC_BOOK3S_64 843 if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) { 844 /* Facility not available to the guest, ignore giveup request*/ 845 return; 846 } 847 848 switch (fac) { 849 case FSCR_TAR_LG: 850 vcpu->arch.tar = mfspr(SPRN_TAR); 851 mtspr(SPRN_TAR, current->thread.tar); 852 vcpu->arch.shadow_fscr &= ~FSCR_TAR; 853 break; 854 } 855#endif 856} 857 858/* Handle external providers (FPU, Altivec, VSX) */ 859static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 860 ulong msr) 861{ 862 struct thread_struct *t = ¤t->thread; 863 864 /* When we have paired singles, we emulate in software */ 865 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) 866 return RESUME_GUEST; 867 868 if (!(kvmppc_get_msr(vcpu) & msr)) { 869 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 870 return RESUME_GUEST; 871 } 872 873 if (msr == MSR_VSX) { 874 /* No VSX? Give an illegal instruction interrupt */ 875#ifdef CONFIG_VSX 876 if (!cpu_has_feature(CPU_FTR_VSX)) 877#endif 878 { 879 kvmppc_core_queue_program(vcpu, SRR1_PROGILL); 880 return RESUME_GUEST; 881 } 882 883 /* 884 * We have to load up all the FP and VMX registers before 885 * we can let the guest use VSX instructions. 886 */ 887 msr = MSR_FP | MSR_VEC | MSR_VSX; 888 } 889 890 /* See if we already own all the ext(s) needed */ 891 msr &= ~vcpu->arch.guest_owned_ext; 892 if (!msr) 893 return RESUME_GUEST; 894 895#ifdef DEBUG_EXT 896 printk(KERN_INFO "Loading up ext 0x%lx\n", msr); 897#endif 898 899 if (msr & MSR_FP) { 900 preempt_disable(); 901 enable_kernel_fp(); 902 load_fp_state(&vcpu->arch.fp); 903 disable_kernel_fp(); 904 t->fp_save_area = &vcpu->arch.fp; 905 preempt_enable(); 906 } 907 908 if (msr & MSR_VEC) { 909#ifdef CONFIG_ALTIVEC 910 preempt_disable(); 911 enable_kernel_altivec(); 912 load_vr_state(&vcpu->arch.vr); 913 disable_kernel_altivec(); 914 t->vr_save_area = &vcpu->arch.vr; 915 preempt_enable(); 916#endif 917 } 918 919 t->regs->msr |= msr; 920 vcpu->arch.guest_owned_ext |= msr; 921 kvmppc_recalc_shadow_msr(vcpu); 922 923 return RESUME_GUEST; 924} 925 926/* 927 * Kernel code using FP or VMX could have flushed guest state to 928 * the thread_struct; if so, get it back now. 929 */ 930static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu) 931{ 932 unsigned long lost_ext; 933 934 lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr; 935 if (!lost_ext) 936 return; 937 938 if (lost_ext & MSR_FP) { 939 preempt_disable(); 940 enable_kernel_fp(); 941 load_fp_state(&vcpu->arch.fp); 942 disable_kernel_fp(); 943 preempt_enable(); 944 } 945#ifdef CONFIG_ALTIVEC 946 if (lost_ext & MSR_VEC) { 947 preempt_disable(); 948 enable_kernel_altivec(); 949 load_vr_state(&vcpu->arch.vr); 950 disable_kernel_altivec(); 951 preempt_enable(); 952 } 953#endif 954 current->thread.regs->msr |= lost_ext; 955} 956 957#ifdef CONFIG_PPC_BOOK3S_64 958 959void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac) 960{ 961 /* Inject the Interrupt Cause field and trigger a guest interrupt */ 962 vcpu->arch.fscr &= ~(0xffULL << 56); 963 vcpu->arch.fscr |= (fac << 56); 964 kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL); 965} 966 967static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac) 968{ 969 enum emulation_result er = EMULATE_FAIL; 970 971 if (!(kvmppc_get_msr(vcpu) & MSR_PR)) 972 er = kvmppc_emulate_instruction(vcpu); 973 974 if ((er != EMULATE_DONE) && (er != EMULATE_AGAIN)) { 975 /* Couldn't emulate, trigger interrupt in guest */ 976 kvmppc_trigger_fac_interrupt(vcpu, fac); 977 } 978} 979 980/* Enable facilities (TAR, EBB, DSCR) for the guest */ 981static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac) 982{ 983 bool guest_fac_enabled; 984 BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S)); 985 986 /* 987 * Not every facility is enabled by FSCR bits, check whether the 988 * guest has this facility enabled at all. 989 */ 990 switch (fac) { 991 case FSCR_TAR_LG: 992 case FSCR_EBB_LG: 993 guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac)); 994 break; 995 case FSCR_TM_LG: 996 guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; 997 break; 998 default: 999 guest_fac_enabled = false; 1000 break; 1001 } 1002 1003 if (!guest_fac_enabled) { 1004 /* Facility not enabled by the guest */ 1005 kvmppc_trigger_fac_interrupt(vcpu, fac); 1006 return RESUME_GUEST; 1007 } 1008 1009 switch (fac) { 1010 case FSCR_TAR_LG: 1011 /* TAR switching isn't lazy in Linux yet */ 1012 current->thread.tar = mfspr(SPRN_TAR); 1013 mtspr(SPRN_TAR, vcpu->arch.tar); 1014 vcpu->arch.shadow_fscr |= FSCR_TAR; 1015 break; 1016 default: 1017 kvmppc_emulate_fac(vcpu, fac); 1018 break; 1019 } 1020 1021#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1022 /* Since we disabled MSR_TM at privilege state, the mfspr instruction 1023 * for TM spr can trigger TM fac unavailable. In this case, the 1024 * emulation is handled by kvmppc_emulate_fac(), which invokes 1025 * kvmppc_emulate_mfspr() finally. But note the mfspr can include 1026 * RT for NV registers. So it need to restore those NV reg to reflect 1027 * the update. 1028 */ 1029 if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR)) 1030 return RESUME_GUEST_NV; 1031#endif 1032 1033 return RESUME_GUEST; 1034} 1035 1036void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr) 1037{ 1038 if (fscr & FSCR_SCV) 1039 fscr &= ~FSCR_SCV; /* SCV must not be enabled */ 1040 /* Prohibit prefixed instructions for now */ 1041 fscr &= ~FSCR_PREFIX; 1042 if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) { 1043 /* TAR got dropped, drop it in shadow too */ 1044 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1045 } else if (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) { 1046 vcpu->arch.fscr = fscr; 1047 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 1048 return; 1049 } 1050 1051 vcpu->arch.fscr = fscr; 1052} 1053#endif 1054 1055static void kvmppc_setup_debug(struct kvm_vcpu *vcpu) 1056{ 1057 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1058 u64 msr = kvmppc_get_msr(vcpu); 1059 1060 kvmppc_set_msr(vcpu, msr | MSR_SE); 1061 } 1062} 1063 1064static void kvmppc_clear_debug(struct kvm_vcpu *vcpu) 1065{ 1066 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1067 u64 msr = kvmppc_get_msr(vcpu); 1068 1069 kvmppc_set_msr(vcpu, msr & ~MSR_SE); 1070 } 1071} 1072 1073static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr) 1074{ 1075 enum emulation_result er; 1076 ulong flags; 1077 ppc_inst_t last_inst; 1078 int emul, r; 1079 1080 /* 1081 * shadow_srr1 only contains valid flags if we came here via a program 1082 * exception. The other exceptions (emulation assist, FP unavailable, 1083 * etc.) do not provide flags in SRR1, so use an illegal-instruction 1084 * exception when injecting a program interrupt into the guest. 1085 */ 1086 if (exit_nr == BOOK3S_INTERRUPT_PROGRAM) 1087 flags = vcpu->arch.shadow_srr1 & 0x1f0000ull; 1088 else 1089 flags = SRR1_PROGILL; 1090 1091 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1092 if (emul != EMULATE_DONE) 1093 return RESUME_GUEST; 1094 1095 if (kvmppc_get_msr(vcpu) & MSR_PR) { 1096#ifdef EXIT_DEBUG 1097 pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n", 1098 kvmppc_get_pc(vcpu), ppc_inst_val(last_inst)); 1099#endif 1100 if ((ppc_inst_val(last_inst) & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) { 1101 kvmppc_core_queue_program(vcpu, flags); 1102 return RESUME_GUEST; 1103 } 1104 } 1105 1106 vcpu->stat.emulated_inst_exits++; 1107 er = kvmppc_emulate_instruction(vcpu); 1108 switch (er) { 1109 case EMULATE_DONE: 1110 r = RESUME_GUEST_NV; 1111 break; 1112 case EMULATE_AGAIN: 1113 r = RESUME_GUEST; 1114 break; 1115 case EMULATE_FAIL: 1116 pr_crit("%s: emulation at %lx failed (%08x)\n", 1117 __func__, kvmppc_get_pc(vcpu), ppc_inst_val(last_inst)); 1118 kvmppc_core_queue_program(vcpu, flags); 1119 r = RESUME_GUEST; 1120 break; 1121 case EMULATE_DO_MMIO: 1122 vcpu->run->exit_reason = KVM_EXIT_MMIO; 1123 r = RESUME_HOST_NV; 1124 break; 1125 case EMULATE_EXIT_USER: 1126 r = RESUME_HOST_NV; 1127 break; 1128 default: 1129 BUG(); 1130 } 1131 1132 return r; 1133} 1134 1135int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr) 1136{ 1137 struct kvm_run *run = vcpu->run; 1138 int r = RESUME_HOST; 1139 int s; 1140 1141 vcpu->stat.sum_exits++; 1142 1143 run->exit_reason = KVM_EXIT_UNKNOWN; 1144 run->ready_for_interrupt_injection = 1; 1145 1146 /* We get here with MSR.EE=1 */ 1147 1148 trace_kvm_exit(exit_nr, vcpu); 1149 guest_exit(); 1150 1151 switch (exit_nr) { 1152 case BOOK3S_INTERRUPT_INST_STORAGE: 1153 { 1154 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1155 vcpu->stat.pf_instruc++; 1156 1157 if (kvmppc_is_split_real(vcpu)) 1158 kvmppc_fixup_split_real(vcpu); 1159 1160#ifdef CONFIG_PPC_BOOK3S_32 1161 /* We set segments as unused segments when invalidating them. So 1162 * treat the respective fault as segment fault. */ 1163 { 1164 struct kvmppc_book3s_shadow_vcpu *svcpu; 1165 u32 sr; 1166 1167 svcpu = svcpu_get(vcpu); 1168 sr = svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT]; 1169 svcpu_put(svcpu); 1170 if (sr == SR_INVALID) { 1171 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 1172 r = RESUME_GUEST; 1173 break; 1174 } 1175 } 1176#endif 1177 1178 /* only care about PTEG not found errors, but leave NX alone */ 1179 if (shadow_srr1 & 0x40000000) { 1180 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1181 r = kvmppc_handle_pagefault(vcpu, kvmppc_get_pc(vcpu), exit_nr); 1182 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1183 vcpu->stat.sp_instruc++; 1184 } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 1185 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 1186 /* 1187 * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, 1188 * so we can't use the NX bit inside the guest. Let's cross our fingers, 1189 * that no guest that needs the dcbz hack does NX. 1190 */ 1191 kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); 1192 r = RESUME_GUEST; 1193 } else { 1194 kvmppc_core_queue_inst_storage(vcpu, 1195 shadow_srr1 & 0x58000000); 1196 r = RESUME_GUEST; 1197 } 1198 break; 1199 } 1200 case BOOK3S_INTERRUPT_DATA_STORAGE: 1201 { 1202 ulong dar = kvmppc_get_fault_dar(vcpu); 1203 u32 fault_dsisr = vcpu->arch.fault_dsisr; 1204 vcpu->stat.pf_storage++; 1205 1206#ifdef CONFIG_PPC_BOOK3S_32 1207 /* We set segments as unused segments when invalidating them. So 1208 * treat the respective fault as segment fault. */ 1209 { 1210 struct kvmppc_book3s_shadow_vcpu *svcpu; 1211 u32 sr; 1212 1213 svcpu = svcpu_get(vcpu); 1214 sr = svcpu->sr[dar >> SID_SHIFT]; 1215 svcpu_put(svcpu); 1216 if (sr == SR_INVALID) { 1217 kvmppc_mmu_map_segment(vcpu, dar); 1218 r = RESUME_GUEST; 1219 break; 1220 } 1221 } 1222#endif 1223 1224 /* 1225 * We need to handle missing shadow PTEs, and 1226 * protection faults due to us mapping a page read-only 1227 * when the guest thinks it is writable. 1228 */ 1229 if (fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT)) { 1230 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1231 r = kvmppc_handle_pagefault(vcpu, dar, exit_nr); 1232 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1233 } else { 1234 kvmppc_core_queue_data_storage(vcpu, 0, dar, fault_dsisr); 1235 r = RESUME_GUEST; 1236 } 1237 break; 1238 } 1239 case BOOK3S_INTERRUPT_DATA_SEGMENT: 1240 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) { 1241 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 1242 kvmppc_book3s_queue_irqprio(vcpu, 1243 BOOK3S_INTERRUPT_DATA_SEGMENT); 1244 } 1245 r = RESUME_GUEST; 1246 break; 1247 case BOOK3S_INTERRUPT_INST_SEGMENT: 1248 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) { 1249 kvmppc_book3s_queue_irqprio(vcpu, 1250 BOOK3S_INTERRUPT_INST_SEGMENT); 1251 } 1252 r = RESUME_GUEST; 1253 break; 1254 /* We're good on these - the host merely wanted to get our attention */ 1255 case BOOK3S_INTERRUPT_DECREMENTER: 1256 case BOOK3S_INTERRUPT_HV_DECREMENTER: 1257 case BOOK3S_INTERRUPT_DOORBELL: 1258 case BOOK3S_INTERRUPT_H_DOORBELL: 1259 vcpu->stat.dec_exits++; 1260 r = RESUME_GUEST; 1261 break; 1262 case BOOK3S_INTERRUPT_EXTERNAL: 1263 case BOOK3S_INTERRUPT_EXTERNAL_HV: 1264 case BOOK3S_INTERRUPT_H_VIRT: 1265 vcpu->stat.ext_intr_exits++; 1266 r = RESUME_GUEST; 1267 break; 1268 case BOOK3S_INTERRUPT_HMI: 1269 case BOOK3S_INTERRUPT_PERFMON: 1270 case BOOK3S_INTERRUPT_SYSTEM_RESET: 1271 r = RESUME_GUEST; 1272 break; 1273 case BOOK3S_INTERRUPT_PROGRAM: 1274 case BOOK3S_INTERRUPT_H_EMUL_ASSIST: 1275 r = kvmppc_exit_pr_progint(vcpu, exit_nr); 1276 break; 1277 case BOOK3S_INTERRUPT_SYSCALL: 1278 { 1279 ppc_inst_t last_sc; 1280 int emul; 1281 1282 /* Get last sc for papr */ 1283 if (vcpu->arch.papr_enabled) { 1284 /* The sc instruction points SRR0 to the next inst */ 1285 emul = kvmppc_get_last_inst(vcpu, INST_SC, &last_sc); 1286 if (emul != EMULATE_DONE) { 1287 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) - 4); 1288 r = RESUME_GUEST; 1289 break; 1290 } 1291 } 1292 1293 if (vcpu->arch.papr_enabled && 1294 (ppc_inst_val(last_sc) == 0x44000022) && 1295 !(kvmppc_get_msr(vcpu) & MSR_PR)) { 1296 /* SC 1 papr hypercalls */ 1297 ulong cmd = kvmppc_get_gpr(vcpu, 3); 1298 int i; 1299 1300#ifdef CONFIG_PPC_BOOK3S_64 1301 if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) { 1302 r = RESUME_GUEST; 1303 break; 1304 } 1305#endif 1306 1307 run->papr_hcall.nr = cmd; 1308 for (i = 0; i < 9; ++i) { 1309 ulong gpr = kvmppc_get_gpr(vcpu, 4 + i); 1310 run->papr_hcall.args[i] = gpr; 1311 } 1312 run->exit_reason = KVM_EXIT_PAPR_HCALL; 1313 vcpu->arch.hcall_needed = 1; 1314 r = RESUME_HOST; 1315 } else if (vcpu->arch.osi_enabled && 1316 (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) && 1317 (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) { 1318 /* MOL hypercalls */ 1319 u64 *gprs = run->osi.gprs; 1320 int i; 1321 1322 run->exit_reason = KVM_EXIT_OSI; 1323 for (i = 0; i < 32; i++) 1324 gprs[i] = kvmppc_get_gpr(vcpu, i); 1325 vcpu->arch.osi_needed = 1; 1326 r = RESUME_HOST_NV; 1327 } else if (!(kvmppc_get_msr(vcpu) & MSR_PR) && 1328 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { 1329 /* KVM PV hypercalls */ 1330 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); 1331 r = RESUME_GUEST; 1332 } else { 1333 /* Guest syscalls */ 1334 vcpu->stat.syscall_exits++; 1335 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1336 r = RESUME_GUEST; 1337 } 1338 break; 1339 } 1340 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1341 case BOOK3S_INTERRUPT_ALTIVEC: 1342 case BOOK3S_INTERRUPT_VSX: 1343 { 1344 int ext_msr = 0; 1345 int emul; 1346 ppc_inst_t last_inst; 1347 1348 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) { 1349 /* Do paired single instruction emulation */ 1350 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, 1351 &last_inst); 1352 if (emul == EMULATE_DONE) 1353 r = kvmppc_exit_pr_progint(vcpu, exit_nr); 1354 else 1355 r = RESUME_GUEST; 1356 1357 break; 1358 } 1359 1360 /* Enable external provider */ 1361 switch (exit_nr) { 1362 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1363 ext_msr = MSR_FP; 1364 break; 1365 1366 case BOOK3S_INTERRUPT_ALTIVEC: 1367 ext_msr = MSR_VEC; 1368 break; 1369 1370 case BOOK3S_INTERRUPT_VSX: 1371 ext_msr = MSR_VSX; 1372 break; 1373 } 1374 1375 r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr); 1376 break; 1377 } 1378 case BOOK3S_INTERRUPT_ALIGNMENT: 1379 { 1380 ppc_inst_t last_inst; 1381 int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1382 1383 if (emul == EMULATE_DONE) { 1384 u32 dsisr; 1385 u64 dar; 1386 1387 dsisr = kvmppc_alignment_dsisr(vcpu, ppc_inst_val(last_inst)); 1388 dar = kvmppc_alignment_dar(vcpu, ppc_inst_val(last_inst)); 1389 1390 kvmppc_set_dsisr(vcpu, dsisr); 1391 kvmppc_set_dar(vcpu, dar); 1392 1393 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1394 } 1395 r = RESUME_GUEST; 1396 break; 1397 } 1398#ifdef CONFIG_PPC_BOOK3S_64 1399 case BOOK3S_INTERRUPT_FAC_UNAVAIL: 1400 r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); 1401 break; 1402#endif 1403 case BOOK3S_INTERRUPT_MACHINE_CHECK: 1404 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1405 r = RESUME_GUEST; 1406 break; 1407 case BOOK3S_INTERRUPT_TRACE: 1408 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1409 run->exit_reason = KVM_EXIT_DEBUG; 1410 r = RESUME_HOST; 1411 } else { 1412 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1413 r = RESUME_GUEST; 1414 } 1415 break; 1416 default: 1417 { 1418 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1419 /* Ugh - bork here! What did we get? */ 1420 printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", 1421 exit_nr, kvmppc_get_pc(vcpu), shadow_srr1); 1422 r = RESUME_HOST; 1423 BUG(); 1424 break; 1425 } 1426 } 1427 1428 if (!(r & RESUME_HOST)) { 1429 /* To avoid clobbering exit_reason, only check for signals if 1430 * we aren't already exiting to userspace for some other 1431 * reason. */ 1432 1433 /* 1434 * Interrupts could be timers for the guest which we have to 1435 * inject again, so let's postpone them until we're in the guest 1436 * and if we really did time things so badly, then we just exit 1437 * again due to a host external interrupt. 1438 */ 1439 s = kvmppc_prepare_to_enter(vcpu); 1440 if (s <= 0) 1441 r = s; 1442 else { 1443 /* interrupts now hard-disabled */ 1444 kvmppc_fix_ee_before_entry(); 1445 } 1446 1447 kvmppc_handle_lost_ext(vcpu); 1448 } 1449 1450 trace_kvm_book3s_reenter(r, vcpu); 1451 1452 return r; 1453} 1454 1455static int kvm_arch_vcpu_ioctl_get_sregs_pr(struct kvm_vcpu *vcpu, 1456 struct kvm_sregs *sregs) 1457{ 1458 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1459 int i; 1460 1461 sregs->pvr = vcpu->arch.pvr; 1462 1463 sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; 1464 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1465 for (i = 0; i < 64; i++) { 1466 sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i; 1467 sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv; 1468 } 1469 } else { 1470 for (i = 0; i < 16; i++) 1471 sregs->u.s.ppc32.sr[i] = kvmppc_get_sr(vcpu, i); 1472 1473 for (i = 0; i < 8; i++) { 1474 sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw; 1475 sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; 1476 } 1477 } 1478 1479 return 0; 1480} 1481 1482static int kvm_arch_vcpu_ioctl_set_sregs_pr(struct kvm_vcpu *vcpu, 1483 struct kvm_sregs *sregs) 1484{ 1485 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1486 int i; 1487 1488 kvmppc_set_pvr_pr(vcpu, sregs->pvr); 1489 1490 vcpu3s->sdr1 = sregs->u.s.sdr1; 1491#ifdef CONFIG_PPC_BOOK3S_64 1492 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1493 /* Flush all SLB entries */ 1494 vcpu->arch.mmu.slbmte(vcpu, 0, 0); 1495 vcpu->arch.mmu.slbia(vcpu); 1496 1497 for (i = 0; i < 64; i++) { 1498 u64 rb = sregs->u.s.ppc64.slb[i].slbe; 1499 u64 rs = sregs->u.s.ppc64.slb[i].slbv; 1500 1501 if (rb & SLB_ESID_V) 1502 vcpu->arch.mmu.slbmte(vcpu, rs, rb); 1503 } 1504 } else 1505#endif 1506 { 1507 for (i = 0; i < 16; i++) { 1508 vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]); 1509 } 1510 for (i = 0; i < 8; i++) { 1511 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false, 1512 (u32)sregs->u.s.ppc32.ibat[i]); 1513 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true, 1514 (u32)(sregs->u.s.ppc32.ibat[i] >> 32)); 1515 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false, 1516 (u32)sregs->u.s.ppc32.dbat[i]); 1517 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true, 1518 (u32)(sregs->u.s.ppc32.dbat[i] >> 32)); 1519 } 1520 } 1521 1522 /* Flush the MMU after messing with the segments */ 1523 kvmppc_mmu_pte_flush(vcpu, 0, 0); 1524 1525 return 0; 1526} 1527 1528static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1529 union kvmppc_one_reg *val) 1530{ 1531 int r = 0; 1532 1533 switch (id) { 1534 case KVM_REG_PPC_DEBUG_INST: 1535 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); 1536 break; 1537 case KVM_REG_PPC_HIOR: 1538 *val = get_reg_val(id, to_book3s(vcpu)->hior); 1539 break; 1540 case KVM_REG_PPC_VTB: 1541 *val = get_reg_val(id, to_book3s(vcpu)->vtb); 1542 break; 1543 case KVM_REG_PPC_LPCR: 1544 case KVM_REG_PPC_LPCR_64: 1545 /* 1546 * We are only interested in the LPCR_ILE bit 1547 */ 1548 if (vcpu->arch.intr_msr & MSR_LE) 1549 *val = get_reg_val(id, LPCR_ILE); 1550 else 1551 *val = get_reg_val(id, 0); 1552 break; 1553#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1554 case KVM_REG_PPC_TFHAR: 1555 *val = get_reg_val(id, vcpu->arch.tfhar); 1556 break; 1557 case KVM_REG_PPC_TFIAR: 1558 *val = get_reg_val(id, vcpu->arch.tfiar); 1559 break; 1560 case KVM_REG_PPC_TEXASR: 1561 *val = get_reg_val(id, vcpu->arch.texasr); 1562 break; 1563 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1564 *val = get_reg_val(id, 1565 vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]); 1566 break; 1567 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1568 { 1569 int i, j; 1570 1571 i = id - KVM_REG_PPC_TM_VSR0; 1572 if (i < 32) 1573 for (j = 0; j < TS_FPRWIDTH; j++) 1574 val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; 1575 else { 1576 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1577 val->vval = vcpu->arch.vr_tm.vr[i-32]; 1578 else 1579 r = -ENXIO; 1580 } 1581 break; 1582 } 1583 case KVM_REG_PPC_TM_CR: 1584 *val = get_reg_val(id, vcpu->arch.cr_tm); 1585 break; 1586 case KVM_REG_PPC_TM_XER: 1587 *val = get_reg_val(id, vcpu->arch.xer_tm); 1588 break; 1589 case KVM_REG_PPC_TM_LR: 1590 *val = get_reg_val(id, vcpu->arch.lr_tm); 1591 break; 1592 case KVM_REG_PPC_TM_CTR: 1593 *val = get_reg_val(id, vcpu->arch.ctr_tm); 1594 break; 1595 case KVM_REG_PPC_TM_FPSCR: 1596 *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); 1597 break; 1598 case KVM_REG_PPC_TM_AMR: 1599 *val = get_reg_val(id, vcpu->arch.amr_tm); 1600 break; 1601 case KVM_REG_PPC_TM_PPR: 1602 *val = get_reg_val(id, vcpu->arch.ppr_tm); 1603 break; 1604 case KVM_REG_PPC_TM_VRSAVE: 1605 *val = get_reg_val(id, vcpu->arch.vrsave_tm); 1606 break; 1607 case KVM_REG_PPC_TM_VSCR: 1608 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1609 *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); 1610 else 1611 r = -ENXIO; 1612 break; 1613 case KVM_REG_PPC_TM_DSCR: 1614 *val = get_reg_val(id, vcpu->arch.dscr_tm); 1615 break; 1616 case KVM_REG_PPC_TM_TAR: 1617 *val = get_reg_val(id, vcpu->arch.tar_tm); 1618 break; 1619#endif 1620 default: 1621 r = -EINVAL; 1622 break; 1623 } 1624 1625 return r; 1626} 1627 1628static void kvmppc_set_lpcr_pr(struct kvm_vcpu *vcpu, u64 new_lpcr) 1629{ 1630 if (new_lpcr & LPCR_ILE) 1631 vcpu->arch.intr_msr |= MSR_LE; 1632 else 1633 vcpu->arch.intr_msr &= ~MSR_LE; 1634} 1635 1636static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1637 union kvmppc_one_reg *val) 1638{ 1639 int r = 0; 1640 1641 switch (id) { 1642 case KVM_REG_PPC_HIOR: 1643 to_book3s(vcpu)->hior = set_reg_val(id, *val); 1644 to_book3s(vcpu)->hior_explicit = true; 1645 break; 1646 case KVM_REG_PPC_VTB: 1647 to_book3s(vcpu)->vtb = set_reg_val(id, *val); 1648 break; 1649 case KVM_REG_PPC_LPCR: 1650 case KVM_REG_PPC_LPCR_64: 1651 kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val)); 1652 break; 1653#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1654 case KVM_REG_PPC_TFHAR: 1655 vcpu->arch.tfhar = set_reg_val(id, *val); 1656 break; 1657 case KVM_REG_PPC_TFIAR: 1658 vcpu->arch.tfiar = set_reg_val(id, *val); 1659 break; 1660 case KVM_REG_PPC_TEXASR: 1661 vcpu->arch.texasr = set_reg_val(id, *val); 1662 break; 1663 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1664 vcpu->arch.gpr_tm[id - KVM_REG_PPC_TM_GPR0] = 1665 set_reg_val(id, *val); 1666 break; 1667 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1668 { 1669 int i, j; 1670 1671 i = id - KVM_REG_PPC_TM_VSR0; 1672 if (i < 32) 1673 for (j = 0; j < TS_FPRWIDTH; j++) 1674 vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; 1675 else 1676 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1677 vcpu->arch.vr_tm.vr[i-32] = val->vval; 1678 else 1679 r = -ENXIO; 1680 break; 1681 } 1682 case KVM_REG_PPC_TM_CR: 1683 vcpu->arch.cr_tm = set_reg_val(id, *val); 1684 break; 1685 case KVM_REG_PPC_TM_XER: 1686 vcpu->arch.xer_tm = set_reg_val(id, *val); 1687 break; 1688 case KVM_REG_PPC_TM_LR: 1689 vcpu->arch.lr_tm = set_reg_val(id, *val); 1690 break; 1691 case KVM_REG_PPC_TM_CTR: 1692 vcpu->arch.ctr_tm = set_reg_val(id, *val); 1693 break; 1694 case KVM_REG_PPC_TM_FPSCR: 1695 vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); 1696 break; 1697 case KVM_REG_PPC_TM_AMR: 1698 vcpu->arch.amr_tm = set_reg_val(id, *val); 1699 break; 1700 case KVM_REG_PPC_TM_PPR: 1701 vcpu->arch.ppr_tm = set_reg_val(id, *val); 1702 break; 1703 case KVM_REG_PPC_TM_VRSAVE: 1704 vcpu->arch.vrsave_tm = set_reg_val(id, *val); 1705 break; 1706 case KVM_REG_PPC_TM_VSCR: 1707 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1708 vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); 1709 else 1710 r = -ENXIO; 1711 break; 1712 case KVM_REG_PPC_TM_DSCR: 1713 vcpu->arch.dscr_tm = set_reg_val(id, *val); 1714 break; 1715 case KVM_REG_PPC_TM_TAR: 1716 vcpu->arch.tar_tm = set_reg_val(id, *val); 1717 break; 1718#endif 1719 default: 1720 r = -EINVAL; 1721 break; 1722 } 1723 1724 return r; 1725} 1726 1727static int kvmppc_core_vcpu_create_pr(struct kvm_vcpu *vcpu) 1728{ 1729 struct kvmppc_vcpu_book3s *vcpu_book3s; 1730 unsigned long p; 1731 int err; 1732 1733 err = -ENOMEM; 1734 1735 vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s)); 1736 if (!vcpu_book3s) 1737 goto out; 1738 vcpu->arch.book3s = vcpu_book3s; 1739 1740#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1741 vcpu->arch.shadow_vcpu = 1742 kzalloc(sizeof(*vcpu->arch.shadow_vcpu), GFP_KERNEL); 1743 if (!vcpu->arch.shadow_vcpu) 1744 goto free_vcpu3s; 1745#endif 1746 1747 p = __get_free_page(GFP_KERNEL|__GFP_ZERO); 1748 if (!p) 1749 goto free_shadow_vcpu; 1750 vcpu->arch.shared = (void *)p; 1751#ifdef CONFIG_PPC_BOOK3S_64 1752 /* Always start the shared struct in native endian mode */ 1753#ifdef __BIG_ENDIAN__ 1754 vcpu->arch.shared_big_endian = true; 1755#else 1756 vcpu->arch.shared_big_endian = false; 1757#endif 1758 1759 /* 1760 * Default to the same as the host if we're on sufficiently 1761 * recent machine that we have 1TB segments; 1762 * otherwise default to PPC970FX. 1763 */ 1764 vcpu->arch.pvr = 0x3C0301; 1765 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1766 vcpu->arch.pvr = mfspr(SPRN_PVR); 1767 vcpu->arch.intr_msr = MSR_SF; 1768#else 1769 /* default to book3s_32 (750) */ 1770 vcpu->arch.pvr = 0x84202; 1771 vcpu->arch.intr_msr = 0; 1772#endif 1773 kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr); 1774 vcpu->arch.slb_nr = 64; 1775 1776 vcpu->arch.shadow_msr = MSR_USER64 & ~MSR_LE; 1777 1778 err = kvmppc_mmu_init_pr(vcpu); 1779 if (err < 0) 1780 goto free_shared_page; 1781 1782 return 0; 1783 1784free_shared_page: 1785 free_page((unsigned long)vcpu->arch.shared); 1786free_shadow_vcpu: 1787#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1788 kfree(vcpu->arch.shadow_vcpu); 1789free_vcpu3s: 1790#endif 1791 vfree(vcpu_book3s); 1792out: 1793 return err; 1794} 1795 1796static void kvmppc_core_vcpu_free_pr(struct kvm_vcpu *vcpu) 1797{ 1798 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); 1799 1800 kvmppc_mmu_destroy_pr(vcpu); 1801 free_page((unsigned long)vcpu->arch.shared & PAGE_MASK); 1802#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1803 kfree(vcpu->arch.shadow_vcpu); 1804#endif 1805 vfree(vcpu_book3s); 1806} 1807 1808static int kvmppc_vcpu_run_pr(struct kvm_vcpu *vcpu) 1809{ 1810 int ret; 1811 1812 /* Check if we can run the vcpu at all */ 1813 if (!vcpu->arch.sane) { 1814 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1815 ret = -EINVAL; 1816 goto out; 1817 } 1818 1819 kvmppc_setup_debug(vcpu); 1820 1821 /* 1822 * Interrupts could be timers for the guest which we have to inject 1823 * again, so let's postpone them until we're in the guest and if we 1824 * really did time things so badly, then we just exit again due to 1825 * a host external interrupt. 1826 */ 1827 ret = kvmppc_prepare_to_enter(vcpu); 1828 if (ret <= 0) 1829 goto out; 1830 /* interrupts now hard-disabled */ 1831 1832 /* Save FPU, Altivec and VSX state */ 1833 giveup_all(current); 1834 1835 /* Preload FPU if it's enabled */ 1836 if (kvmppc_get_msr(vcpu) & MSR_FP) 1837 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 1838 1839 kvmppc_fix_ee_before_entry(); 1840 1841 ret = __kvmppc_vcpu_run(vcpu); 1842 1843 kvmppc_clear_debug(vcpu); 1844 1845 /* No need for guest_exit. It's done in handle_exit. 1846 We also get here with interrupts enabled. */ 1847 1848 /* Make sure we save the guest FPU/Altivec/VSX state */ 1849 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 1850 1851 /* Make sure we save the guest TAR/EBB/DSCR state */ 1852 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1853 1854 srr_regs_clobbered(); 1855out: 1856 vcpu->mode = OUTSIDE_GUEST_MODE; 1857 return ret; 1858} 1859 1860/* 1861 * Get (and clear) the dirty memory log for a memory slot. 1862 */ 1863static int kvm_vm_ioctl_get_dirty_log_pr(struct kvm *kvm, 1864 struct kvm_dirty_log *log) 1865{ 1866 struct kvm_memory_slot *memslot; 1867 struct kvm_vcpu *vcpu; 1868 ulong ga, ga_end; 1869 int is_dirty = 0; 1870 int r; 1871 unsigned long n; 1872 1873 mutex_lock(&kvm->slots_lock); 1874 1875 r = kvm_get_dirty_log(kvm, log, &is_dirty, &memslot); 1876 if (r) 1877 goto out; 1878 1879 /* If nothing is dirty, don't bother messing with page tables. */ 1880 if (is_dirty) { 1881 ga = memslot->base_gfn << PAGE_SHIFT; 1882 ga_end = ga + (memslot->npages << PAGE_SHIFT); 1883 1884 kvm_for_each_vcpu(n, vcpu, kvm) 1885 kvmppc_mmu_pte_pflush(vcpu, ga, ga_end); 1886 1887 n = kvm_dirty_bitmap_bytes(memslot); 1888 memset(memslot->dirty_bitmap, 0, n); 1889 } 1890 1891 r = 0; 1892out: 1893 mutex_unlock(&kvm->slots_lock); 1894 return r; 1895} 1896 1897static void kvmppc_core_flush_memslot_pr(struct kvm *kvm, 1898 struct kvm_memory_slot *memslot) 1899{ 1900 return; 1901} 1902 1903static int kvmppc_core_prepare_memory_region_pr(struct kvm *kvm, 1904 const struct kvm_memory_slot *old, 1905 struct kvm_memory_slot *new, 1906 enum kvm_mr_change change) 1907{ 1908 return 0; 1909} 1910 1911static void kvmppc_core_commit_memory_region_pr(struct kvm *kvm, 1912 struct kvm_memory_slot *old, 1913 const struct kvm_memory_slot *new, 1914 enum kvm_mr_change change) 1915{ 1916 return; 1917} 1918 1919static void kvmppc_core_free_memslot_pr(struct kvm_memory_slot *slot) 1920{ 1921 return; 1922} 1923 1924#ifdef CONFIG_PPC64 1925static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1926 struct kvm_ppc_smmu_info *info) 1927{ 1928 long int i; 1929 struct kvm_vcpu *vcpu; 1930 1931 info->flags = 0; 1932 1933 /* SLB is always 64 entries */ 1934 info->slb_size = 64; 1935 1936 /* Standard 4k base page size segment */ 1937 info->sps[0].page_shift = 12; 1938 info->sps[0].slb_enc = 0; 1939 info->sps[0].enc[0].page_shift = 12; 1940 info->sps[0].enc[0].pte_enc = 0; 1941 1942 /* 1943 * 64k large page size. 1944 * We only want to put this in if the CPUs we're emulating 1945 * support it, but unfortunately we don't have a vcpu easily 1946 * to hand here to test. Just pick the first vcpu, and if 1947 * that doesn't exist yet, report the minimum capability, 1948 * i.e., no 64k pages. 1949 * 1T segment support goes along with 64k pages. 1950 */ 1951 i = 1; 1952 vcpu = kvm_get_vcpu(kvm, 0); 1953 if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) { 1954 info->flags = KVM_PPC_1T_SEGMENTS; 1955 info->sps[i].page_shift = 16; 1956 info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01; 1957 info->sps[i].enc[0].page_shift = 16; 1958 info->sps[i].enc[0].pte_enc = 1; 1959 ++i; 1960 } 1961 1962 /* Standard 16M large page size segment */ 1963 info->sps[i].page_shift = 24; 1964 info->sps[i].slb_enc = SLB_VSID_L; 1965 info->sps[i].enc[0].page_shift = 24; 1966 info->sps[i].enc[0].pte_enc = 0; 1967 1968 return 0; 1969} 1970 1971static int kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg) 1972{ 1973 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1974 return -ENODEV; 1975 /* Require flags and process table base and size to all be zero. */ 1976 if (cfg->flags || cfg->process_table) 1977 return -EINVAL; 1978 return 0; 1979} 1980 1981#else 1982static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1983 struct kvm_ppc_smmu_info *info) 1984{ 1985 /* We should not get called */ 1986 BUG(); 1987 return 0; 1988} 1989#endif /* CONFIG_PPC64 */ 1990 1991static unsigned int kvm_global_user_count = 0; 1992static DEFINE_SPINLOCK(kvm_global_user_count_lock); 1993 1994static int kvmppc_core_init_vm_pr(struct kvm *kvm) 1995{ 1996 mutex_init(&kvm->arch.hpt_mutex); 1997 1998#ifdef CONFIG_PPC_BOOK3S_64 1999 /* Start out with the default set of hcalls enabled */ 2000 kvmppc_pr_init_default_hcalls(kvm); 2001#endif 2002 2003 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2004 spin_lock(&kvm_global_user_count_lock); 2005 if (++kvm_global_user_count == 1) 2006 pseries_disable_reloc_on_exc(); 2007 spin_unlock(&kvm_global_user_count_lock); 2008 } 2009 return 0; 2010} 2011 2012static void kvmppc_core_destroy_vm_pr(struct kvm *kvm) 2013{ 2014#ifdef CONFIG_PPC64 2015 WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables)); 2016#endif 2017 2018 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2019 spin_lock(&kvm_global_user_count_lock); 2020 BUG_ON(kvm_global_user_count == 0); 2021 if (--kvm_global_user_count == 0) 2022 pseries_enable_reloc_on_exc(); 2023 spin_unlock(&kvm_global_user_count_lock); 2024 } 2025} 2026 2027static int kvmppc_core_check_processor_compat_pr(void) 2028{ 2029 /* 2030 * PR KVM can work on POWER9 inside a guest partition 2031 * running in HPT mode. It can't work if we are using 2032 * radix translation (because radix provides no way for 2033 * a process to have unique translations in quadrant 3). 2034 */ 2035 if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled()) 2036 return -EIO; 2037 return 0; 2038} 2039 2040static int kvm_arch_vm_ioctl_pr(struct file *filp, 2041 unsigned int ioctl, unsigned long arg) 2042{ 2043 return -ENOTTY; 2044} 2045 2046static struct kvmppc_ops kvm_ops_pr = { 2047 .get_sregs = kvm_arch_vcpu_ioctl_get_sregs_pr, 2048 .set_sregs = kvm_arch_vcpu_ioctl_set_sregs_pr, 2049 .get_one_reg = kvmppc_get_one_reg_pr, 2050 .set_one_reg = kvmppc_set_one_reg_pr, 2051 .vcpu_load = kvmppc_core_vcpu_load_pr, 2052 .vcpu_put = kvmppc_core_vcpu_put_pr, 2053 .inject_interrupt = kvmppc_inject_interrupt_pr, 2054 .set_msr = kvmppc_set_msr_pr, 2055 .vcpu_run = kvmppc_vcpu_run_pr, 2056 .vcpu_create = kvmppc_core_vcpu_create_pr, 2057 .vcpu_free = kvmppc_core_vcpu_free_pr, 2058 .check_requests = kvmppc_core_check_requests_pr, 2059 .get_dirty_log = kvm_vm_ioctl_get_dirty_log_pr, 2060 .flush_memslot = kvmppc_core_flush_memslot_pr, 2061 .prepare_memory_region = kvmppc_core_prepare_memory_region_pr, 2062 .commit_memory_region = kvmppc_core_commit_memory_region_pr, 2063 .unmap_gfn_range = kvm_unmap_gfn_range_pr, 2064 .age_gfn = kvm_age_gfn_pr, 2065 .test_age_gfn = kvm_test_age_gfn_pr, 2066 .free_memslot = kvmppc_core_free_memslot_pr, 2067 .init_vm = kvmppc_core_init_vm_pr, 2068 .destroy_vm = kvmppc_core_destroy_vm_pr, 2069 .get_smmu_info = kvm_vm_ioctl_get_smmu_info_pr, 2070 .emulate_op = kvmppc_core_emulate_op_pr, 2071 .emulate_mtspr = kvmppc_core_emulate_mtspr_pr, 2072 .emulate_mfspr = kvmppc_core_emulate_mfspr_pr, 2073 .fast_vcpu_kick = kvm_vcpu_kick, 2074 .arch_vm_ioctl = kvm_arch_vm_ioctl_pr, 2075#ifdef CONFIG_PPC_BOOK3S_64 2076 .hcall_implemented = kvmppc_hcall_impl_pr, 2077 .configure_mmu = kvm_configure_mmu_pr, 2078#endif 2079 .giveup_ext = kvmppc_giveup_ext, 2080}; 2081 2082 2083int kvmppc_book3s_init_pr(void) 2084{ 2085 int r; 2086 2087 r = kvmppc_core_check_processor_compat_pr(); 2088 if (r < 0) 2089 return r; 2090 2091 kvm_ops_pr.owner = THIS_MODULE; 2092 kvmppc_pr_ops = &kvm_ops_pr; 2093 2094 r = kvmppc_mmu_hpte_sysinit(); 2095 return r; 2096} 2097 2098void kvmppc_book3s_exit_pr(void) 2099{ 2100 kvmppc_pr_ops = NULL; 2101 kvmppc_mmu_hpte_sysexit(); 2102} 2103 2104/* 2105 * We only support separate modules for book3s 64 2106 */ 2107#ifdef CONFIG_PPC_BOOK3S_64 2108 2109module_init(kvmppc_book3s_init_pr); 2110module_exit(kvmppc_book3s_exit_pr); 2111 2112MODULE_DESCRIPTION("KVM on Book3S without using hypervisor mode"); 2113MODULE_LICENSE("GPL"); 2114MODULE_ALIAS_MISCDEV(KVM_MINOR); 2115MODULE_ALIAS("devname:kvm"); 2116#endif
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