setup_64.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * 
  4 * Common boot and setup code.
  5 *
  6 * Copyright (C) 2001 PPC64 Team, IBM Corp
  7 */
  8
  9#include <linux/export.h>
 10#include <linux/string.h>
 11#include <linux/sched.h>
 12#include <linux/init.h>
 13#include <linux/kernel.h>
 14#include <linux/reboot.h>
 15#include <linux/delay.h>
 16#include <linux/initrd.h>
 17#include <linux/seq_file.h>
 18#include <linux/ioport.h>
 19#include <linux/console.h>
 20#include <linux/utsname.h>
 21#include <linux/tty.h>
 22#include <linux/root_dev.h>
 23#include <linux/notifier.h>
 24#include <linux/cpu.h>
 25#include <linux/unistd.h>
 26#include <linux/serial.h>
 27#include <linux/serial_8250.h>
 28#include <linux/memblock.h>
 29#include <linux/pci.h>
 30#include <linux/lockdep.h>
 31#include <linux/memory.h>
 32#include <linux/nmi.h>
 33#include <linux/pgtable.h>
 34#include <linux/of.h>
 35#include <linux/of_fdt.h>
 36
 37#include <asm/asm-prototypes.h>
 38#include <asm/kvm_guest.h>
 39#include <asm/io.h>
 40#include <asm/kdump.h>
 41#include <asm/processor.h>
 42#include <asm/smp.h>
 43#include <asm/elf.h>
 44#include <asm/machdep.h>
 45#include <asm/paca.h>
 46#include <asm/time.h>
 47#include <asm/cputable.h>
 48#include <asm/dt_cpu_ftrs.h>
 49#include <asm/sections.h>
 50#include <asm/btext.h>
 51#include <asm/nvram.h>
 52#include <asm/setup.h>
 53#include <asm/rtas.h>
 54#include <asm/iommu.h>
 55#include <asm/serial.h>
 56#include <asm/cache.h>
 57#include <asm/page.h>
 58#include <asm/mmu.h>
 59#include <asm/firmware.h>
 60#include <asm/xmon.h>
 61#include <asm/udbg.h>
 62#include <asm/kexec.h>
 63#include <asm/text-patching.h>
 64#include <asm/ftrace.h>
 65#include <asm/opal.h>
 66#include <asm/cputhreads.h>
 67#include <asm/hw_irq.h>
 68#include <asm/feature-fixups.h>
 69#include <asm/kup.h>
 70#include <asm/early_ioremap.h>
 71#include <asm/pgalloc.h>
 72
 73#include "setup.h"
 74
 75int spinning_secondaries;
 76u64 ppc64_pft_size;
 77
 78struct ppc64_caches ppc64_caches = {
 79	.l1d = {
 80		.block_size = 0x40,
 81		.log_block_size = 6,
 82	},
 83	.l1i = {
 84		.block_size = 0x40,
 85		.log_block_size = 6
 86	},
 87};
 88EXPORT_SYMBOL_GPL(ppc64_caches);
 89
 90#if defined(CONFIG_PPC_BOOK3E_64) && defined(CONFIG_SMP)
 91void __init setup_tlb_core_data(void)
 92{
 93	int cpu;
 94
 95	BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
 96
 97	for_each_possible_cpu(cpu) {
 98		int first = cpu_first_thread_sibling(cpu);
 99
100		/*
101		 * If we boot via kdump on a non-primary thread,
102		 * make sure we point at the thread that actually
103		 * set up this TLB.
104		 */
105		if (cpu_first_thread_sibling(boot_cpuid) == first)
106			first = boot_cpuid;
107
108		paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
109
110		/*
111		 * If we have threads, we need either tlbsrx.
112		 * or e6500 tablewalk mode, or else TLB handlers
113		 * will be racy and could produce duplicate entries.
114		 * Should we panic instead?
115		 */
116		WARN_ONCE(smt_enabled_at_boot >= 2 &&
117			  book3e_htw_mode != PPC_HTW_E6500,
118			  "%s: unsupported MMU configuration\n", __func__);
119	}
120}
121#endif
122
123#ifdef CONFIG_SMP
124
125static char *smt_enabled_cmdline;
126
127/* Look for ibm,smt-enabled OF option */
128void __init check_smt_enabled(void)
129{
130	struct device_node *dn;
131	const char *smt_option;
132
133	/* Default to enabling all threads */
134	smt_enabled_at_boot = threads_per_core;
135
136	/* Allow the command line to overrule the OF option */
137	if (smt_enabled_cmdline) {
138		if (!strcmp(smt_enabled_cmdline, "on"))
139			smt_enabled_at_boot = threads_per_core;
140		else if (!strcmp(smt_enabled_cmdline, "off"))
141			smt_enabled_at_boot = 0;
142		else {
143			int smt;
144			if (!kstrtoint(smt_enabled_cmdline, 10, &smt))
145				smt_enabled_at_boot =
146					min(threads_per_core, smt);
147		}
148	} else {
149		dn = of_find_node_by_path("/options");
150		if (dn) {
151			smt_option = of_get_property(dn, "ibm,smt-enabled",
152						     NULL);
153
154			if (smt_option) {
155				if (!strcmp(smt_option, "on"))
156					smt_enabled_at_boot = threads_per_core;
157				else if (!strcmp(smt_option, "off"))
158					smt_enabled_at_boot = 0;
159			}
160
161			of_node_put(dn);
162		}
163	}
164}
165
166/* Look for smt-enabled= cmdline option */
167static int __init early_smt_enabled(char *p)
168{
169	smt_enabled_cmdline = p;
170	return 0;
171}
172early_param("smt-enabled", early_smt_enabled);
173
174#endif /* CONFIG_SMP */
175
176/** Fix up paca fields required for the boot cpu */
177static void __init fixup_boot_paca(struct paca_struct *boot_paca)
178{
179	/* The boot cpu is started */
180	boot_paca->cpu_start = 1;
181#ifdef CONFIG_PPC_BOOK3S_64
182	/*
183	 * Give the early boot machine check stack somewhere to use, use
184	 * half of the init stack. This is a bit hacky but there should not be
185	 * deep stack usage in early init so shouldn't overflow it or overwrite
186	 * things.
187	 */
188	boot_paca->mc_emergency_sp = (void *)&init_thread_union +
189		(THREAD_SIZE/2);
190#endif
191	/* Allow percpu accesses to work until we setup percpu data */
192	boot_paca->data_offset = 0;
193	/* Mark interrupts soft and hard disabled in PACA */
194	boot_paca->irq_soft_mask = IRQS_DISABLED;
195	boot_paca->irq_happened = PACA_IRQ_HARD_DIS;
196	WARN_ON(mfmsr() & MSR_EE);
197}
198
199static void __init configure_exceptions(void)
200{
201	/*
202	 * Setup the trampolines from the lowmem exception vectors
203	 * to the kdump kernel when not using a relocatable kernel.
204	 */
205	setup_kdump_trampoline();
206
207	/* Under a PAPR hypervisor, we need hypercalls */
208	if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
209		/*
210		 * - PR KVM does not support AIL mode interrupts in the host
211		 *   while a PR guest is running.
212		 *
213		 * - SCV system call interrupt vectors are only implemented for
214		 *   AIL mode interrupts.
215		 *
216		 * - On pseries, AIL mode can only be enabled and disabled
217		 *   system-wide so when a PR VM is created on a pseries host,
218		 *   all CPUs of the host are set to AIL=0 mode.
219		 *
220		 * - Therefore host CPUs must not execute scv while a PR VM
221		 *   exists.
222		 *
223		 * - SCV support can not be disabled dynamically because the
224		 *   feature is advertised to host userspace. Disabling the
225		 *   facility and emulating it would be possible but is not
226		 *   implemented.
227		 *
228		 * - So SCV support is blanket disabled if PR KVM could possibly
229		 *   run. That is, PR support compiled in, booting on pseries
230		 *   with hash MMU.
231		 */
232		if (IS_ENABLED(CONFIG_KVM_BOOK3S_PR_POSSIBLE) && !radix_enabled()) {
233			init_task.thread.fscr &= ~FSCR_SCV;
234			cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
235		}
236
237		/* Enable AIL if possible */
238		if (!pseries_enable_reloc_on_exc()) {
239			init_task.thread.fscr &= ~FSCR_SCV;
240			cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
241		}
242
243		/*
244		 * Tell the hypervisor that we want our exceptions to
245		 * be taken in little endian mode.
246		 *
247		 * We don't call this for big endian as our calling convention
248		 * makes us always enter in BE, and the call may fail under
249		 * some circumstances with kdump.
250		 */
251#ifdef __LITTLE_ENDIAN__
252		pseries_little_endian_exceptions();
253#endif
254	} else {
255		/* Set endian mode using OPAL */
256		if (firmware_has_feature(FW_FEATURE_OPAL))
257			opal_configure_cores();
258
259		/* AIL on native is done in cpu_ready_for_interrupts() */
260	}
261}
262
263static void cpu_ready_for_interrupts(void)
264{
265	/*
266	 * Enable AIL if supported, and we are in hypervisor mode. This
267	 * is called once for every processor.
268	 *
269	 * If we are not in hypervisor mode the job is done once for
270	 * the whole partition in configure_exceptions().
271	 */
272	if (cpu_has_feature(CPU_FTR_HVMODE)) {
273		unsigned long lpcr = mfspr(SPRN_LPCR);
274		unsigned long new_lpcr = lpcr;
275
276		if (cpu_has_feature(CPU_FTR_ARCH_31)) {
277			/* P10 DD1 does not have HAIL */
278			if (pvr_version_is(PVR_POWER10) &&
279					(mfspr(SPRN_PVR) & 0xf00) == 0x100)
280				new_lpcr |= LPCR_AIL_3;
281			else
282				new_lpcr |= LPCR_HAIL;
283		} else if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
284			new_lpcr |= LPCR_AIL_3;
285		}
286
287		if (new_lpcr != lpcr)
288			mtspr(SPRN_LPCR, new_lpcr);
289	}
290
291	/*
292	 * Set HFSCR:TM based on CPU features:
293	 * In the special case of TM no suspend (P9N DD2.1), Linux is
294	 * told TM is off via the dt-ftrs but told to (partially) use
295	 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
296	 * will be off from dt-ftrs but we need to turn it on for the
297	 * no suspend case.
298	 */
299	if (cpu_has_feature(CPU_FTR_HVMODE)) {
300		if (cpu_has_feature(CPU_FTR_TM_COMP))
301			mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
302		else
303			mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
304	}
305
306	/* Set IR and DR in PACA MSR */
307	get_paca()->kernel_msr = MSR_KERNEL;
308}
309
310unsigned long spr_default_dscr = 0;
311
312static void __init record_spr_defaults(void)
313{
314	if (early_cpu_has_feature(CPU_FTR_DSCR))
315		spr_default_dscr = mfspr(SPRN_DSCR);
316}
317
318/*
319 * Early initialization entry point. This is called by head.S
320 * with MMU translation disabled. We rely on the "feature" of
321 * the CPU that ignores the top 2 bits of the address in real
322 * mode so we can access kernel globals normally provided we
323 * only toy with things in the RMO region. From here, we do
324 * some early parsing of the device-tree to setup out MEMBLOCK
325 * data structures, and allocate & initialize the hash table
326 * and segment tables so we can start running with translation
327 * enabled.
328 *
329 * It is this function which will call the probe() callback of
330 * the various platform types and copy the matching one to the
331 * global ppc_md structure. Your platform can eventually do
332 * some very early initializations from the probe() routine, but
333 * this is not recommended, be very careful as, for example, the
334 * device-tree is not accessible via normal means at this point.
335 */
336
337void __init early_setup(unsigned long dt_ptr)
338{
339	static __initdata struct paca_struct boot_paca;
340
341	/* -------- printk is _NOT_ safe to use here ! ------- */
342
343	/*
344	 * Assume we're on cpu 0 for now.
345	 *
346	 * We need to load a PACA very early for a few reasons.
347	 *
348	 * The stack protector canary is stored in the paca, so as soon as we
349	 * call any stack protected code we need r13 pointing somewhere valid.
350	 *
351	 * If we are using kcov it will call in_task() in its instrumentation,
352	 * which relies on the current task from the PACA.
353	 *
354	 * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as
355	 * printk(), which can trigger both stack protector and kcov.
356	 *
357	 * percpu variables and spin locks also use the paca.
358	 *
359	 * So set up a temporary paca. It will be replaced below once we know
360	 * what CPU we are on.
361	 */
362	initialise_paca(&boot_paca, 0);
363	fixup_boot_paca(&boot_paca);
364	WARN_ON(local_paca);
365	setup_paca(&boot_paca); /* install the paca into registers */
366
367	/* -------- printk is now safe to use ------- */
368
369	if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && (mfmsr() & MSR_HV))
370		enable_machine_check();
371
372	/* Try new device tree based feature discovery ... */
373	if (!dt_cpu_ftrs_init(__va(dt_ptr)))
374		/* Otherwise use the old style CPU table */
375		identify_cpu(0, mfspr(SPRN_PVR));
376
377	/* Enable early debugging if any specified (see udbg.h) */
378	udbg_early_init();
379
380	udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
381
382	/*
383	 * Do early initialization using the flattened device
384	 * tree, such as retrieving the physical memory map or
385	 * calculating/retrieving the hash table size, discover
386	 * boot_cpuid and boot_cpu_hwid.
387	 */
388	early_init_devtree(__va(dt_ptr));
389
390	allocate_paca_ptrs();
391	allocate_paca(boot_cpuid);
392	set_hard_smp_processor_id(boot_cpuid, boot_cpu_hwid);
393	fixup_boot_paca(paca_ptrs[boot_cpuid]);
394	setup_paca(paca_ptrs[boot_cpuid]); /* install the paca into registers */
395	// smp_processor_id() now reports boot_cpuid
396
397#ifdef CONFIG_SMP
398	task_thread_info(current)->cpu = boot_cpuid; // fix task_cpu(current)
399#endif
400
401	/*
402	 * Configure exception handlers. This include setting up trampolines
403	 * if needed, setting exception endian mode, etc...
404	 */
405	configure_exceptions();
406
407	/*
408	 * Configure Kernel Userspace Protection. This needs to happen before
409	 * feature fixups for platforms that implement this using features.
410	 */
411	setup_kup();
412
413	/* Apply all the dynamic patching */
414	apply_feature_fixups();
415	setup_feature_keys();
416
417	/* Initialize the hash table or TLB handling */
418	early_init_mmu();
419
420	early_ioremap_setup();
421
422	/*
423	 * After firmware and early platform setup code has set things up,
424	 * we note the SPR values for configurable control/performance
425	 * registers, and use those as initial defaults.
426	 */
427	record_spr_defaults();
428
429	/*
430	 * At this point, we can let interrupts switch to virtual mode
431	 * (the MMU has been setup), so adjust the MSR in the PACA to
432	 * have IR and DR set and enable AIL if it exists
433	 */
434	cpu_ready_for_interrupts();
435
436	/*
437	 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
438	 * will only actually get enabled on the boot cpu much later once
439	 * ftrace itself has been initialized.
440	 */
441	this_cpu_enable_ftrace();
442
443	udbg_printf(" <- %s()\n", __func__);
444
445#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
446	/*
447	 * This needs to be done *last* (after the above udbg_printf() even)
448	 *
449	 * Right after we return from this function, we turn on the MMU
450	 * which means the real-mode access trick that btext does will
451	 * no longer work, it needs to switch to using a real MMU
452	 * mapping. This call will ensure that it does
453	 */
454	btext_map();
455#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
456}
457
458#ifdef CONFIG_SMP
459void early_setup_secondary(void)
460{
461	/* Mark interrupts disabled in PACA */
462	irq_soft_mask_set(IRQS_DISABLED);
463
464	/* Initialize the hash table or TLB handling */
465	early_init_mmu_secondary();
466
467	/* Perform any KUP setup that is per-cpu */
468	setup_kup();
469
470	/*
471	 * At this point, we can let interrupts switch to virtual mode
472	 * (the MMU has been setup), so adjust the MSR in the PACA to
473	 * have IR and DR set.
474	 */
475	cpu_ready_for_interrupts();
476}
477
478#endif /* CONFIG_SMP */
479
480void __noreturn panic_smp_self_stop(void)
481{
482	hard_irq_disable();
483	spin_begin();
484	while (1)
485		spin_cpu_relax();
486}
487
488#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
489static bool use_spinloop(void)
490{
491	if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
492		/*
493		 * See comments in head_64.S -- not all platforms insert
494		 * secondaries at __secondary_hold and wait at the spin
495		 * loop.
496		 */
497		if (firmware_has_feature(FW_FEATURE_OPAL))
498			return false;
499		return true;
500	}
501
502	/*
503	 * When book3e boots from kexec, the ePAPR spin table does
504	 * not get used.
505	 */
506	return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
507}
508
509void smp_release_cpus(void)
510{
511	unsigned long *ptr;
512	int i;
513
514	if (!use_spinloop())
515		return;
516
517	/* All secondary cpus are spinning on a common spinloop, release them
518	 * all now so they can start to spin on their individual paca
519	 * spinloops. For non SMP kernels, the secondary cpus never get out
520	 * of the common spinloop.
521	 */
522
523	ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
524			- PHYSICAL_START);
525	*ptr = ppc_function_entry(generic_secondary_smp_init);
526
527	/* And wait a bit for them to catch up */
528	for (i = 0; i < 100000; i++) {
529		mb();
530		HMT_low();
531		if (spinning_secondaries == 0)
532			break;
533		udelay(1);
534	}
535	pr_debug("spinning_secondaries = %d\n", spinning_secondaries);
536}
537#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
538
539/*
540 * Initialize some remaining members of the ppc64_caches and systemcfg
541 * structures
542 * (at least until we get rid of them completely). This is mostly some
543 * cache informations about the CPU that will be used by cache flush
544 * routines and/or provided to userland
545 */
546
547static void __init init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
548			    u32 bsize, u32 sets)
549{
550	info->size = size;
551	info->sets = sets;
552	info->line_size = lsize;
553	info->block_size = bsize;
554	info->log_block_size = __ilog2(bsize);
555	if (bsize)
556		info->blocks_per_page = PAGE_SIZE / bsize;
557	else
558		info->blocks_per_page = 0;
559
560	if (sets == 0)
561		info->assoc = 0xffff;
562	else
563		info->assoc = size / (sets * lsize);
564}
565
566static bool __init parse_cache_info(struct device_node *np,
567				    bool icache,
568				    struct ppc_cache_info *info)
569{
570	static const char *ipropnames[] __initdata = {
571		"i-cache-size",
572		"i-cache-sets",
573		"i-cache-block-size",
574		"i-cache-line-size",
575	};
576	static const char *dpropnames[] __initdata = {
577		"d-cache-size",
578		"d-cache-sets",
579		"d-cache-block-size",
580		"d-cache-line-size",
581	};
582	const char **propnames = icache ? ipropnames : dpropnames;
583	const __be32 *sizep, *lsizep, *bsizep, *setsp;
584	u32 size, lsize, bsize, sets;
585	bool success = true;
586
587	size = 0;
588	sets = -1u;
589	lsize = bsize = cur_cpu_spec->dcache_bsize;
590	sizep = of_get_property(np, propnames[0], NULL);
591	if (sizep != NULL)
592		size = be32_to_cpu(*sizep);
593	setsp = of_get_property(np, propnames[1], NULL);
594	if (setsp != NULL)
595		sets = be32_to_cpu(*setsp);
596	bsizep = of_get_property(np, propnames[2], NULL);
597	lsizep = of_get_property(np, propnames[3], NULL);
598	if (bsizep == NULL)
599		bsizep = lsizep;
600	if (lsizep == NULL)
601		lsizep = bsizep;
602	if (lsizep != NULL)
603		lsize = be32_to_cpu(*lsizep);
604	if (bsizep != NULL)
605		bsize = be32_to_cpu(*bsizep);
606	if (sizep == NULL || bsizep == NULL || lsizep == NULL)
607		success = false;
608
609	/*
610	 * OF is weird .. it represents fully associative caches
611	 * as "1 way" which doesn't make much sense and doesn't
612	 * leave room for direct mapped. We'll assume that 0
613	 * in OF means direct mapped for that reason.
614	 */
615	if (sets == 1)
616		sets = 0;
617	else if (sets == 0)
618		sets = 1;
619
620	init_cache_info(info, size, lsize, bsize, sets);
621
622	return success;
623}
624
625void __init initialize_cache_info(void)
626{
627	struct device_node *cpu = NULL, *l2, *l3 = NULL;
628	u32 pvr;
629
630	/*
631	 * All shipping POWER8 machines have a firmware bug that
632	 * puts incorrect information in the device-tree. This will
633	 * be (hopefully) fixed for future chips but for now hard
634	 * code the values if we are running on one of these
635	 */
636	pvr = PVR_VER(mfspr(SPRN_PVR));
637	if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
638	    pvr == PVR_POWER8NVL) {
639						/* size    lsize   blk  sets */
640		init_cache_info(&ppc64_caches.l1i, 0x8000,   128,  128, 32);
641		init_cache_info(&ppc64_caches.l1d, 0x10000,  128,  128, 64);
642		init_cache_info(&ppc64_caches.l2,  0x80000,  128,  0,   512);
643		init_cache_info(&ppc64_caches.l3,  0x800000, 128,  0,   8192);
644	} else
645		cpu = of_find_node_by_type(NULL, "cpu");
646
647	/*
648	 * We're assuming *all* of the CPUs have the same
649	 * d-cache and i-cache sizes... -Peter
650	 */
651	if (cpu) {
652		if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
653			pr_warn("Argh, can't find dcache properties !\n");
654
655		if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
656			pr_warn("Argh, can't find icache properties !\n");
657
658		/*
659		 * Try to find the L2 and L3 if any. Assume they are
660		 * unified and use the D-side properties.
661		 */
662		l2 = of_find_next_cache_node(cpu);
663		of_node_put(cpu);
664		if (l2) {
665			parse_cache_info(l2, false, &ppc64_caches.l2);
666			l3 = of_find_next_cache_node(l2);
667			of_node_put(l2);
668		}
669		if (l3) {
670			parse_cache_info(l3, false, &ppc64_caches.l3);
671			of_node_put(l3);
672		}
673	}
674
675	/* For use by binfmt_elf */
676	dcache_bsize = ppc64_caches.l1d.block_size;
677	icache_bsize = ppc64_caches.l1i.block_size;
678
679	cur_cpu_spec->dcache_bsize = dcache_bsize;
680	cur_cpu_spec->icache_bsize = icache_bsize;
681}
682
683/*
684 * This returns the limit below which memory accesses to the linear
685 * mapping are guarnateed not to cause an architectural exception (e.g.,
686 * TLB or SLB miss fault).
687 *
688 * This is used to allocate PACAs and various interrupt stacks that
689 * that are accessed early in interrupt handlers that must not cause
690 * re-entrant interrupts.
691 */
692__init u64 ppc64_bolted_size(void)
693{
694#ifdef CONFIG_PPC_BOOK3E_64
695	/* Freescale BookE bolts the entire linear mapping */
696	return linear_map_top;
697#else
698	/* BookS radix, does not take faults on linear mapping */
699	if (early_radix_enabled())
700		return ULONG_MAX;
701
702	/* BookS hash, the first segment is bolted */
703	if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
704		return 1UL << SID_SHIFT_1T;
705	return 1UL << SID_SHIFT;
706#endif
707}
708
709static void *__init alloc_stack(unsigned long limit, int cpu)
710{
711	void *ptr;
712
713	BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
714
715	ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN,
716				     MEMBLOCK_LOW_LIMIT, limit,
717				     early_cpu_to_node(cpu));
718	if (!ptr)
719		panic("cannot allocate stacks");
720
721	return ptr;
722}
723
724void __init irqstack_early_init(void)
725{
726	u64 limit = ppc64_bolted_size();
727	unsigned int i;
728
729	/*
730	 * Interrupt stacks must be in the first segment since we
731	 * cannot afford to take SLB misses on them. They are not
732	 * accessed in realmode.
733	 */
734	for_each_possible_cpu(i) {
735		softirq_ctx[i] = alloc_stack(limit, i);
736		hardirq_ctx[i] = alloc_stack(limit, i);
737	}
738}
739
740#ifdef CONFIG_PPC_BOOK3E_64
741void __init exc_lvl_early_init(void)
742{
743	unsigned int i;
744
745	for_each_possible_cpu(i) {
746		void *sp;
747
748		sp = alloc_stack(ULONG_MAX, i);
749		critirq_ctx[i] = sp;
750		paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
751
752		sp = alloc_stack(ULONG_MAX, i);
753		dbgirq_ctx[i] = sp;
754		paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
755
756		sp = alloc_stack(ULONG_MAX, i);
757		mcheckirq_ctx[i] = sp;
758		paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
759	}
760
761	if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
762		patch_exception(0x040, exc_debug_debug_book3e);
763}
764#endif
765
766/*
767 * Stack space used when we detect a bad kernel stack pointer, and
768 * early in SMP boots before relocation is enabled. Exclusive emergency
769 * stack for machine checks.
770 */
771void __init emergency_stack_init(void)
772{
773	u64 limit, mce_limit;
774	unsigned int i;
775
776	/*
777	 * Emergency stacks must be under 256MB, we cannot afford to take
778	 * SLB misses on them. The ABI also requires them to be 128-byte
779	 * aligned.
780	 *
781	 * Since we use these as temporary stacks during secondary CPU
782	 * bringup, machine check, system reset, and HMI, we need to get
783	 * at them in real mode. This means they must also be within the RMO
784	 * region.
785	 *
786	 * The IRQ stacks allocated elsewhere in this file are zeroed and
787	 * initialized in kernel/irq.c. These are initialized here in order
788	 * to have emergency stacks available as early as possible.
789	 */
790	limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size);
791
792	/*
793	 * Machine check on pseries calls rtas, but can't use the static
794	 * rtas_args due to a machine check hitting while the lock is held.
795	 * rtas args have to be under 4GB, so the machine check stack is
796	 * limited to 4GB so args can be put on stack.
797	 */
798	if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G)
799		mce_limit = SZ_4G;
800
801	for_each_possible_cpu(i) {
802		paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
803
804#ifdef CONFIG_PPC_BOOK3S_64
805		/* emergency stack for NMI exception handling. */
806		paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
807
808		/* emergency stack for machine check exception handling. */
809		paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE;
810#endif
811	}
812}
813
814#ifdef CONFIG_SMP
815static int pcpu_cpu_distance(unsigned int from, unsigned int to)
816{
817	if (early_cpu_to_node(from) == early_cpu_to_node(to))
818		return LOCAL_DISTANCE;
819	else
820		return REMOTE_DISTANCE;
821}
822
823static __init int pcpu_cpu_to_node(int cpu)
824{
825	return early_cpu_to_node(cpu);
826}
827
828unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
829EXPORT_SYMBOL(__per_cpu_offset);
830DEFINE_STATIC_KEY_FALSE(__percpu_first_chunk_is_paged);
831
832void __init setup_per_cpu_areas(void)
833{
834	const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
835	size_t atom_size;
836	unsigned long delta;
837	unsigned int cpu;
838	int rc = -EINVAL;
839
840	/*
841	 * BookE and BookS radix are historical values and should be revisited.
842	 */
843	if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) {
844		atom_size = SZ_1M;
845	} else if (radix_enabled()) {
846		atom_size = PAGE_SIZE;
847	} else if (IS_ENABLED(CONFIG_PPC_64S_HASH_MMU)) {
848		/*
849		 * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
850		 * to group units.  For larger mappings, use 1M atom which
851		 * should be large enough to contain a number of units.
852		 */
853		if (mmu_linear_psize == MMU_PAGE_4K)
854			atom_size = PAGE_SIZE;
855		else
856			atom_size = SZ_1M;
857	}
858
859	if (pcpu_chosen_fc != PCPU_FC_PAGE) {
860		rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
861					    pcpu_cpu_to_node);
862		if (rc)
863			pr_warn("PERCPU: %s allocator failed (%d), "
864				"falling back to page size\n",
865				pcpu_fc_names[pcpu_chosen_fc], rc);
866	}
867
868	if (rc < 0)
869		rc = pcpu_page_first_chunk(0, pcpu_cpu_to_node);
870	if (rc < 0)
871		panic("cannot initialize percpu area (err=%d)", rc);
872
873	static_key_enable(&__percpu_first_chunk_is_paged.key);
874	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
875	for_each_possible_cpu(cpu) {
876                __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
877		paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
878	}
879}
880#endif
881
882#ifdef CONFIG_MEMORY_HOTPLUG
883unsigned long memory_block_size_bytes(void)
884{
885	if (ppc_md.memory_block_size)
886		return ppc_md.memory_block_size();
887
888	return MIN_MEMORY_BLOCK_SIZE;
889}
890#endif
891
892#ifdef CONFIG_PPC_INDIRECT_PIO
893struct ppc_pci_io ppc_pci_io;
894EXPORT_SYMBOL(ppc_pci_io);
895#endif
896
897#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
898u64 hw_nmi_get_sample_period(int watchdog_thresh)
899{
900	return ppc_proc_freq * watchdog_thresh;
901}
902#endif
903
904/*
905 * The perf based hardlockup detector breaks PMU event based branches, so
906 * disable it by default. Book3S has a soft-nmi hardlockup detector based
907 * on the decrementer interrupt, so it does not suffer from this problem.
908 *
909 * It is likely to get false positives in KVM guests, so disable it there
910 * by default too. PowerVM will not stop or arbitrarily oversubscribe
911 * CPUs, but give a minimum regular allotment even with SPLPAR, so enable
912 * the detector for non-KVM guests, assume PowerVM.
913 */
914static int __init disable_hardlockup_detector(void)
915{
916#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
917	hardlockup_detector_disable();
918#else
919	if (firmware_has_feature(FW_FEATURE_LPAR)) {
920		check_kvm_guest();
921		if (is_kvm_guest())
922			hardlockup_detector_disable();
923	}
924#endif
925
926	return 0;
927}
928early_initcall(disable_hardlockup_detector);