reg.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Contains the definition of registers common to all PowerPC variants.
   4 * If a register definition has been changed in a different PowerPC
   5 * variant, we will case it in #ifndef XXX ... #endif, and have the
   6 * number used in the Programming Environments Manual For 32-Bit
   7 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
   8 */
   9
  10#ifndef _ASM_POWERPC_REG_H
  11#define _ASM_POWERPC_REG_H
  12#ifdef __KERNEL__
  13
  14#include <linux/stringify.h>
  15#include <linux/const.h>
  16#include <asm/cputable.h>
  17#include <asm/asm-const.h>
  18#include <asm/feature-fixups.h>
  19
  20/* Pickup Book E specific registers. */
  21#ifdef CONFIG_BOOKE
  22#include <asm/reg_booke.h>
  23#endif
  24
  25#ifdef CONFIG_FSL_EMB_PERFMON
  26#include <asm/reg_fsl_emb.h>
  27#endif
  28
  29#include <asm/reg_8xx.h>
  30
  31#define MSR_SF_LG	63              /* Enable 64 bit mode */
  32#define MSR_HV_LG 	60              /* Hypervisor state */
  33#define MSR_TS_T_LG	34		/* Trans Mem state: Transactional */
  34#define MSR_TS_S_LG	33		/* Trans Mem state: Suspended */
  35#define MSR_TS_LG	33		/* Trans Mem state (2 bits) */
  36#define MSR_TM_LG	32		/* Trans Mem Available */
  37#define MSR_VEC_LG	25	        /* Enable AltiVec */
  38#define MSR_VSX_LG	23		/* Enable VSX */
  39#define MSR_S_LG	22		/* Secure state */
  40#define MSR_POW_LG	18		/* Enable Power Management */
  41#define MSR_WE_LG	18		/* Wait State Enable */
  42#define MSR_TGPR_LG	17		/* TLB Update registers in use */
  43#define MSR_CE_LG	17		/* Critical Interrupt Enable */
  44#define MSR_ILE_LG	16		/* Interrupt Little Endian */
  45#define MSR_EE_LG	15		/* External Interrupt Enable */
  46#define MSR_PR_LG	14		/* Problem State / Privilege Level */
  47#define MSR_FP_LG	13		/* Floating Point enable */
  48#define MSR_ME_LG	12		/* Machine Check Enable */
  49#define MSR_FE0_LG	11		/* Floating Exception mode 0 */
  50#define MSR_SE_LG	10		/* Single Step */
  51#define MSR_BE_LG	9		/* Branch Trace */
  52#define MSR_DE_LG	9 		/* Debug Exception Enable */
  53#define MSR_FE1_LG	8		/* Floating Exception mode 1 */
  54#define MSR_IP_LG	6		/* Exception prefix 0x000/0xFFF */
  55#define MSR_IR_LG	5 		/* Instruction Relocate */
  56#define MSR_DR_LG	4 		/* Data Relocate */
  57#define MSR_PE_LG	3		/* Protection Enable */
  58#define MSR_PX_LG	2		/* Protection Exclusive Mode */
  59#define MSR_PMM_LG	2		/* Performance monitor */
  60#define MSR_RI_LG	1		/* Recoverable Exception */
  61#define MSR_LE_LG	0 		/* Little Endian */
  62
  63#ifdef __ASSEMBLER__
  64#define __MASK(X)	(1<<(X))
  65#else
  66#define __MASK(X)	(1UL<<(X))
  67#endif
  68
  69#ifdef CONFIG_PPC64
  70#define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
  71#define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
  72#define MSR_S		__MASK(MSR_S_LG)	/* Secure state */
  73#else
  74/* so tests for these bits fail on 32-bit */
  75#define MSR_SF		0
  76#define MSR_HV		0
  77#define MSR_S		0
  78#endif
  79
  80/*
  81 * To be used in shared book E/book S, this avoids needing to worry about
  82 * book S/book E in shared code
  83 */
  84#ifndef MSR_SPE
  85#define MSR_SPE 	0
  86#endif
  87
  88#define MSR_VEC		__MASK(MSR_VEC_LG)	/* Enable AltiVec */
  89#define MSR_VSX		__MASK(MSR_VSX_LG)	/* Enable VSX */
  90#define MSR_POW		__MASK(MSR_POW_LG)	/* Enable Power Management */
  91#define MSR_WE		__MASK(MSR_WE_LG)	/* Wait State Enable */
  92#define MSR_TGPR	__MASK(MSR_TGPR_LG)	/* TLB Update registers in use */
  93#define MSR_CE		__MASK(MSR_CE_LG)	/* Critical Interrupt Enable */
  94#define MSR_ILE		__MASK(MSR_ILE_LG)	/* Interrupt Little Endian */
  95#define MSR_EE		__MASK(MSR_EE_LG)	/* External Interrupt Enable */
  96#define MSR_PR		__MASK(MSR_PR_LG)	/* Problem State / Privilege Level */
  97#define MSR_FP		__MASK(MSR_FP_LG)	/* Floating Point enable */
  98#define MSR_ME		__MASK(MSR_ME_LG)	/* Machine Check Enable */
  99#define MSR_FE0		__MASK(MSR_FE0_LG)	/* Floating Exception mode 0 */
 100#define MSR_SE		__MASK(MSR_SE_LG)	/* Single Step */
 101#define MSR_BE		__MASK(MSR_BE_LG)	/* Branch Trace */
 102#define MSR_DE		__MASK(MSR_DE_LG)	/* Debug Exception Enable */
 103#define MSR_FE1		__MASK(MSR_FE1_LG)	/* Floating Exception mode 1 */
 104#define MSR_IP		__MASK(MSR_IP_LG)	/* Exception prefix 0x000/0xFFF */
 105#define MSR_IR		__MASK(MSR_IR_LG)	/* Instruction Relocate */
 106#define MSR_DR		__MASK(MSR_DR_LG)	/* Data Relocate */
 107#define MSR_PE		__MASK(MSR_PE_LG)	/* Protection Enable */
 108#define MSR_PX		__MASK(MSR_PX_LG)	/* Protection Exclusive Mode */
 109#ifndef MSR_PMM
 110#define MSR_PMM		__MASK(MSR_PMM_LG)	/* Performance monitor */
 111#endif
 112#define MSR_RI		__MASK(MSR_RI_LG)	/* Recoverable Exception */
 113#define MSR_LE		__MASK(MSR_LE_LG)	/* Little Endian */
 114
 115#define MSR_TM		__MASK(MSR_TM_LG)	/* Transactional Mem Available */
 116#define MSR_TS_N	0			/*  Non-transactional */
 117#define MSR_TS_S	__MASK(MSR_TS_S_LG)	/*  Transaction Suspended */
 118#define MSR_TS_T	__MASK(MSR_TS_T_LG)	/*  Transaction Transactional */
 119#define MSR_TS_MASK	(MSR_TS_T | MSR_TS_S)   /* Transaction State bits */
 120#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
 121#define MSR_TM_TRANSACTIONAL(x)	(((x) & MSR_TS_MASK) == MSR_TS_T)
 122#define MSR_TM_SUSPENDED(x)	(((x) & MSR_TS_MASK) == MSR_TS_S)
 123
 124#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 125#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
 126#else
 127#define MSR_TM_ACTIVE(x) ((void)(x), 0)
 128#endif
 129
 130#if defined(CONFIG_PPC_BOOK3S_64)
 131#define MSR_64BIT	MSR_SF
 132
 133/* Server variant */
 134#define __MSR		(MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV)
 135#ifdef __BIG_ENDIAN__
 136#define MSR_		__MSR
 137#define MSR_IDLE	(MSR_ME | MSR_SF | MSR_HV)
 138#else
 139#define MSR_		(__MSR | MSR_LE)
 140#define MSR_IDLE	(MSR_ME | MSR_SF | MSR_HV | MSR_LE)
 141#endif
 142#define MSR_KERNEL	(MSR_ | MSR_64BIT)
 143#define MSR_USER32	(MSR_ | MSR_PR | MSR_EE)
 144#define MSR_USER64	(MSR_USER32 | MSR_64BIT)
 145#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
 146/* Default MSR for kernel mode. */
 147#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR)
 148#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
 149#endif
 150
 151#ifndef MSR_64BIT
 152#define MSR_64BIT	0
 153#endif
 154
 155/* Condition Register related */
 156#define CR0_SHIFT	28
 157#define CR0_MASK	0xF
 158#define CR0_TBEGIN_FAILURE	(0x2 << 28) /* 0b0010 */
 159
 160
 161/* Power Management - Processor Stop Status and Control Register Fields */
 162#define PSSCR_RL_MASK		0x0000000F /* Requested Level */
 163#define PSSCR_MTL_MASK		0x000000F0 /* Maximum Transition Level */
 164#define PSSCR_TR_MASK		0x00000300 /* Transition State */
 165#define PSSCR_PSLL_MASK		0x000F0000 /* Power-Saving Level Limit */
 166#define PSSCR_EC		0x00100000 /* Exit Criterion */
 167#define PSSCR_ESL		0x00200000 /* Enable State Loss */
 168#define PSSCR_SD		0x00400000 /* Status Disable */
 169#define PSSCR_PLS	0xf000000000000000 /* Power-saving Level Status */
 170#define PSSCR_PLS_SHIFT	60
 171#define PSSCR_GUEST_VIS	0xf0000000000003ffUL /* Guest-visible PSSCR fields */
 172#define PSSCR_FAKE_SUSPEND	0x00000400 /* Fake-suspend bit (P9 DD2.2) */
 173#define PSSCR_FAKE_SUSPEND_LG	10	   /* Fake-suspend bit position */
 174
 175/* Floating Point Status and Control Register (FPSCR) Fields */
 176#define FPSCR_FX	0x80000000	/* FPU exception summary */
 177#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
 178#define FPSCR_VX	0x20000000	/* Invalid operation summary */
 179#define FPSCR_OX	0x10000000	/* Overflow exception summary */
 180#define FPSCR_UX	0x08000000	/* Underflow exception summary */
 181#define FPSCR_ZX	0x04000000	/* Zero-divide exception summary */
 182#define FPSCR_XX	0x02000000	/* Inexact exception summary */
 183#define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
 184#define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
 185#define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
 186#define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
 187#define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
 188#define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
 189#define FPSCR_FR	0x00040000	/* Fraction rounded */
 190#define FPSCR_FI	0x00020000	/* Fraction inexact */
 191#define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
 192#define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
 193#define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
 194#define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
 195#define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
 196#define FPSCR_VE	0x00000080	/* Invalid op exception enable */
 197#define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
 198#define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
 199#define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
 200#define FPSCR_XE	0x00000008	/* FP inexact exception enable */
 201#define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
 202#define FPSCR_RN	0x00000003	/* FPU rounding control */
 203
 204/* Bit definitions for SPEFSCR. */
 205#define SPEFSCR_SOVH	0x80000000	/* Summary integer overflow high */
 206#define SPEFSCR_OVH	0x40000000	/* Integer overflow high */
 207#define SPEFSCR_FGH	0x20000000	/* Embedded FP guard bit high */
 208#define SPEFSCR_FXH	0x10000000	/* Embedded FP sticky bit high */
 209#define SPEFSCR_FINVH	0x08000000	/* Embedded FP invalid operation high */
 210#define SPEFSCR_FDBZH	0x04000000	/* Embedded FP div by zero high */
 211#define SPEFSCR_FUNFH	0x02000000	/* Embedded FP underflow high */
 212#define SPEFSCR_FOVFH	0x01000000	/* Embedded FP overflow high */
 213#define SPEFSCR_FINXS	0x00200000	/* Embedded FP inexact sticky */
 214#define SPEFSCR_FINVS	0x00100000	/* Embedded FP invalid op. sticky */
 215#define SPEFSCR_FDBZS	0x00080000	/* Embedded FP div by zero sticky */
 216#define SPEFSCR_FUNFS	0x00040000	/* Embedded FP underflow sticky */
 217#define SPEFSCR_FOVFS	0x00020000	/* Embedded FP overflow sticky */
 218#define SPEFSCR_MODE	0x00010000	/* Embedded FP mode */
 219#define SPEFSCR_SOV	0x00008000	/* Integer summary overflow */
 220#define SPEFSCR_OV	0x00004000	/* Integer overflow */
 221#define SPEFSCR_FG	0x00002000	/* Embedded FP guard bit */
 222#define SPEFSCR_FX	0x00001000	/* Embedded FP sticky bit */
 223#define SPEFSCR_FINV	0x00000800	/* Embedded FP invalid operation */
 224#define SPEFSCR_FDBZ	0x00000400	/* Embedded FP div by zero */
 225#define SPEFSCR_FUNF	0x00000200	/* Embedded FP underflow */
 226#define SPEFSCR_FOVF	0x00000100	/* Embedded FP overflow */
 227#define SPEFSCR_FINXE	0x00000040	/* Embedded FP inexact enable */
 228#define SPEFSCR_FINVE	0x00000020	/* Embedded FP invalid op. enable */
 229#define SPEFSCR_FDBZE	0x00000010	/* Embedded FP div by zero enable */
 230#define SPEFSCR_FUNFE	0x00000008	/* Embedded FP underflow enable */
 231#define SPEFSCR_FOVFE	0x00000004	/* Embedded FP overflow enable */
 232#define SPEFSCR_FRMC 	0x00000003	/* Embedded FP rounding mode control */
 233
 234/* Special Purpose Registers (SPRNs)*/
 235
 236#define SPRN_PID	0x030	/* Process ID */
 237#ifdef CONFIG_BOOKE
 238#define SPRN_PID0	SPRN_PID/* Process ID Register 0 */
 239#endif
 240
 241#define SPRN_CTR	0x009	/* Count Register */
 242#define SPRN_DSCR	0x11
 243#define SPRN_CFAR	0x1c	/* Come From Address Register */
 244#define SPRN_AMR	0x1d	/* Authority Mask Register */
 245#define SPRN_UAMOR	0x9d	/* User Authority Mask Override Register */
 246#define SPRN_AMOR	0x15d	/* Authority Mask Override Register */
 247#define SPRN_ACOP	0x1F	/* Available Coprocessor Register */
 248#define SPRN_TFIAR	0x81	/* Transaction Failure Inst Addr   */
 249#define SPRN_TEXASR	0x82	/* Transaction EXception & Summary */
 250#define SPRN_TEXASRU	0x83	/* ''	   ''	   ''	 Upper 32  */
 251
 252#define TEXASR_FC_LG	(63 - 7)	/* Failure Code */
 253#define TEXASR_AB_LG	(63 - 31)	/* Abort */
 254#define TEXASR_SU_LG	(63 - 32)	/* Suspend */
 255#define TEXASR_HV_LG	(63 - 34)	/* Hypervisor state*/
 256#define TEXASR_PR_LG	(63 - 35)	/* Privilege level */
 257#define TEXASR_FS_LG	(63 - 36)	/* failure summary */
 258#define TEXASR_EX_LG	(63 - 37)	/* TFIAR exact bit */
 259#define TEXASR_ROT_LG	(63 - 38)	/* ROT bit */
 260
 261#define   TEXASR_ABORT	__MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
 262#define   TEXASR_SUSP	__MASK(TEXASR_SU_LG) /* tx failed in suspended state */
 263#define   TEXASR_HV	__MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
 264#define   TEXASR_PR	__MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
 265#define   TEXASR_FS	__MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
 266#define   TEXASR_EXACT	__MASK(TEXASR_EX_LG) /* TFIAR value is exact */
 267#define   TEXASR_ROT	__MASK(TEXASR_ROT_LG)
 268#define   TEXASR_FC	(ASM_CONST(0xFF) << TEXASR_FC_LG)
 269
 270#define SPRN_TFHAR	0x80	/* Transaction Failure Handler Addr */
 271
 272#define SPRN_TIDR	144	/* Thread ID register */
 273#define SPRN_CTRLF	0x088
 274#define SPRN_CTRLT	0x098
 275#define   CTRL_CT	0xc0000000	/* current thread */
 276#define   CTRL_CT0	0x80000000	/* thread 0 */
 277#define   CTRL_CT1	0x40000000	/* thread 1 */
 278#define   CTRL_TE	0x00c00000	/* thread enable */
 279#define   CTRL_RUNLATCH	0x1
 280#define SPRN_DAWR0	0xB4
 281#define SPRN_DAWR1	0xB5
 282#define SPRN_RPR	0xBA	/* Relative Priority Register */
 283#define SPRN_CIABR	0xBB
 284#define   CIABR_PRIV		0x3
 285#define   CIABR_PRIV_USER	1
 286#define   CIABR_PRIV_SUPER	2
 287#define   CIABR_PRIV_HYPER	3
 288#define SPRN_DAWRX0	0xBC
 289#define SPRN_DAWRX1	0xBD
 290#define   DAWRX_USER	__MASK(0)
 291#define   DAWRX_KERNEL	__MASK(1)
 292#define   DAWRX_HYP	__MASK(2)
 293#define   DAWRX_WTI	__MASK(3)
 294#define   DAWRX_WT	__MASK(4)
 295#define   DAWRX_DR	__MASK(5)
 296#define   DAWRX_DW	__MASK(6)
 297#define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
 298#define SPRN_DABR2	0x13D	/* e300 */
 299#define SPRN_DABRX	0x3F7	/* Data Address Breakpoint Register Extension */
 300#define   DABRX_USER	__MASK(0)
 301#define   DABRX_KERNEL	__MASK(1)
 302#define   DABRX_HYP	__MASK(2)
 303#define   DABRX_BTI	__MASK(3)
 304#define   DABRX_ALL     (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
 305#define SPRN_DAR	0x013	/* Data Address Register */
 306#define SPRN_DBCR	0x136	/* e300 Data Breakpoint Control Reg */
 307#define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
 308#define   DSISR_BAD_DIRECT_ST	0x80000000 /* Obsolete: Direct store error */
 309#define   DSISR_NOHPTE		0x40000000 /* no translation found */
 310#define   DSISR_ATTR_CONFLICT	0x20000000 /* P9: Process vs. Partition attr */
 311#define   DSISR_NOEXEC_OR_G	0x10000000 /* Alias of SRR1 bit, see below */
 312#define   DSISR_PROTFAULT	0x08000000 /* protection fault */
 313#define   DSISR_BADACCESS	0x04000000 /* bad access to CI or G */
 314#define   DSISR_ISSTORE		0x02000000 /* access was a store */
 315#define   DSISR_DABRMATCH	0x00400000 /* hit data breakpoint */
 316#define   DSISR_NOSEGMENT	0x00200000 /* STAB miss (unsupported) */
 317#define   DSISR_KEYFAULT	0x00200000 /* Storage Key fault */
 318#define   DSISR_BAD_EXT_CTRL	0x00100000 /* Obsolete: External ctrl error */
 319#define   DSISR_UNSUPP_MMU	0x00080000 /* P9: Unsupported MMU config */
 320#define   DSISR_SET_RC		0x00040000 /* P9: Failed setting of R/C bits */
 321#define   DSISR_PRTABLE_FAULT   0x00020000 /* P9: Fault on process table */
 322#define   DSISR_ICSWX_NO_CT     0x00004000 /* P7: icswx unavailable cp type */
 323#define   DSISR_BAD_COPYPASTE   0x00000008 /* P9: Copy/Paste on wrong memtype */
 324#define   DSISR_BAD_AMO		0x00000004 /* P9: Incorrect AMO opcode */
 325#define   DSISR_BAD_CI_LDST	0x00000002 /* P8: Bad HV CI load/store */
 326
 327/*
 328 * DSISR_NOEXEC_OR_G doesn't actually exist. This bit is always
 329 * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1
 330 * indicates an attempt at executing from a no-execute PTE
 331 * or segment or from a guarded page.
 332 *
 333 * We add a definition here for completeness as we alias
 334 * DSISR and SRR1 in do_page_fault.
 335 */
 336
 337/*
 338 * DSISR bits that are treated as a fault. Any bit set
 339 * here will skip hash_page, and cause do_page_fault to
 340 * trigger a SIGBUS or SIGSEGV:
 341 */
 342#define   DSISR_BAD_FAULT_32S	(DSISR_BAD_DIRECT_ST	| \
 343				 DSISR_BADACCESS	| \
 344				 DSISR_BAD_EXT_CTRL)
 345#define	  DSISR_BAD_FAULT_64S	(DSISR_BAD_FAULT_32S	| \
 346				 DSISR_ATTR_CONFLICT	| \
 347				 DSISR_UNSUPP_MMU	| \
 348				 DSISR_PRTABLE_FAULT	| \
 349				 DSISR_ICSWX_NO_CT	| \
 350				 DSISR_BAD_COPYPASTE	| \
 351				 DSISR_BAD_AMO		| \
 352				 DSISR_BAD_CI_LDST)
 353/*
 354 * These bits are equivalent in SRR1 and DSISR for 0x400
 355 * instruction access interrupts on Book3S
 356 */
 357#define   DSISR_SRR1_MATCH_32S	(DSISR_NOHPTE		| \
 358				 DSISR_NOEXEC_OR_G	| \
 359				 DSISR_PROTFAULT)
 360#define   DSISR_SRR1_MATCH_64S	(DSISR_SRR1_MATCH_32S	| \
 361				 DSISR_KEYFAULT		| \
 362				 DSISR_UNSUPP_MMU	| \
 363				 DSISR_SET_RC		| \
 364				 DSISR_PRTABLE_FAULT)
 365
 366#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register (user, R/O) */
 367#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register (user, R/O) */
 368#define SPRN_CIR	0x11B	/* Chip Information Register (hyper, R/0) */
 369#define SPRN_TBWL	0x11C	/* Time Base Lower Register (super, R/W) */
 370#define SPRN_TBWU	0x11D	/* Time Base Upper Register (super, R/W) */
 371#define SPRN_TBU40	0x11E	/* Timebase upper 40 bits (hyper, R/W) */
 372#define SPRN_SPURR	0x134	/* Scaled PURR */
 373#define SPRN_HSPRG0	0x130	/* Hypervisor Scratch 0 */
 374#define SPRN_HSPRG1	0x131	/* Hypervisor Scratch 1 */
 375#define SPRN_HDSISR     0x132
 376#define SPRN_HDAR       0x133
 377#define SPRN_HDEC	0x136	/* Hypervisor Decrementer */
 378#define SPRN_HIOR	0x137	/* 970 Hypervisor interrupt offset */
 379#define SPRN_RMOR	0x138	/* Real mode offset register */
 380#define SPRN_HRMOR	0x139	/* Real mode offset register */
 381#define SPRN_HDEXCR_RO	0x1C7	/* Hypervisor DEXCR (non-privileged, readonly) */
 382#define SPRN_HASHKEYR	0x1D4	/* Non-privileged hashst/hashchk key register */
 383#define SPRN_HDEXCR	0x1D7	/* Hypervisor dynamic execution control register */
 384#define SPRN_DEXCR_RO	0x32C	/* DEXCR (non-privileged, readonly) */
 385#define SPRN_ASDR	0x330	/* Access segment descriptor register */
 386#define SPRN_DEXCR	0x33C	/* Dynamic execution control register */
 387#define   DEXCR_PR_SBHE	  0x80000000UL /* 0: Speculative Branch Hint Enable */
 388#define   DEXCR_PR_IBRTPD 0x10000000UL /* 3: Indirect Branch Recurrent Target Prediction Disable */
 389#define   DEXCR_PR_SRAPD  0x08000000UL /* 4: Subroutine Return Address Prediction Disable */
 390#define   DEXCR_PR_NPHIE  0x04000000UL /* 5: Non-Privileged Hash Instruction Enable */
 391#define   DEXCR_INIT	DEXCR_PR_NPHIE	/* Fixed DEXCR value to initialise all CPUs with */
 392#define SPRN_IC		0x350	/* Virtual Instruction Count */
 393#define SPRN_VTB	0x351	/* Virtual Time Base */
 394#define SPRN_LDBAR	0x352	/* LD Base Address Register */
 395#define SPRN_PMICR	0x354   /* Power Management Idle Control Reg */
 396#define SPRN_PMSR	0x355   /* Power Management Status Reg */
 397#define SPRN_PMMAR	0x356	/* Power Management Memory Activity Register */
 398#define SPRN_PSSCR	0x357	/* Processor Stop Status and Control Register (ISA 3.0) */
 399#define SPRN_PSSCR_PR	0x337	/* PSSCR ISA 3.0, privileged mode access */
 400#define SPRN_TRIG2	0x372
 401#define SPRN_PMCR	0x374	/* Power Management Control Register */
 402#define SPRN_RWMR	0x375	/* Region-Weighting Mode Register */
 403
 404/* HFSCR and FSCR bit numbers are the same */
 405#define FSCR_PREFIX_LG	13	/* Enable Prefix Instructions */
 406#define FSCR_SCV_LG	12	/* Enable System Call Vectored */
 407#define FSCR_MSGP_LG	10	/* Enable MSGP */
 408#define FSCR_TAR_LG	8	/* Enable Target Address Register */
 409#define FSCR_EBB_LG	7	/* Enable Event Based Branching */
 410#define FSCR_TM_LG	5	/* Enable Transactional Memory */
 411#define FSCR_BHRB_LG	4	/* Enable Branch History Rolling Buffer*/
 412#define FSCR_PM_LG	3	/* Enable prob/priv access to PMU SPRs */
 413#define FSCR_DSCR_LG	2	/* Enable Data Stream Control Register */
 414#define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */
 415#define FSCR_FP_LG	0	/* Enable Floating Point */
 416#define SPRN_FSCR	0x099	/* Facility Status & Control Register */
 417#define   FSCR_PREFIX	__MASK(FSCR_PREFIX_LG)
 418#define   FSCR_SCV	__MASK(FSCR_SCV_LG)
 419#define   FSCR_TAR	__MASK(FSCR_TAR_LG)
 420#define   FSCR_EBB	__MASK(FSCR_EBB_LG)
 421#define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)
 422#define   FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56)	/* interrupt cause */
 423#define SPRN_HFSCR	0xbe	/* HV=1 Facility Status & Control Register */
 424#define   HFSCR_PREFIX	__MASK(FSCR_PREFIX_LG)
 425#define   HFSCR_MSGP	__MASK(FSCR_MSGP_LG)
 426#define   HFSCR_TAR	__MASK(FSCR_TAR_LG)
 427#define   HFSCR_EBB	__MASK(FSCR_EBB_LG)
 428#define   HFSCR_TM	__MASK(FSCR_TM_LG)
 429#define   HFSCR_PM	__MASK(FSCR_PM_LG)
 430#define   HFSCR_BHRB	__MASK(FSCR_BHRB_LG)
 431#define   HFSCR_DSCR	__MASK(FSCR_DSCR_LG)
 432#define   HFSCR_VECVSX	__MASK(FSCR_VECVSX_LG)
 433#define   HFSCR_FP	__MASK(FSCR_FP_LG)
 434#define   HFSCR_INTR_CAUSE FSCR_INTR_CAUSE
 435#define SPRN_TAR	0x32f	/* Target Address Register */
 436#define SPRN_LPCR	0x13E	/* LPAR Control Register */
 437#define   LPCR_VPM0		ASM_CONST(0x8000000000000000)
 438#define   LPCR_VPM1		ASM_CONST(0x4000000000000000)
 439#define   LPCR_ISL		ASM_CONST(0x2000000000000000)
 440#define   LPCR_VC_SH		61
 441#define   LPCR_DPFD_SH		52
 442#define   LPCR_DPFD		(ASM_CONST(7) << LPCR_DPFD_SH)
 443#define   LPCR_VRMASD_SH	47
 444#define   LPCR_VRMASD		(ASM_CONST(0x1f) << LPCR_VRMASD_SH)
 445#define   LPCR_VRMA_L		ASM_CONST(0x0008000000000000)
 446#define   LPCR_VRMA_LP0		ASM_CONST(0x0001000000000000)
 447#define   LPCR_VRMA_LP1		ASM_CONST(0x0000800000000000)
 448#define   LPCR_RMLS		0x1C000000	/* Implementation dependent RMO limit sel */
 449#define   LPCR_RMLS_SH		26
 450#define   LPCR_HAIL		ASM_CONST(0x0000000004000000)   /* HV AIL (ISAv3.1) */
 451#define   LPCR_ILE		ASM_CONST(0x0000000002000000)   /* !HV irqs set MSR:LE */
 452#define   LPCR_AIL		ASM_CONST(0x0000000001800000)	/* Alternate interrupt location */
 453#define   LPCR_AIL_0		ASM_CONST(0x0000000000000000)	/* MMU off exception offset 0x0 */
 454#define   LPCR_AIL_3		ASM_CONST(0x0000000001800000)   /* MMU on exception offset 0xc00...4xxx */
 455#define   LPCR_ONL		ASM_CONST(0x0000000000040000)	/* online - PURR/SPURR count */
 456#define   LPCR_LD		ASM_CONST(0x0000000000020000)	/* large decremeter */
 457#define   LPCR_PECE		ASM_CONST(0x000000000001f000)	/* powersave exit cause enable */
 458#define     LPCR_PECEDP	ASM_CONST(0x0000000000010000)	/* directed priv dbells cause exit */
 459#define     LPCR_PECEDH	ASM_CONST(0x0000000000008000)	/* directed hyp dbells cause exit */
 460#define     LPCR_PECE0		ASM_CONST(0x0000000000004000)	/* ext. exceptions can cause exit */
 461#define     LPCR_PECE1		ASM_CONST(0x0000000000002000)	/* decrementer can cause exit */
 462#define     LPCR_PECE2		ASM_CONST(0x0000000000001000)	/* machine check etc can cause exit */
 463#define     LPCR_PECE_HVEE	ASM_CONST(0x0000400000000000)	/* P9 Wakeup on HV interrupts */
 464#define   LPCR_MER		ASM_CONST(0x0000000000000800)	/* Mediated External Exception */
 465#define   LPCR_MER_SH		11
 466#define	  LPCR_GTSE		ASM_CONST(0x0000000000000400)  	/* Guest Translation Shootdown Enable */
 467#define   LPCR_TC		ASM_CONST(0x0000000000000200)	/* Translation control */
 468#define   LPCR_HEIC		ASM_CONST(0x0000000000000010)   /* Hypervisor External Interrupt Control */
 469#define   LPCR_LPES		0x0000000c
 470#define   LPCR_LPES0		ASM_CONST(0x0000000000000008)      /* LPAR Env selector 0 */
 471#define   LPCR_LPES1		ASM_CONST(0x0000000000000004)      /* LPAR Env selector 1 */
 472#define   LPCR_LPES_SH		2
 473#define   LPCR_RMI		ASM_CONST(0x0000000000000002)      /* real mode is cache inhibit */
 474#define   LPCR_HVICE		ASM_CONST(0x0000000000000002)      /* P9: HV interrupt enable */
 475#define   LPCR_HDICE		ASM_CONST(0x0000000000000001)      /* Hyp Decr enable (HV,PR,EE) */
 476#define   LPCR_UPRT		ASM_CONST(0x0000000000400000)      /* Use Process Table (ISA 3) */
 477#define   LPCR_HR		ASM_CONST(0x0000000000100000)
 478#ifndef SPRN_LPID
 479#define SPRN_LPID	0x13F	/* Logical Partition Identifier */
 480#endif
 481#define	SPRN_HMER	0x150	/* Hypervisor maintenance exception reg */
 482#define   HMER_DEBUG_TRIG	(1ul << (63 - 17)) /* Debug trigger */
 483#define	SPRN_HMEER	0x151	/* Hyp maintenance exception enable reg */
 484#define SPRN_PCR	0x152	/* Processor compatibility register */
 485#define   PCR_VEC_DIS	(__MASK(63-0))	/* Vec. disable (bit NA since POWER8) */
 486#define   PCR_VSX_DIS	(__MASK(63-1))	/* VSX disable (bit NA since POWER8) */
 487#define   PCR_TM_DIS	(__MASK(63-2))	/* Trans. memory disable (POWER8) */
 488#define   PCR_MMA_DIS	(__MASK(63-3)) /* Matrix-Multiply Accelerator */
 489#define   PCR_HIGH_BITS	(PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
 490/*
 491 * These bits are used in the function kvmppc_set_arch_compat() to specify and
 492 * determine both the compatibility level which we want to emulate and the
 493 * compatibility level which the host is capable of emulating.
 494 */
 495#define   PCR_ARCH_300	0x10		/* Architecture 3.00 */
 496#define   PCR_ARCH_207	0x8		/* Architecture 2.07 */
 497#define   PCR_ARCH_206	0x4		/* Architecture 2.06 */
 498#define   PCR_ARCH_205	0x2		/* Architecture 2.05 */
 499#define   PCR_LOW_BITS	(PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
 500#define   PCR_MASK	~(PCR_HIGH_BITS | PCR_LOW_BITS)	/* PCR Reserved Bits */
 501#define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */
 502#define SPRN_TLBINDEXR	0x154	/* P7 TLB control register */
 503#define SPRN_TLBVPNR	0x155	/* P7 TLB control register */
 504#define SPRN_TLBRPNR	0x156	/* P7 TLB control register */
 505#define SPRN_TLBLPIDR	0x157	/* P7 TLB control register */
 506#define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
 507#define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
 508#define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
 509#define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
 510#define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
 511#define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
 512#define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
 513#define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
 514#define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
 515#define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
 516#define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
 517#define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
 518#define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
 519#define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
 520#define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
 521#define SPRN_DBAT7U	0x23E	/* Data BAT 7 Upper Register */
 522#define SPRN_PPR	0x380	/* SMT Thread status Register */
 523#define SPRN_TSCR	0x399	/* Thread Switch Control Register */
 524
 525#define SPRN_DEC	0x016		/* Decrement Register */
 526#define SPRN_PIT	0x3DB		/* Programmable Interval Timer (BOOKE) */
 527
 528#define SPRN_DER	0x095		/* Debug Enable Register */
 529#define DER_RSTE	0x40000000	/* Reset Interrupt */
 530#define DER_CHSTPE	0x20000000	/* Check Stop */
 531#define DER_MCIE	0x10000000	/* Machine Check Interrupt */
 532#define DER_EXTIE	0x02000000	/* External Interrupt */
 533#define DER_ALIE	0x01000000	/* Alignment Interrupt */
 534#define DER_PRIE	0x00800000	/* Program Interrupt */
 535#define DER_FPUVIE	0x00400000	/* FP Unavailable Interrupt */
 536#define DER_DECIE	0x00200000	/* Decrementer Interrupt */
 537#define DER_SYSIE	0x00040000	/* System Call Interrupt */
 538#define DER_TRE		0x00020000	/* Trace Interrupt */
 539#define DER_SEIE	0x00004000	/* FP SW Emulation Interrupt */
 540#define DER_ITLBMSE	0x00002000	/* Imp. Spec. Instruction TLB Miss */
 541#define DER_ITLBERE	0x00001000	/* Imp. Spec. Instruction TLB Error */
 542#define DER_DTLBMSE	0x00000800	/* Imp. Spec. Data TLB Miss */
 543#define DER_DTLBERE	0x00000400	/* Imp. Spec. Data TLB Error */
 544#define DER_LBRKE	0x00000008	/* Load/Store Breakpoint Interrupt */
 545#define DER_IBRKE	0x00000004	/* Instruction Breakpoint Interrupt */
 546#define DER_EBRKE	0x00000002	/* External Breakpoint Interrupt */
 547#define DER_DPIE	0x00000001	/* Dev. Port Nonmaskable Request */
 548#define SPRN_DMISS	0x3D0		/* Data TLB Miss Register */
 549#define SPRN_DHDES	0x0B1		/* Directed Hyp. Doorbell Exc. State */
 550#define SPRN_DPDES	0x0B0		/* Directed Priv. Doorbell Exc. State */
 551#define SPRN_EAR	0x11A		/* External Address Register */
 552#define SPRN_HASH1	0x3D2		/* Primary Hash Address Register */
 553#define SPRN_HASH2	0x3D3		/* Secondary Hash Address Register */
 554#define SPRN_HID0	0x3F0		/* Hardware Implementation Register 0 */
 555#define HID0_HDICE_SH	(63 - 23)	/* 970 HDEC interrupt enable */
 556#define HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
 557#define HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
 558#define HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
 559#define HID0_SBCLK	(1<<27)
 560#define HID0_EICE	(1<<26)
 561#define HID0_TBEN	(1<<26)		/* Timebase enable - 745x */
 562#define HID0_ECLK	(1<<25)
 563#define HID0_PAR	(1<<24)
 564#define HID0_STEN	(1<<24)		/* Software table search enable - 745x */
 565#define HID0_HIGH_BAT	(1<<23)		/* Enable high BATs - 7455 */
 566#define HID0_DOZE	(1<<23)
 567#define HID0_NAP	(1<<22)
 568#define HID0_SLEEP	(1<<21)
 569#define HID0_DPM	(1<<20)
 570#define HID0_BHTCLR	(1<<18)		/* Clear branch history table - 7450 */
 571#define HID0_XAEN	(1<<17)		/* Extended addressing enable - 7450 */
 572#define HID0_NHR	(1<<16)		/* Not hard reset (software bit-7450)*/
 573#define HID0_ICE	(1<<15)		/* Instruction Cache Enable */
 574#define HID0_DCE	(1<<14)		/* Data Cache Enable */
 575#define HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
 576#define HID0_DLOCK	(1<<12)		/* Data Cache Lock */
 577#define HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
 578#define HID0_DCI	(1<<10)		/* Data Cache Invalidate */
 579#define HID0_SPD	(1<<9)		/* Speculative disable */
 580#define HID0_DAPUEN	(1<<8)		/* Debug APU enable */
 581#define HID0_SGE	(1<<7)		/* Store Gathering Enable */
 582#define HID0_SIED	(1<<7)		/* Serial Instr. Execution [Disable] */
 583#define HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
 584#define HID0_LRSTK	(1<<4)		/* Link register stack - 745x */
 585#define HID0_BTIC	(1<<5)		/* Branch Target Instr Cache Enable */
 586#define HID0_ABE	(1<<3)		/* Address Broadcast Enable */
 587#define HID0_FOLD	(1<<3)		/* Branch Folding enable - 745x */
 588#define HID0_BHTE	(1<<2)		/* Branch History Table Enable */
 589#define HID0_BTCD	(1<<1)		/* Branch target cache disable */
 590#define HID0_NOPDST	(1<<1)		/* No-op dst, dstt, etc. instr. */
 591#define HID0_NOPTI	(1<<0)		/* No-op dcbt and dcbst instr. */
 592/* POWER8 HID0 bits */
 593#define HID0_POWER8_4LPARMODE	__MASK(61)
 594#define HID0_POWER8_2LPARMODE	__MASK(57)
 595#define HID0_POWER8_1TO2LPAR	__MASK(52)
 596#define HID0_POWER8_1TO4LPAR	__MASK(51)
 597#define HID0_POWER8_DYNLPARDIS	__MASK(48)
 598
 599/* POWER9 HID0 bits */
 600#define HID0_POWER9_RADIX	__MASK(63 - 8)
 601
 602#define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
 603#ifdef CONFIG_PPC_BOOK3S_32
 604#define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
 605#define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
 606#define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
 607#define HID1_PC1	(1<<15)		/* 7450 PLL_CFG[1] */
 608#define HID1_PC2	(1<<14)		/* 7450 PLL_CFG[2] */
 609#define HID1_PC3	(1<<13)		/* 7450 PLL_CFG[3] */
 610#define HID1_SYNCBE	(1<<11)		/* 7450 ABE for sync, eieio */
 611#define HID1_ABE	(1<<10)		/* 7450 Address Broadcast Enable */
 612#define HID1_PS		(1<<16)		/* 750FX PLL selection */
 613#endif
 614#define SPRN_HID2_750FX	0x3F8		/* IBM 750FX HID2 Register */
 615#define SPRN_HID2_GEKKO	0x398		/* Gekko HID2 Register */
 616#define SPRN_HID2_G2_LE	0x3F3		/* G2_LE HID2 Register */
 617#define  HID2_G2_LE_HBE	(1<<18)		/* High BAT Enable (G2_LE) */
 618#define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
 619#define SPRN_IABR2	0x3FA		/* 83xx */
 620#define SPRN_IBCR	0x135		/* 83xx Insn Breakpoint Control Reg */
 621#define SPRN_IAMR	0x03D		/* Instr. Authority Mask Reg */
 622#define SPRN_HID4	0x3F4		/* 970 HID4 */
 623#define  HID4_LPES0	 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
 624#define	 HID4_RMLS2_SH	 (63 - 2)	/* Real mode limit bottom 2 bits */
 625#define	 HID4_LPID5_SH	 (63 - 6)	/* partition ID bottom 4 bits */
 626#define	 HID4_RMOR_SH	 (63 - 22)	/* real mode offset (16 bits) */
 627#define  HID4_RMOR	 (0xFFFFul << HID4_RMOR_SH)
 628#define  HID4_LPES1	 (1 << (63-57))	/* LPAR env. sel. bit 1 */
 629#define  HID4_RMLS0_SH	 (63 - 58)	/* Real mode limit top bit */
 630#define	 HID4_LPID1_SH	 0		/* partition ID top 2 bits */
 631#define SPRN_HID4_GEKKO	0x3F3		/* Gekko HID4 */
 632#define SPRN_HID5	0x3F6		/* 970 HID5 */
 633#define SPRN_HID6	0x3F9	/* BE HID 6 */
 634#define   HID6_LB	(0x0F<<12) /* Concurrent Large Page Modes */
 635#define   HID6_DLP	(1<<20)	/* Disable all large page modes (4K only) */
 636#define SPRN_TSC_CELL	0x399	/* Thread switch control on Cell */
 637#define   TSC_CELL_DEC_ENABLE_0	0x400000 /* Decrementer Interrupt */
 638#define   TSC_CELL_DEC_ENABLE_1	0x200000 /* Decrementer Interrupt */
 639#define   TSC_CELL_EE_ENABLE	0x100000 /* External Interrupt */
 640#define   TSC_CELL_EE_BOOST	0x080000 /* External Interrupt Boost */
 641#define SPRN_TSC 	0x3FD	/* Thread switch control on others */
 642#define SPRN_TST 	0x3FC	/* Thread switch timeout on others */
 643#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
 644#define SPRN_IAC1	0x3F4		/* Instruction Address Compare 1 */
 645#define SPRN_IAC2	0x3F5		/* Instruction Address Compare 2 */
 646#endif
 647#define SPRN_IBAT0L	0x211		/* Instruction BAT 0 Lower Register */
 648#define SPRN_IBAT0U	0x210		/* Instruction BAT 0 Upper Register */
 649#define SPRN_IBAT1L	0x213		/* Instruction BAT 1 Lower Register */
 650#define SPRN_IBAT1U	0x212		/* Instruction BAT 1 Upper Register */
 651#define SPRN_IBAT2L	0x215		/* Instruction BAT 2 Lower Register */
 652#define SPRN_IBAT2U	0x214		/* Instruction BAT 2 Upper Register */
 653#define SPRN_IBAT3L	0x217		/* Instruction BAT 3 Lower Register */
 654#define SPRN_IBAT3U	0x216		/* Instruction BAT 3 Upper Register */
 655#define SPRN_IBAT4L	0x231		/* Instruction BAT 4 Lower Register */
 656#define SPRN_IBAT4U	0x230		/* Instruction BAT 4 Upper Register */
 657#define SPRN_IBAT5L	0x233		/* Instruction BAT 5 Lower Register */
 658#define SPRN_IBAT5U	0x232		/* Instruction BAT 5 Upper Register */
 659#define SPRN_IBAT6L	0x235		/* Instruction BAT 6 Lower Register */
 660#define SPRN_IBAT6U	0x234		/* Instruction BAT 6 Upper Register */
 661#define SPRN_IBAT7L	0x237		/* Instruction BAT 7 Lower Register */
 662#define SPRN_IBAT7U	0x236		/* Instruction BAT 7 Upper Register */
 663#define SPRN_ICMP	0x3D5		/* Instruction TLB Compare Register */
 664#define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
 665#ifndef SPRN_ICTRL
 666#define SPRN_ICTRL	0x3F3	/* 1011 7450 icache and interrupt ctrl */
 667#endif
 668#define ICTRL_EICE	0x08000000	/* enable icache parity errs */
 669#define ICTRL_EDC	0x04000000	/* enable dcache parity errs */
 670#define ICTRL_EICP	0x00000100	/* enable icache par. check */
 671#define SPRN_IMISS	0x3D4		/* Instruction TLB Miss Register */
 672#define SPRN_IMMR	0x27E		/* Internal Memory Map Register */
 673#define SPRN_L2CR	0x3F9		/* Level 2 Cache Control Register */
 674#define SPRN_L2CR2	0x3f8
 675#define L2CR_L2E		0x80000000	/* L2 enable */
 676#define L2CR_L2PE		0x40000000	/* L2 parity enable */
 677#define L2CR_L2SIZ_MASK		0x30000000	/* L2 size mask */
 678#define L2CR_L2SIZ_256KB	0x10000000	/* L2 size 256KB */
 679#define L2CR_L2SIZ_512KB	0x20000000	/* L2 size 512KB */
 680#define L2CR_L2SIZ_1MB		0x30000000	/* L2 size 1MB */
 681#define L2CR_L2CLK_MASK		0x0e000000	/* L2 clock mask */
 682#define L2CR_L2CLK_DISABLED	0x00000000	/* L2 clock disabled */
 683#define L2CR_L2CLK_DIV1		0x02000000	/* L2 clock / 1 */
 684#define L2CR_L2CLK_DIV1_5	0x04000000	/* L2 clock / 1.5 */
 685#define L2CR_L2CLK_DIV2		0x08000000	/* L2 clock / 2 */
 686#define L2CR_L2CLK_DIV2_5	0x0a000000	/* L2 clock / 2.5 */
 687#define L2CR_L2CLK_DIV3		0x0c000000	/* L2 clock / 3 */
 688#define L2CR_L2RAM_MASK		0x01800000	/* L2 RAM type mask */
 689#define L2CR_L2RAM_FLOW		0x00000000	/* L2 RAM flow through */
 690#define L2CR_L2RAM_PIPE		0x01000000	/* L2 RAM pipelined */
 691#define L2CR_L2RAM_PIPE_LW	0x01800000	/* L2 RAM pipelined latewr */
 692#define L2CR_L2DO		0x00400000	/* L2 data only */
 693#define L2CR_L2I		0x00200000	/* L2 global invalidate */
 694#define L2CR_L2CTL		0x00100000	/* L2 RAM control */
 695#define L2CR_L2WT		0x00080000	/* L2 write-through */
 696#define L2CR_L2TS		0x00040000	/* L2 test support */
 697#define L2CR_L2OH_MASK		0x00030000	/* L2 output hold mask */
 698#define L2CR_L2OH_0_5		0x00000000	/* L2 output hold 0.5 ns */
 699#define L2CR_L2OH_1_0		0x00010000	/* L2 output hold 1.0 ns */
 700#define L2CR_L2SL		0x00008000	/* L2 DLL slow */
 701#define L2CR_L2DF		0x00004000	/* L2 differential clock */
 702#define L2CR_L2BYP		0x00002000	/* L2 DLL bypass */
 703#define L2CR_L2IP		0x00000001	/* L2 GI in progress */
 704#define L2CR_L2IO_745x		0x00100000	/* L2 instr. only (745x) */
 705#define L2CR_L2DO_745x		0x00010000	/* L2 data only (745x) */
 706#define L2CR_L2REP_745x		0x00001000	/* L2 repl. algorithm (745x) */
 707#define L2CR_L2HWF_745x		0x00000800	/* L2 hardware flush (745x) */
 708#define SPRN_L3CR		0x3FA	/* Level 3 Cache Control Register */
 709#define L3CR_L3E		0x80000000	/* L3 enable */
 710#define L3CR_L3PE		0x40000000	/* L3 data parity enable */
 711#define L3CR_L3APE		0x20000000	/* L3 addr parity enable */
 712#define L3CR_L3SIZ		0x10000000	/* L3 size */
 713#define L3CR_L3CLKEN		0x08000000	/* L3 clock enable */
 714#define L3CR_L3RES		0x04000000	/* L3 special reserved bit */
 715#define L3CR_L3CLKDIV		0x03800000	/* L3 clock divisor */
 716#define L3CR_L3IO		0x00400000	/* L3 instruction only */
 717#define L3CR_L3SPO		0x00040000	/* L3 sample point override */
 718#define L3CR_L3CKSP		0x00030000	/* L3 clock sample point */
 719#define L3CR_L3PSP		0x0000e000	/* L3 P-clock sample point */
 720#define L3CR_L3REP		0x00001000	/* L3 replacement algorithm */
 721#define L3CR_L3HWF		0x00000800	/* L3 hardware flush */
 722#define L3CR_L3I		0x00000400	/* L3 global invalidate */
 723#define L3CR_L3RT		0x00000300	/* L3 SRAM type */
 724#define L3CR_L3NIRCA		0x00000080	/* L3 non-integer ratio clock adj. */
 725#define L3CR_L3DO		0x00000040	/* L3 data only mode */
 726#define L3CR_PMEN		0x00000004	/* L3 private memory enable */
 727#define L3CR_PMSIZ		0x00000001	/* L3 private memory size */
 728
 729#define SPRN_MSSCR0	0x3f6	/* Memory Subsystem Control Register 0 */
 730#define SPRN_MSSSR0	0x3f7	/* Memory Subsystem Status Register 1 */
 731#define SPRN_LDSTCR	0x3f8	/* Load/Store control register */
 732#define SPRN_LDSTDB	0x3f4	/* */
 733#define SPRN_LR		0x008	/* Link Register */
 734#ifndef SPRN_PIR
 735#define SPRN_PIR	0x3FF	/* Processor Identification Register */
 736#endif
 737#define SPRN_TIR	0x1BE	/* Thread Identification Register */
 738#define SPRN_PTCR	0x1D0	/* Partition table control Register */
 739#define SPRN_PSPB	0x09F	/* Problem State Priority Boost reg */
 740#define SPRN_PTEHI	0x3D5	/* 981 7450 PTE HI word (S/W TLB load) */
 741#define SPRN_PTELO	0x3D6	/* 982 7450 PTE LO word (S/W TLB load) */
 742#define SPRN_PURR	0x135	/* Processor Utilization of Resources Reg */
 743#define SPRN_PVR	0x11F	/* Processor Version Register */
 744#define SPRN_RPA	0x3D6	/* Required Physical Address Register */
 745#define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
 746#define SPRN_SDR1	0x019	/* MMU Hash Base Register */
 747#define SPRN_ASR	0x118   /* Address Space Register */
 748#define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
 749#define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
 750#define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
 751#define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
 752#define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
 753#define SPRN_USPRG3	0x103	/* SPRG3 userspace read */
 754#define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
 755#define SPRN_USPRG4	0x104	/* SPRG4 userspace read */
 756#define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
 757#define SPRN_USPRG5	0x105	/* SPRG5 userspace read */
 758#define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
 759#define SPRN_USPRG6	0x106	/* SPRG6 userspace read */
 760#define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
 761#define SPRN_USPRG7	0x107	/* SPRG7 userspace read */
 762#define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
 763#define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
 764
 765#ifdef CONFIG_PPC_BOOK3S
 766/*
 767 * Bits loaded from MSR upon interrupt.
 768 * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are
 769 * loaded from MSR. The exception is that SRESET and MCE do not always load
 770 * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses
 771 * it.
 772 */
 773#define   SRR1_MSR_BITS		(~0x783f0000UL)
 774#endif
 775
 776#define   SRR1_ISI_NOPT		0x40000000 /* ISI: Not found in hash */
 777#define   SRR1_ISI_N_G_OR_CIP	0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instruction */
 778#define   SRR1_ISI_PROT		0x08000000 /* ISI: Other protection fault */
 779#define   SRR1_WAKEMASK		0x00380000 /* reason for wakeup */
 780#define   SRR1_WAKEMASK_P8	0x003c0000 /* reason for wakeup on POWER8 and 9 */
 781#define   SRR1_WAKEMCE_RESVD	0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cause to idle wakeup handler */
 782#define   SRR1_WAKESYSERR	0x00300000 /* System error */
 783#define   SRR1_WAKEEE		0x00200000 /* External interrupt */
 784#define   SRR1_WAKEHVI		0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
 785#define   SRR1_WAKEMT		0x00280000 /* mtctrl */
 786#define	  SRR1_WAKEHMI		0x00280000 /* Hypervisor maintenance */
 787#define   SRR1_WAKEDEC		0x00180000 /* Decrementer interrupt */
 788#define   SRR1_WAKEDBELL	0x00140000 /* Privileged doorbell on P8 */
 789#define   SRR1_WAKETHERM	0x00100000 /* Thermal management interrupt */
 790#define	  SRR1_WAKERESET	0x00100000 /* System reset */
 791#define   SRR1_WAKEHDBELL	0x000c0000 /* Hypervisor doorbell on P8 */
 792#define	  SRR1_WAKESTATE	0x00030000 /* Powersave exit mask [46:47] */
 793#define	  SRR1_WS_HVLOSS	0x00030000 /* HV resources not maintained */
 794#define	  SRR1_WS_GPRLOSS	0x00020000 /* GPRs not maintained */
 795#define	  SRR1_WS_NOLOSS	0x00010000 /* All resources maintained */
 796#define   SRR1_PROGTM		0x00200000 /* TM Bad Thing */
 797#define   SRR1_PROGFPE		0x00100000 /* Floating Point Enabled */
 798#define   SRR1_PROGILL		0x00080000 /* Illegal instruction */
 799#define   SRR1_PROGPRIV		0x00040000 /* Privileged instruction */
 800#define   SRR1_PROGTRAP		0x00020000 /* Trap */
 801#define   SRR1_PROGADDR		0x00010000 /* SRR0 contains subsequent addr */
 802
 803#define   SRR1_MCE_MCP		0x00080000 /* Machine check signal caused interrupt */
 804#define   SRR1_BOUNDARY		0x10000000 /* Prefixed instruction crosses 64-byte boundary */
 805#define   SRR1_PREFIXED		0x20000000 /* Exception caused by prefixed instruction */
 806
 807#define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
 808#define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
 809#define   HSRR1_DENORM		0x00100000 /* Denorm exception */
 810#define   HSRR1_HISI_WRITE	0x00010000 /* HISI bcs couldn't update mem */
 811
 812#define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
 813#define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */
 814#define   TBCTL_RESTART		0x0000000100000000ull /* Restart all tbs */
 815#define   TBCTL_UPDATE_UPPER	0x0000000200000000ull /* Set upper 32 bits */
 816#define   TBCTL_UPDATE_LOWER	0x0000000300000000ull /* Set lower 32 bits */
 817
 818#ifndef SPRN_SVR
 819#define SPRN_SVR	0x11E	/* System Version Register */
 820#endif
 821#define SPRN_THRM1	0x3FC		/* Thermal Management Register 1 */
 822/* these bits were defined in inverted endian sense originally, ugh, confusing */
 823#define THRM1_TIN	(1 << 31)
 824#define THRM1_TIV	(1 << 30)
 825#define THRM1_THRES(x)	((x&0x7f)<<23)
 826#define THRM3_SITV(x)	((x & 0x1fff) << 1)
 827#define THRM1_TID	(1<<2)
 828#define THRM1_TIE	(1<<1)
 829#define THRM1_V		(1<<0)
 830#define SPRN_THRM2	0x3FD		/* Thermal Management Register 2 */
 831#define SPRN_THRM3	0x3FE		/* Thermal Management Register 3 */
 832#define THRM3_E		(1<<0)
 833#define SPRN_TLBMISS	0x3D4		/* 980 7450 TLB Miss Register */
 834#define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
 835#define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
 836#define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
 837#define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
 838#define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
 839#define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
 840#define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
 841#define SPRN_VRSAVE	0x100	/* Vector Register Save Register */
 842#define SPRN_XER	0x001	/* Fixed Point Exception Register */
 843
 844#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
 845#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
 846#define SPRN_PMC1_GEKKO  0x3B9 /* Gekko Performance Monitor Control 1 */
 847#define SPRN_PMC2_GEKKO  0x3BA /* Gekko Performance Monitor Control 2 */
 848#define SPRN_PMC3_GEKKO  0x3BD /* Gekko Performance Monitor Control 3 */
 849#define SPRN_PMC4_GEKKO  0x3BE /* Gekko Performance Monitor Control 4 */
 850#define SPRN_WPAR_GEKKO  0x399 /* Gekko Write Pipe Address Register */
 851
 852#define SPRN_SCOMC	0x114	/* SCOM Access Control */
 853#define SPRN_SCOMD	0x115	/* SCOM Access DATA */
 854
 855/* Performance monitor SPRs */
 856#ifdef CONFIG_PPC64
 857#define SPRN_MMCR0	795
 858#define   MMCR0_FC	0x80000000UL /* freeze counters */
 859#define   MMCR0_FCS	0x40000000UL /* freeze in supervisor state */
 860#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
 861#define   MMCR0_FCP	0x20000000UL /* freeze in problem state */
 862#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
 863#define   MMCR0_FCM1	0x10000000UL /* freeze counters while MSR mark = 1 */
 864#define   MMCR0_FCM0	0x08000000UL /* freeze counters while MSR mark = 0 */
 865#define   MMCR0_PMXE	ASM_CONST(0x04000000) /* perf mon exception enable */
 866#define   MMCR0_FCECE	ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
 867#define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
 868#define   MMCR0_BHRBA	0x00200000UL /* BHRB Access allowed in userspace */
 869#define   MMCR0_EBE	0x00100000UL /* Event based branch enable */
 870#define   MMCR0_PMCC	0x000c0000UL /* PMC control */
 871#define   MMCR0_PMCCEXT	ASM_CONST(0x00000200) /* PMCCEXT control */
 872#define   MMCR0_PMCC_U6	0x00080000UL /* PMC1-6 are R/W by user (PR) */
 873#define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
 874#define   MMCR0_PMCjCE	ASM_CONST(0x00004000) /* PMCj count enable*/
 875#define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
 876#define   MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
 877#define   MMCR0_C56RUN	ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
 878/* performance monitor alert has occurred, set to 0 after handling exception */
 879#define   MMCR0_PMAO	ASM_CONST(0x00000080)
 880#define   MMCR0_SHRFC	0x00000040UL /* SHRre freeze conditions between threads */
 881#define   MMCR0_FC56	0x00000010UL /* freeze counters 5 and 6 */
 882#define   MMCR0_FCTI	0x00000008UL /* freeze counters in tags inactive mode */
 883#define   MMCR0_FCTA	0x00000004UL /* freeze counters in tags active mode */
 884#define   MMCR0_FCWAIT	0x00000002UL /* freeze counter in WAIT state */
 885#define   MMCR0_FCHV	0x00000001UL /* freeze conditions in hypervisor mode */
 886#define SPRN_MMCR1	798
 887#define SPRN_MMCR2	785
 888#define SPRN_MMCR3	754
 889#define SPRN_UMMCR2	769
 890#define SPRN_UMMCR3	738
 891#define SPRN_MMCRA	0x312
 892#define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */
 893#define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
 894#define   MMCRA_SDAR_ERAT_MISS   0x20000000UL
 895#define   MMCRA_SIHV	0x10000000UL /* state of MSR HV when SIAR set */
 896#define   MMCRA_SIPR	0x08000000UL /* state of MSR PR when SIAR set */
 897#define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
 898#define   MMCRA_SLOT_SHIFT	24
 899#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
 900#define   MMCRA_BHRB_DISABLE  _UL(0x2000000000) // BHRB disable bit for ISA v3.1
 901#define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL	/* SDAR/SIAR synced */
 902#define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
 903#define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
 904#define   POWER6_MMCRA_THRM	0x00000020UL
 905#define   POWER6_MMCRA_OTHER	0x0000000EUL
 906
 907#define   POWER7P_MMCRA_SIAR_VALID 0x10000000	/* P7+ SIAR contents valid */
 908#define   POWER7P_MMCRA_SDAR_VALID 0x08000000	/* P7+ SDAR contents valid */
 909
 910#define SPRN_MMCRH	316	/* Hypervisor monitor mode control register */
 911#define SPRN_MMCRS	894	/* Supervisor monitor mode control register */
 912#define SPRN_MMCRC	851	/* Core monitor mode control register */
 913#define SPRN_EBBHR	804	/* Event based branch handler register */
 914#define SPRN_EBBRR	805	/* Event based branch return register */
 915#define SPRN_BESCR	806	/* Branch event status and control register */
 916#define   BESCR_GE	0x8000000000000000ULL /* Global Enable */
 917#define SPRN_WORT	895	/* Workload optimization register - thread */
 918#define SPRN_WORC	863	/* Workload optimization register - core */
 919
 920#define SPRN_PMC1	787
 921#define SPRN_PMC2	788
 922#define SPRN_PMC3	789
 923#define SPRN_PMC4	790
 924#define SPRN_PMC5	791
 925#define SPRN_PMC6	792
 926#define SPRN_PMC7	793
 927#define SPRN_PMC8	794
 928#define SPRN_SIER	784
 929#define   SIER_SIPR		0x2000000	/* Sampled MSR_PR */
 930#define   SIER_SIHV		0x1000000	/* Sampled MSR_HV */
 931#define   SIER_SIAR_VALID	0x0400000	/* SIAR contents valid */
 932#define   SIER_SDAR_VALID	0x0200000	/* SDAR contents valid */
 933#define SPRN_SIER2	752
 934#define SPRN_SIER3	753
 935#define SPRN_USIER2	736
 936#define SPRN_USIER3	737
 937#define SPRN_SIAR	796
 938#define SPRN_SDAR	797
 939#define SPRN_TACR	888
 940#define SPRN_TCSCR	889
 941#define SPRN_CSIGR	890
 942#define SPRN_SPMC1	892
 943#define SPRN_SPMC2	893
 944
 945/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
 946#define MMCR0_USER_MASK	(MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
 947#define MMCR2_USER_MASK	0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
 948#define SIER_USER_MASK	0x7fffffUL
 949
 950#define SPRN_PA6T_MMCR0 795
 951#define   PA6T_MMCR0_EN0	0x0000000000000001UL
 952#define   PA6T_MMCR0_EN1	0x0000000000000002UL
 953#define   PA6T_MMCR0_EN2	0x0000000000000004UL
 954#define   PA6T_MMCR0_EN3	0x0000000000000008UL
 955#define   PA6T_MMCR0_EN4	0x0000000000000010UL
 956#define   PA6T_MMCR0_EN5	0x0000000000000020UL
 957#define   PA6T_MMCR0_SUPEN	0x0000000000000040UL
 958#define   PA6T_MMCR0_PREN	0x0000000000000080UL
 959#define   PA6T_MMCR0_HYPEN	0x0000000000000100UL
 960#define   PA6T_MMCR0_FCM0	0x0000000000000200UL
 961#define   PA6T_MMCR0_FCM1	0x0000000000000400UL
 962#define   PA6T_MMCR0_INTGEN	0x0000000000000800UL
 963#define   PA6T_MMCR0_INTEN0	0x0000000000001000UL
 964#define   PA6T_MMCR0_INTEN1	0x0000000000002000UL
 965#define   PA6T_MMCR0_INTEN2	0x0000000000004000UL
 966#define   PA6T_MMCR0_INTEN3	0x0000000000008000UL
 967#define   PA6T_MMCR0_INTEN4	0x0000000000010000UL
 968#define   PA6T_MMCR0_INTEN5	0x0000000000020000UL
 969#define   PA6T_MMCR0_DISCNT	0x0000000000040000UL
 970#define   PA6T_MMCR0_UOP	0x0000000000080000UL
 971#define   PA6T_MMCR0_TRG	0x0000000000100000UL
 972#define   PA6T_MMCR0_TRGEN	0x0000000000200000UL
 973#define   PA6T_MMCR0_TRGREG	0x0000000001600000UL
 974#define   PA6T_MMCR0_SIARLOG	0x0000000002000000UL
 975#define   PA6T_MMCR0_SDARLOG	0x0000000004000000UL
 976#define   PA6T_MMCR0_PROEN	0x0000000008000000UL
 977#define   PA6T_MMCR0_PROLOG	0x0000000010000000UL
 978#define   PA6T_MMCR0_DAMEN2	0x0000000020000000UL
 979#define   PA6T_MMCR0_DAMEN3	0x0000000040000000UL
 980#define   PA6T_MMCR0_DAMEN4	0x0000000080000000UL
 981#define   PA6T_MMCR0_DAMEN5	0x0000000100000000UL
 982#define   PA6T_MMCR0_DAMSEL2	0x0000000200000000UL
 983#define   PA6T_MMCR0_DAMSEL3	0x0000000400000000UL
 984#define   PA6T_MMCR0_DAMSEL4	0x0000000800000000UL
 985#define   PA6T_MMCR0_DAMSEL5	0x0000001000000000UL
 986#define   PA6T_MMCR0_HANDDIS	0x0000002000000000UL
 987#define   PA6T_MMCR0_PCTEN	0x0000004000000000UL
 988#define   PA6T_MMCR0_SOCEN	0x0000008000000000UL
 989#define   PA6T_MMCR0_SOCMOD	0x0000010000000000UL
 990
 991#define SPRN_PA6T_MMCR1 798
 992#define   PA6T_MMCR1_ES2	0x00000000000000ffUL
 993#define   PA6T_MMCR1_ES3	0x000000000000ff00UL
 994#define   PA6T_MMCR1_ES4	0x0000000000ff0000UL
 995#define   PA6T_MMCR1_ES5	0x00000000ff000000UL
 996
 997#define SPRN_PA6T_UPMC0 771	/* User PerfMon Counter 0 */
 998#define SPRN_PA6T_UPMC1 772	/* ... */
 999#define SPRN_PA6T_UPMC2 773
1000#define SPRN_PA6T_UPMC3 774
1001#define SPRN_PA6T_UPMC4 775
1002#define SPRN_PA6T_UPMC5 776
1003#define SPRN_PA6T_UMMCR0 779	/* User Monitor Mode Control Register 0 */
1004#define SPRN_PA6T_SIAR	780	/* Sampled Instruction Address */
1005#define SPRN_PA6T_UMMCR1 782	/* User Monitor Mode Control Register 1 */
1006#define SPRN_PA6T_SIER	785	/* Sampled Instruction Event Register */
1007#define SPRN_PA6T_PMC0	787
1008#define SPRN_PA6T_PMC1	788
1009#define SPRN_PA6T_PMC2	789
1010#define SPRN_PA6T_PMC3	790
1011#define SPRN_PA6T_PMC4	791
1012#define SPRN_PA6T_PMC5	792
1013#define SPRN_PA6T_TSR0	793	/* Timestamp Register 0 */
1014#define SPRN_PA6T_TSR1	794	/* Timestamp Register 1 */
1015#define SPRN_PA6T_TSR2	799	/* Timestamp Register 2 */
1016#define SPRN_PA6T_TSR3	784	/* Timestamp Register 3 */
1017
1018#define SPRN_PA6T_IER	981	/* Icache Error Register */
1019#define SPRN_PA6T_DER	982	/* Dcache Error Register */
1020#define SPRN_PA6T_BER	862	/* BIU Error Address Register */
1021#define SPRN_PA6T_MER	849	/* MMU Error Register */
1022
1023#define SPRN_PA6T_IMA0	880	/* Instruction Match Array 0 */
1024#define SPRN_PA6T_IMA1	881	/* ... */
1025#define SPRN_PA6T_IMA2	882
1026#define SPRN_PA6T_IMA3	883
1027#define SPRN_PA6T_IMA4	884
1028#define SPRN_PA6T_IMA5	885
1029#define SPRN_PA6T_IMA6	886
1030#define SPRN_PA6T_IMA7	887
1031#define SPRN_PA6T_IMA8	888
1032#define SPRN_PA6T_IMA9	889
1033#define SPRN_PA6T_BTCR	978	/* Breakpoint and Tagging Control Register */
1034#define SPRN_PA6T_IMAAT	979	/* Instruction Match Array Action Table */
1035#define SPRN_PA6T_PCCR	1019	/* Power Counter Control Register */
1036#define SPRN_BKMK	1020	/* Cell Bookmark Register */
1037#define SPRN_PA6T_RPCCR	1021	/* Retire PC Trace Control Register */
1038
1039
1040#else /* 32-bit */
1041#define SPRN_MMCR0	952	/* Monitor Mode Control Register 0 */
1042#define   MMCR0_FC	0x80000000UL /* freeze counters */
1043#define   MMCR0_FCS	0x40000000UL /* freeze in supervisor state */
1044#define   MMCR0_FCP	0x20000000UL /* freeze in problem state */
1045#define   MMCR0_FCM1	0x10000000UL /* freeze counters while MSR mark = 1 */
1046#define   MMCR0_FCM0	0x08000000UL /* freeze counters while MSR mark = 0 */
1047#define   MMCR0_PMXE	0x04000000UL /* performance monitor exception enable */
1048#define   MMCR0_FCECE	0x02000000UL /* freeze ctrs on enabled cond or event */
1049#define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
1050#define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
1051#define   MMCR0_PMCnCE	0x00004000UL /* count enable for all but PMC 1*/
1052#define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
1053#define   MMCR0_PMC1SEL	0x00001fc0UL /* PMC 1 Event */
1054#define   MMCR0_PMC2SEL	0x0000003fUL /* PMC 2 Event */
1055
1056#define SPRN_MMCR1	956
1057#define   MMCR1_PMC3SEL	0xf8000000UL /* PMC 3 Event */
1058#define   MMCR1_PMC4SEL	0x07c00000UL /* PMC 4 Event */
1059#define   MMCR1_PMC5SEL	0x003e0000UL /* PMC 5 Event */
1060#define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
1061#define SPRN_MMCR2	944
1062#define SPRN_PMC1	953	/* Performance Counter Register 1 */
1063#define SPRN_PMC2	954	/* Performance Counter Register 2 */
1064#define SPRN_PMC3	957	/* Performance Counter Register 3 */
1065#define SPRN_PMC4	958	/* Performance Counter Register 4 */
1066#define SPRN_PMC5	945	/* Performance Counter Register 5 */
1067#define SPRN_PMC6	946	/* Performance Counter Register 6 */
1068
1069#define SPRN_SIAR	955	/* Sampled Instruction Address Register */
1070
1071/* Bit definitions for MMCR0 and PMC1 / PMC2. */
1072#define MMCR0_PMC1_CYCLES	(1 << 7)
1073#define MMCR0_PMC1_ICACHEMISS	(5 << 7)
1074#define MMCR0_PMC1_DTLB		(6 << 7)
1075#define MMCR0_PMC2_DCACHEMISS	0x6
1076#define MMCR0_PMC2_CYCLES	0x1
1077#define MMCR0_PMC2_ITLB		0x7
1078#define MMCR0_PMC2_LOADMISSTIME	0x5
1079#endif
1080
1081/*
1082 * SPRG usage:
1083 *
1084 * All 64-bit:
1085 *	- SPRG1 stores PACA pointer except 64-bit server in
1086 *        HV mode in which case it is HSPRG0
1087 *
1088 * 64-bit server:
1089 *	- SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
1090 *	- SPRG2 scratch for exception vectors
1091 *	- SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
1092 *      - HSPRG0 stores PACA in HV mode
1093 *      - HSPRG1 scratch for "HV" exceptions
1094 *
1095 * 64-bit embedded
1096 *	- SPRG0 generic exception scratch
1097 *	- SPRG2 TLB exception stack
1098 *	- SPRG3 critical exception scratch (user visible, sorry!)
1099 *	- SPRG4 unused (user visible)
1100 *	- SPRG6 TLB miss scratch (user visible, sorry !)
1101 *	- SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
1102 *	- SPRG8 machine check exception scratch
1103 *	- SPRG9 debug exception scratch
1104 *
1105 * All 32-bit:
1106 *	- SPRG3 current thread_struct physical addr pointer
1107 *        (virtual on BookE, physical on others)
1108 *
1109 * 32-bit classic:
1110 *	- SPRG0 scratch for exception vectors
1111 *	- SPRG1 scratch for exception vectors
1112 *	- SPRG2 indicator that we are in RTAS
1113 *	- SPRG4 (603 only) pseudo TLB LRU data
1114 *
1115 * 32-bit 440 and FSL BookE:
1116 *	- SPRG0 scratch for exception vectors
1117 *	- SPRG1 scratch for exception vectors (*)
1118 *	- SPRG2 scratch for crit interrupts handler
1119 *	- SPRG4 scratch for exception vectors
1120 *	- SPRG5 scratch for exception vectors
1121 *	- SPRG6 scratch for machine check handler
1122 *	- SPRG7 scratch for exception vectors
1123 *	- SPRG9 scratch for debug vectors (e500 only)
1124 *
1125 *      Additionally, BookE separates "read" and "write"
1126 *      of those registers. That allows to use the userspace
1127 *      readable variant for reads, which can avoid a fault
1128 *      with KVM type virtualization.
1129 *
1130 * 32-bit 8xx:
1131 *	- SPRG0 scratch for exception vectors
1132 *	- SPRG1 scratch for exception vectors
1133 *	- SPRG2 scratch for exception vectors
1134 *
1135 */
1136#ifdef CONFIG_PPC64
1137#define SPRN_SPRG_PACA 		SPRN_SPRG1
1138#else
1139#define SPRN_SPRG_THREAD 	SPRN_SPRG3
1140#endif
1141
1142#ifdef CONFIG_PPC_BOOK3S_64
1143#define SPRN_SPRG_SCRATCH0	SPRN_SPRG2
1144#define SPRN_SPRG_HPACA		SPRN_HSPRG0
1145#define SPRN_SPRG_HSCRATCH0	SPRN_HSPRG1
1146#define SPRN_SPRG_VDSO_READ	SPRN_USPRG3
1147#define SPRN_SPRG_VDSO_WRITE	SPRN_SPRG3
1148
1149#define GET_PACA(rX)					\
1150	BEGIN_FTR_SECTION_NESTED(66);			\
1151	mfspr	rX,SPRN_SPRG_PACA;			\
1152	FTR_SECTION_ELSE_NESTED(66);			\
1153	mfspr	rX,SPRN_SPRG_HPACA;			\
1154	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1155
1156#define SET_PACA(rX)					\
1157	BEGIN_FTR_SECTION_NESTED(66);			\
1158	mtspr	SPRN_SPRG_PACA,rX;			\
1159	FTR_SECTION_ELSE_NESTED(66);			\
1160	mtspr	SPRN_SPRG_HPACA,rX;			\
1161	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1162
1163#define GET_SCRATCH0(rX)				\
1164	BEGIN_FTR_SECTION_NESTED(66);			\
1165	mfspr	rX,SPRN_SPRG_SCRATCH0;			\
1166	FTR_SECTION_ELSE_NESTED(66);			\
1167	mfspr	rX,SPRN_SPRG_HSCRATCH0;			\
1168	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1169
1170#define SET_SCRATCH0(rX)				\
1171	BEGIN_FTR_SECTION_NESTED(66);			\
1172	mtspr	SPRN_SPRG_SCRATCH0,rX;			\
1173	FTR_SECTION_ELSE_NESTED(66);			\
1174	mtspr	SPRN_SPRG_HSCRATCH0,rX;			\
1175	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1176
1177#else /* CONFIG_PPC_BOOK3S_64 */
1178#define GET_SCRATCH0(rX)	mfspr	rX,SPRN_SPRG_SCRATCH0
1179#define SET_SCRATCH0(rX)	mtspr	SPRN_SPRG_SCRATCH0,rX
1180
1181#endif
1182
1183#ifdef CONFIG_PPC_BOOK3E_64
1184#define SPRN_SPRG_MC_SCRATCH	SPRN_SPRG8
1185#define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG3
1186#define SPRN_SPRG_DBG_SCRATCH	SPRN_SPRG9
1187#define SPRN_SPRG_TLB_EXFRAME	SPRN_SPRG2
1188#define SPRN_SPRG_TLB_SCRATCH	SPRN_SPRG6
1189#define SPRN_SPRG_GEN_SCRATCH	SPRN_SPRG0
1190#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1191#define SPRN_SPRG_VDSO_READ	SPRN_USPRG7
1192#define SPRN_SPRG_VDSO_WRITE	SPRN_SPRG7
1193
1194#define SET_PACA(rX)	mtspr	SPRN_SPRG_PACA,rX
1195#define GET_PACA(rX)	mfspr	rX,SPRN_SPRG_PACA
1196
1197#endif
1198
1199#ifdef CONFIG_PPC_BOOK3S_32
1200#define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
1201#define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
1202#define SPRN_SPRG_SCRATCH2	SPRN_SPRG2
1203#define SPRN_SPRG_603_LRU	SPRN_SPRG4
1204#endif
1205
1206#ifdef CONFIG_BOOKE
1207#define SPRN_SPRG_RSCRATCH0	SPRN_SPRG0
1208#define SPRN_SPRG_WSCRATCH0	SPRN_SPRG0
1209#define SPRN_SPRG_RSCRATCH1	SPRN_SPRG1
1210#define SPRN_SPRG_WSCRATCH1	SPRN_SPRG1
1211#define SPRN_SPRG_RSCRATCH_CRIT	SPRN_SPRG2
1212#define SPRN_SPRG_WSCRATCH_CRIT	SPRN_SPRG2
1213#define SPRN_SPRG_RSCRATCH2	SPRN_SPRG4R
1214#define SPRN_SPRG_WSCRATCH2	SPRN_SPRG4W
1215#define SPRN_SPRG_RSCRATCH3	SPRN_SPRG5R
1216#define SPRN_SPRG_WSCRATCH3	SPRN_SPRG5W
1217#define SPRN_SPRG_RSCRATCH_MC	SPRN_SPRG1
1218#define SPRN_SPRG_WSCRATCH_MC	SPRN_SPRG1
1219#define SPRN_SPRG_RSCRATCH4	SPRN_SPRG7R
1220#define SPRN_SPRG_WSCRATCH4	SPRN_SPRG7W
1221#define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG9
1222#define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG9
1223#endif
1224
1225#ifdef CONFIG_PPC_8xx
1226#define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
1227#define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
1228#define SPRN_SPRG_SCRATCH2	SPRN_SPRG2
1229#endif
1230
1231
1232
1233/*
1234 * An mtfsf instruction with the L bit set. On CPUs that support this a
1235 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
1236 *
1237 * Until binutils gets the new form of mtfsf, hardwire the instruction.
1238 */
1239#ifdef CONFIG_PPC64
1240#define MTFSF_L(REG) \
1241	.long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1242#else
1243#define MTFSF_L(REG)	mtfsf	0xff, (REG)
1244#endif
1245
1246/* Processor Version Register (PVR) field extraction */
1247
1248#define PVR_VER(pvr)	(((pvr) >>  16) & 0xFFFF)	/* Version field */
1249#define PVR_REV(pvr)	(((pvr) >>   0) & 0xFFFF)	/* Revison field */
1250
1251#define pvr_version_is(pvr)	(PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1252
1253/*
1254 * IBM has further subdivided the standard PowerPC 16-bit version and
1255 * revision subfields of the PVR for the PowerPC 403s into the following:
1256 */
1257
1258#define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
1259#define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
1260#define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
1261#define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
1262#define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
1263#define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
1264
1265/* Processor Version Numbers */
1266
1267#define PVR_403GA	0x00200000
1268#define PVR_403GB	0x00200100
1269#define PVR_403GC	0x00200200
1270#define PVR_403GCX	0x00201400
1271#define PVR_405GP	0x40110000
1272#define PVR_476		0x11a52000
1273#define PVR_476FPE	0x7ff50000
1274#define PVR_STB03XXX	0x40310000
1275#define PVR_NP405H	0x41410000
1276#define PVR_NP405L	0x41610000
1277#define PVR_601		0x00010000
1278#define PVR_602		0x00050000
1279#define PVR_603		0x00030000
1280#define PVR_603e	0x00060000
1281#define PVR_603ev	0x00070000
1282#define PVR_603r	0x00071000
1283#define PVR_604		0x00040000
1284#define PVR_604e	0x00090000
1285#define PVR_604r	0x000A0000
1286#define PVR_620		0x00140000
1287#define PVR_740		0x00080000
1288#define PVR_750		PVR_740
1289#define PVR_740P	0x10080000
1290#define PVR_750P	PVR_740P
1291#define PVR_7400	0x000C0000
1292#define PVR_7410	0x800C0000
1293#define PVR_7450	0x80000000
1294#define PVR_8540	0x80200000
1295#define PVR_8560	0x80200000
1296#define PVR_VER_E500V1	0x8020
1297#define PVR_VER_E500V2	0x8021
1298#define PVR_VER_E500MC	0x8023
1299#define PVR_VER_E5500	0x8024
1300#define PVR_VER_E6500	0x8040
1301#define PVR_VER_7450	0x8000
1302#define PVR_VER_7455	0x8001
1303#define PVR_VER_7447	0x8002
1304#define PVR_VER_7447A	0x8003
1305#define PVR_VER_7448	0x8004
1306
1307/*
1308 * For the 8xx processors, all of them report the same PVR family for
1309 * the PowerPC core. The various versions of these processors must be
1310 * differentiated by the version number in the Communication Processor
1311 * Module (CPM).
1312 */
1313#define PVR_8xx		0x00500000
1314
1315#define PVR_8240	0x00810100
1316#define PVR_8245	0x80811014
1317#define PVR_8260	PVR_8240
1318
1319/* 476 Simulator seems to currently have the PVR of the 602... */
1320#define PVR_476_ISS	0x00052000
1321
1322/* 64-bit processors */
1323#define PVR_NORTHSTAR	0x0033
1324#define PVR_PULSAR	0x0034
1325#define PVR_POWER4	0x0035
1326#define PVR_ICESTAR	0x0036
1327#define PVR_SSTAR	0x0037
1328#define PVR_POWER4p	0x0038
1329#define PVR_970		0x0039
1330#define PVR_POWER5	0x003A
1331#define PVR_POWER5p	0x003B
1332#define PVR_970FX	0x003C
1333#define PVR_POWER6	0x003E
1334#define PVR_POWER7	0x003F
1335#define PVR_630		0x0040
1336#define PVR_630p	0x0041
1337#define PVR_970MP	0x0044
1338#define PVR_970GX	0x0045
1339#define PVR_POWER7p	0x004A
1340#define PVR_POWER8E	0x004B
1341#define PVR_POWER8NVL	0x004C
1342#define PVR_POWER8	0x004D
1343#define PVR_HX_C2000	0x0066
1344#define PVR_POWER9	0x004E
1345#define PVR_POWER10	0x0080
1346#define PVR_POWER11	0x0082
1347#define PVR_BE		0x0070
1348#define PVR_PA6T	0x0090
1349
1350/* "Logical" PVR values defined in PAPR, representing architecture levels */
1351#define PVR_ARCH_204	0x0f000001
1352#define PVR_ARCH_205	0x0f000002
1353#define PVR_ARCH_206	0x0f000003
1354#define PVR_ARCH_206p	0x0f100003
1355#define PVR_ARCH_207	0x0f000004
1356#define PVR_ARCH_300	0x0f000005
1357#define PVR_ARCH_31	0x0f000006
1358#define PVR_ARCH_31_P11	0x0f000007
1359
1360/* Macros for setting and retrieving special purpose registers */
1361#ifndef __ASSEMBLER__
1362
1363#if defined(CONFIG_PPC64) || defined(__CHECKER__)
1364typedef struct {
1365	u32 val;
1366#ifdef CONFIG_PPC64
1367	u32 suffix;
1368#endif
1369} __packed ppc_inst_t;
1370#else
1371typedef u32 ppc_inst_t;
1372#endif
1373
1374#define mfmsr()		({unsigned long rval; \
1375			asm volatile("mfmsr %0" : "=r" (rval) : \
1376						: "memory"); rval;})
1377#ifdef CONFIG_PPC_BOOK3S_64
1378#define __mtmsrd(v, l)	asm volatile("mtmsrd %0," __stringify(l) \
1379				     : : "r" (v) : "memory")
1380#define mtmsr(v)	__mtmsrd((v), 0)
1381#define __MTMSR		"mtmsrd"
1382#else
1383#define mtmsr(v)	asm volatile("mtmsr %0" : \
1384				     : "r" ((unsigned long)(v)) \
1385				     : "memory")
1386#define __mtmsrd(v, l)	BUILD_BUG()
1387#define __MTMSR		"mtmsr"
1388#endif
1389
1390static inline void mtmsr_isync(unsigned long val)
1391{
1392	asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1393			"r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1394}
1395
1396#define mfspr(rn)	({unsigned long rval; \
1397			asm volatile("mfspr %0," __stringify(rn) \
1398				: "=r" (rval)); rval;})
1399#define mtspr(rn, v)	asm volatile("mtspr " __stringify(rn) ",%0" : \
1400				     : "r" ((unsigned long)(v)) \
1401				     : "memory")
1402#define wrtspr(rn)	asm volatile("mtspr " __stringify(rn) ",2" : : : "memory")
1403#define wrtspr_sync(rn)	asm volatile("mtspr " __stringify(rn) ",2; sync" : : : "memory")
1404
1405static inline void wrtee(unsigned long val)
1406{
1407	if (__builtin_constant_p(val))
1408		asm volatile("wrteei %0" : : "i" ((val & MSR_EE) ? 1 : 0) : "memory");
1409	else
1410		asm volatile("wrtee %0" : : "r" (val) : "memory");
1411}
1412
1413extern unsigned long msr_check_and_set(unsigned long bits);
1414extern bool strict_msr_control;
1415extern void __msr_check_and_clear(unsigned long bits);
1416static inline void msr_check_and_clear(unsigned long bits)
1417{
1418	if (strict_msr_control)
1419		__msr_check_and_clear(bits);
1420}
1421
1422#ifdef CONFIG_PPC32
1423static inline u32 mfsr(u32 idx)
1424{
1425	u32 val;
1426
1427	if (__builtin_constant_p(idx))
1428		asm volatile("mfsr %0, %1" : "=r" (val): "i" (idx >> 28));
1429	else
1430		asm volatile("mfsrin %0, %1" : "=r" (val): "r" (idx));
1431
1432	return val;
1433}
1434
1435static inline void mtsr(u32 val, u32 idx)
1436{
1437	if (__builtin_constant_p(idx))
1438		asm volatile("mtsr %1, %0" : : "r" (val), "i" (idx >> 28));
1439	else
1440		asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx));
1441}
1442#endif
1443
1444extern unsigned long current_stack_frame(void);
1445
1446register unsigned long current_stack_pointer asm("r1");
1447
1448extern unsigned long scom970_read(unsigned int address);
1449extern void scom970_write(unsigned int address, unsigned long value);
1450
1451struct pt_regs;
1452
1453extern void ppc_save_regs(struct pt_regs *regs);
1454#endif /* __ASSEMBLER__ */
1455#endif /* __KERNEL__ */
1456#endif /* _ASM_POWERPC_REG_H */