pgtable.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
   3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
   4
   5#include <asm-generic/pgtable-nop4d.h>
   6
   7#ifndef __ASSEMBLER__
   8#include <linux/mmdebug.h>
   9#include <linux/bug.h>
  10#include <linux/sizes.h>
  11#endif
  12
  13/*
  14 * Common bits between hash and Radix page table
  15 */
  16
  17#define _PAGE_EXEC		0x00001 /* execute permission */
  18#define _PAGE_WRITE		0x00002 /* write access allowed */
  19#define _PAGE_READ		0x00004	/* read access allowed */
  20#define _PAGE_PRIVILEGED	0x00008 /* kernel access only */
  21#define _PAGE_SAO		0x00010 /* Strong access order */
  22#define _PAGE_NON_IDEMPOTENT	0x00020 /* non idempotent memory */
  23#define _PAGE_TOLERANT		0x00030 /* tolerant memory, cache inhibited */
  24#define _PAGE_DIRTY		0x00080 /* C: page changed */
  25#define _PAGE_ACCESSED		0x00100 /* R: page referenced */
  26/*
  27 * Software bits
  28 */
  29#define _RPAGE_SW0		0x2000000000000000UL
  30#define _RPAGE_SW1		0x00800
  31#define _RPAGE_SW2		0x00400
  32#define _RPAGE_SW3		0x00200
  33#define _RPAGE_RSV1		0x00040UL
  34
  35#define _RPAGE_PKEY_BIT4	0x1000000000000000UL
  36#define _RPAGE_PKEY_BIT3	0x0800000000000000UL
  37#define _RPAGE_PKEY_BIT2	0x0400000000000000UL
  38#define _RPAGE_PKEY_BIT1	0x0200000000000000UL
  39#define _RPAGE_PKEY_BIT0	0x0100000000000000UL
  40
  41#define _PAGE_PTE		0x4000000000000000UL	/* distinguishes PTEs from pointers */
  42#define _PAGE_PRESENT		0x8000000000000000UL	/* pte contains a translation */
  43/*
  44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing
  45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to
  46 * differentiate between two use a SW field when invalidating.
  47 *
  48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags
  49 *
  50 * This is used only when _PAGE_PRESENT is cleared.
  51 */
  52#define _PAGE_INVALID		_RPAGE_SW0
  53
  54/*
  55 * Top and bottom bits of RPN which can be used by hash
  56 * translation mode, because we expect them to be zero
  57 * otherwise.
  58 */
  59#define _RPAGE_RPN0		0x01000
  60#define _RPAGE_RPN1		0x02000
  61#define _RPAGE_RPN43		0x0080000000000000UL
  62#define _RPAGE_RPN42		0x0040000000000000UL
  63#define _RPAGE_RPN41		0x0020000000000000UL
  64
  65/* Max physical address bit as per radix table */
  66#define _RPAGE_PA_MAX		56
  67
  68/*
  69 * Max physical address bit we will use for now.
  70 *
  71 * This is mostly a hardware limitation and for now Power9 has
  72 * a 51 bit limit.
  73 *
  74 * This is different from the number of physical bit required to address
  75 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
  76 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
  77 * number of sections we can support (SECTIONS_SHIFT).
  78 *
  79 * This is different from Radix page table limitation above and
  80 * should always be less than that. The limit is done such that
  81 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
  82 * for hash linux page table specific bits.
  83 *
  84 * In order to be compatible with future hardware generations we keep
  85 * some offsets and limit this for now to 53
  86 */
  87#define _PAGE_PA_MAX		53
  88
  89#define _PAGE_SOFT_DIRTY	_RPAGE_SW3 /* software: software dirty tracking */
  90#define _PAGE_SPECIAL		_RPAGE_SW2 /* software: special page */
  91
  92/*
  93 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
  94 * Instead of fixing all of them, add an alternate define which
  95 * maps CI pte mapping.
  96 */
  97#define _PAGE_NO_CACHE		_PAGE_TOLERANT
  98/*
  99 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
 100 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
 101 * and every thing below PAGE_SHIFT;
 102 */
 103#define PTE_RPN_MASK	(((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
 104#define PTE_RPN_SHIFT	PAGE_SHIFT
 105/*
 106 * set of bits not changed in pmd_modify. Even though we have hash specific bits
 107 * in here, on radix we expect them to be zero.
 108 */
 109#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
 110			 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
 111			 _PAGE_SOFT_DIRTY)
 112/*
 113 * user access blocked by key
 114 */
 115#define _PAGE_KERNEL_RW		(_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
 116#define _PAGE_KERNEL_RO		 (_PAGE_PRIVILEGED | _PAGE_READ)
 117#define _PAGE_KERNEL_ROX	 (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC)
 118#define _PAGE_KERNEL_RWX	(_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
 119/*
 120 * _PAGE_CHG_MASK masks of bits that are to be preserved across
 121 * pgprot changes
 122 */
 123#define _PAGE_CHG_MASK	(PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
 124			 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE |	\
 125			 _PAGE_SOFT_DIRTY)
 126
 127/*
 128 * We define 2 sets of base prot bits, one for basic pages (ie,
 129 * cacheable kernel and user pages) and one for non cacheable
 130 * pages. We always set _PAGE_COHERENT when SMP is enabled or
 131 * the processor might need it for DMA coherency.
 132 */
 133#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)
 134#define _PAGE_BASE	(_PAGE_BASE_NC)
 135
 136#include <asm/pgtable-masks.h>
 137
 138/* Permission masks used for kernel mappings */
 139#define PAGE_KERNEL	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
 140#define PAGE_KERNEL_NC	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT)
 141#define PAGE_KERNEL_NCG	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT)
 142#define PAGE_KERNEL_X	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
 143#define PAGE_KERNEL_RO	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
 144#define PAGE_KERNEL_ROX	__pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
 145
 146#ifndef __ASSEMBLER__
 147/*
 148 * page table defines
 149 */
 150extern unsigned long __pte_index_size;
 151extern unsigned long __pmd_index_size;
 152extern unsigned long __pud_index_size;
 153extern unsigned long __pgd_index_size;
 154extern unsigned long __pud_cache_index;
 155#define PTE_INDEX_SIZE  __pte_index_size
 156#define PMD_INDEX_SIZE  __pmd_index_size
 157#define PUD_INDEX_SIZE  __pud_index_size
 158#define PGD_INDEX_SIZE  __pgd_index_size
 159/* pmd table use page table fragments */
 160#define PMD_CACHE_INDEX  0
 161#define PUD_CACHE_INDEX __pud_cache_index
 162/*
 163 * Because of use of pte fragments and THP, size of page table
 164 * are not always derived out of index size above.
 165 */
 166extern unsigned long __pte_table_size;
 167extern unsigned long __pmd_table_size;
 168extern unsigned long __pud_table_size;
 169extern unsigned long __pgd_table_size;
 170#define PTE_TABLE_SIZE	__pte_table_size
 171#define PMD_TABLE_SIZE	__pmd_table_size
 172#define PUD_TABLE_SIZE	__pud_table_size
 173#define PGD_TABLE_SIZE	__pgd_table_size
 174
 175extern unsigned long __pmd_val_bits;
 176extern unsigned long __pud_val_bits;
 177extern unsigned long __pgd_val_bits;
 178#define PMD_VAL_BITS	__pmd_val_bits
 179#define PUD_VAL_BITS	__pud_val_bits
 180#define PGD_VAL_BITS	__pgd_val_bits
 181
 182extern unsigned long __pte_frag_nr;
 183#define PTE_FRAG_NR __pte_frag_nr
 184extern unsigned long __pte_frag_size_shift;
 185#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
 186#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
 187
 188extern unsigned long __pmd_frag_nr;
 189#define PMD_FRAG_NR __pmd_frag_nr
 190extern unsigned long __pmd_frag_size_shift;
 191#define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
 192#define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
 193
 194#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
 195#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
 196#define PTRS_PER_PUD	(1 << PUD_INDEX_SIZE)
 197#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)
 198
 199#define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE)
 200#define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD)
 201#define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD)
 202#define MAX_PTRS_PER_PGD	(1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \
 203				       H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE))
 204
 205/* PMD_SHIFT determines what a second-level page table entry can map */
 206#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
 207#define PMD_SIZE	(1UL << PMD_SHIFT)
 208#define PMD_MASK	(~(PMD_SIZE-1))
 209
 210/* PUD_SHIFT determines what a third-level page table entry can map */
 211#define PUD_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
 212#define PUD_SIZE	(1UL << PUD_SHIFT)
 213#define PUD_MASK	(~(PUD_SIZE-1))
 214
 215/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
 216#define PGDIR_SHIFT	(PUD_SHIFT + PUD_INDEX_SIZE)
 217#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 218#define PGDIR_MASK	(~(PGDIR_SIZE-1))
 219
 220/* Bits to mask out from a PMD to get to the PTE page */
 221#define PMD_MASKED_BITS		0xc0000000000000ffUL
 222/* Bits to mask out from a PUD to get to the PMD page */
 223#define PUD_MASKED_BITS		0xc0000000000000ffUL
 224/* Bits to mask out from a PGD to get to the PUD page */
 225#define P4D_MASKED_BITS		0xc0000000000000ffUL
 226
 227/*
 228 * Used as an indicator for rcu callback functions
 229 */
 230enum pgtable_index {
 231	PTE_INDEX = 0,
 232	PMD_INDEX,
 233	PUD_INDEX,
 234	PGD_INDEX,
 235	/*
 236	 * Below are used with 4k page size and hugetlb
 237	 */
 238	HTLB_16M_INDEX,
 239	HTLB_16G_INDEX,
 240};
 241
 242extern unsigned long __vmalloc_start;
 243extern unsigned long __vmalloc_end;
 244#define VMALLOC_START	__vmalloc_start
 245#define VMALLOC_END	__vmalloc_end
 246
 247static inline unsigned int ioremap_max_order(void)
 248{
 249	if (radix_enabled())
 250		return PUD_SHIFT;
 251	return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */
 252}
 253#define IOREMAP_MAX_ORDER ioremap_max_order()
 254
 255extern unsigned long __kernel_virt_start;
 256extern unsigned long __kernel_io_start;
 257extern unsigned long __kernel_io_end;
 258#define KERN_VIRT_START __kernel_virt_start
 259#define KERN_IO_START  __kernel_io_start
 260#define KERN_IO_END __kernel_io_end
 261
 262extern struct page *vmemmap;
 263extern unsigned long pci_io_base;
 264
 265#define pmd_leaf pmd_leaf
 266static inline bool pmd_leaf(pmd_t pmd)
 267{
 268	return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
 269}
 270
 271#define pud_leaf pud_leaf
 272static inline bool pud_leaf(pud_t pud)
 273{
 274	return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
 275}
 276
 277#define pmd_leaf_size pmd_leaf_size
 278static inline unsigned long pmd_leaf_size(pmd_t pmd)
 279{
 280	if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled())
 281		return SZ_16M;
 282	else
 283		return PMD_SIZE;
 284}
 285
 286#define pud_leaf_size pud_leaf_size
 287static inline unsigned long pud_leaf_size(pud_t pud)
 288{
 289	if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled())
 290		return SZ_16G;
 291	else
 292		return PUD_SIZE;
 293}
 294#endif /* __ASSEMBLER__ */
 295
 296#include <asm/book3s/64/hash.h>
 297#include <asm/book3s/64/radix.h>
 298
 299#if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS
 300#define  MAX_PHYSMEM_BITS	H_MAX_PHYSMEM_BITS
 301#else
 302#define  MAX_PHYSMEM_BITS	R_MAX_PHYSMEM_BITS
 303#endif
 304
 305/* hash 4k can't share hugetlb and also doesn't support THP */
 306#ifdef CONFIG_PPC_64K_PAGES
 307#include <asm/book3s/64/pgtable-64k.h>
 308#endif
 309
 310#include <asm/barrier.h>
 311/*
 312 * IO space itself carved into the PIO region (ISA and PHB IO space) and
 313 * the ioremap space
 314 *
 315 *  ISA_IO_BASE = KERN_IO_START, 64K reserved area
 316 *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
 317 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
 318 */
 319#define FULL_IO_SIZE	0x80000000ul
 320#define  ISA_IO_BASE	(KERN_IO_START)
 321#define  ISA_IO_END	(KERN_IO_START + 0x10000ul)
 322#define  PHB_IO_BASE	(ISA_IO_END)
 323#define  PHB_IO_END	(KERN_IO_START + FULL_IO_SIZE)
 324#define IOREMAP_BASE	(PHB_IO_END)
 325#define IOREMAP_START	(ioremap_bot)
 326#define IOREMAP_END	(KERN_IO_END - FIXADDR_SIZE)
 327#define FIXADDR_SIZE	SZ_32M
 328#define FIXADDR_TOP	(IOREMAP_END + FIXADDR_SIZE)
 329
 330#ifndef __ASSEMBLER__
 331
 332static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
 333				       pte_t *ptep, unsigned long clr,
 334				       unsigned long set, int huge)
 335{
 336	if (radix_enabled())
 337		return radix__pte_update(mm, addr, ptep, clr, set, huge);
 338	return hash__pte_update(mm, addr, ptep, clr, set, huge);
 339}
 340/*
 341 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
 342 * We currently remove entries from the hashtable regardless of whether
 343 * the entry was young or dirty.
 344 *
 345 * We should be more intelligent about this but for the moment we override
 346 * these functions and force a tlb flush unconditionally
 347 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
 348 * function for both hash and radix.
 349 */
 350static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 351					      unsigned long addr, pte_t *ptep)
 352{
 353	unsigned long old;
 354
 355	if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
 356		return 0;
 357	old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
 358	return (old & _PAGE_ACCESSED) != 0;
 359}
 360
 361#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 362#define ptep_test_and_clear_young(__vma, __addr, __ptep)	\
 363({								\
 364	__ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
 365})
 366
 367/*
 368 * On Book3S CPUs, clearing the accessed bit without a TLB flush
 369 * doesn't cause data corruption. [ It could cause incorrect
 370 * page aging and the (mistaken) reclaim of hot pages, but the
 371 * chance of that should be relatively low. ]
 372 *
 373 * So as a performance optimization don't flush the TLB when
 374 * clearing the accessed bit, it will eventually be flushed by
 375 * a context switch or a VM operation anyway. [ In the rare
 376 * event of it not getting flushed for a long time the delay
 377 * shouldn't really matter because there's no real memory
 378 * pressure for swapout to react to. ]
 379 *
 380 * Note: this optimisation also exists in pte_needs_flush() and
 381 * huge_pmd_needs_flush().
 382 */
 383#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 384#define ptep_clear_flush_young ptep_test_and_clear_young
 385
 386#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
 387#define pmdp_clear_flush_young pmdp_test_and_clear_young
 388
 389static inline int pte_write(pte_t pte)
 390{
 391	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
 392}
 393
 394static inline int pte_read(pte_t pte)
 395{
 396	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
 397}
 398
 399#define __HAVE_ARCH_PTEP_SET_WRPROTECT
 400static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 401				      pte_t *ptep)
 402{
 403	if (pte_write(*ptep))
 404		pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
 405}
 406
 407#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
 408static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 409					   unsigned long addr, pte_t *ptep)
 410{
 411	if (pte_write(*ptep))
 412		pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
 413}
 414
 415#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 416static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 417				       unsigned long addr, pte_t *ptep)
 418{
 419	unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
 420	return __pte(old);
 421}
 422
 423#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 424static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
 425					    unsigned long addr,
 426					    pte_t *ptep, int full)
 427{
 428	if (full && radix_enabled()) {
 429		/*
 430		 * We know that this is a full mm pte clear and
 431		 * hence can be sure there is no parallel set_pte.
 432		 */
 433		return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
 434	}
 435	return ptep_get_and_clear(mm, addr, ptep);
 436}
 437
 438
 439static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 440			     pte_t * ptep)
 441{
 442	pte_update(mm, addr, ptep, ~0UL, 0, 0);
 443}
 444
 445static inline int pte_dirty(pte_t pte)
 446{
 447	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
 448}
 449
 450static inline int pte_young(pte_t pte)
 451{
 452	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
 453}
 454
 455static inline int pte_special(pte_t pte)
 456{
 457	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
 458}
 459
 460static inline bool pte_exec(pte_t pte)
 461{
 462	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC));
 463}
 464
 465
 466#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
 467static inline bool pte_soft_dirty(pte_t pte)
 468{
 469	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
 470}
 471
 472static inline pte_t pte_mksoft_dirty(pte_t pte)
 473{
 474	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY));
 475}
 476
 477static inline pte_t pte_clear_soft_dirty(pte_t pte)
 478{
 479	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY));
 480}
 481#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
 482
 483#ifdef CONFIG_NUMA_BALANCING
 484static inline int pte_protnone(pte_t pte)
 485{
 486	return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
 487		cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
 488}
 489#endif /* CONFIG_NUMA_BALANCING */
 490
 491static inline bool pte_hw_valid(pte_t pte)
 492{
 493	return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) ==
 494		cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
 495}
 496
 497static inline int pte_present(pte_t pte)
 498{
 499	/*
 500	 * A pte is considerent present if _PAGE_PRESENT is set.
 501	 * We also need to consider the pte present which is marked
 502	 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID
 503	 * if we find _PAGE_PRESENT cleared.
 504	 */
 505
 506	if (pte_hw_valid(pte))
 507		return true;
 508	return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) ==
 509		cpu_to_be64(_PAGE_INVALID | _PAGE_PTE);
 510}
 511
 512#ifdef CONFIG_PPC_MEM_KEYS
 513extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
 514#else
 515static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
 516{
 517	return true;
 518}
 519#endif /* CONFIG_PPC_MEM_KEYS */
 520
 521static inline bool pte_user(pte_t pte)
 522{
 523	return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
 524}
 525
 526#define pte_access_permitted pte_access_permitted
 527static inline bool pte_access_permitted(pte_t pte, bool write)
 528{
 529	/*
 530	 * _PAGE_READ is needed for any access and will be cleared for
 531	 * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false.
 532	 */
 533	if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
 534		return false;
 535
 536	if (write && !pte_write(pte))
 537		return false;
 538
 539	return arch_pte_access_permitted(pte_val(pte), write, 0);
 540}
 541
 542/*
 543 * Conversion functions: convert a page and protection to a page entry,
 544 * and a page entry and page directory to the page they refer to.
 545 *
 546 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
 547 * long for now.
 548 */
 549static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 550{
 551	VM_BUG_ON(pfn >> (64 - PAGE_SHIFT));
 552	VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK);
 553
 554	return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE);
 555}
 556
 557/* Generic modifiers for PTE bits */
 558static inline pte_t pte_wrprotect(pte_t pte)
 559{
 560	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE));
 561}
 562
 563static inline pte_t pte_exprotect(pte_t pte)
 564{
 565	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC));
 566}
 567
 568static inline pte_t pte_mkclean(pte_t pte)
 569{
 570	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY));
 571}
 572
 573static inline pte_t pte_mkold(pte_t pte)
 574{
 575	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED));
 576}
 577
 578static inline pte_t pte_mkexec(pte_t pte)
 579{
 580	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC));
 581}
 582
 583static inline pte_t pte_mkwrite_novma(pte_t pte)
 584{
 585	/*
 586	 * write implies read, hence set both
 587	 */
 588	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW));
 589}
 590
 591static inline pte_t pte_mkdirty(pte_t pte)
 592{
 593	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
 594}
 595
 596static inline pte_t pte_mkyoung(pte_t pte)
 597{
 598	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED));
 599}
 600
 601static inline pte_t pte_mkspecial(pte_t pte)
 602{
 603	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL));
 604}
 605
 606static inline pte_t pte_mkhuge(pte_t pte)
 607{
 608	return pte;
 609}
 610
 611static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 612{
 613	/* FIXME!! check whether this need to be a conditional */
 614	return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) |
 615			 cpu_to_be64(pgprot_val(newprot)));
 616}
 617
 618/* Encode and de-code a swap entry */
 619#define MAX_SWAPFILES_CHECK() do { \
 620	BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
 621	/*							\
 622	 * Don't have overlapping bits with _PAGE_HPTEFLAGS	\
 623	 * We filter HPTEFLAGS on set_pte.			\
 624	 */							\
 625	BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \
 626	BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY);	\
 627	BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE);	\
 628	} while (0)
 629
 630#define SWP_TYPE_BITS 5
 631#define SWP_TYPE_MASK		((1UL << SWP_TYPE_BITS) - 1)
 632#define __swp_type(x)		((x).val & SWP_TYPE_MASK)
 633#define __swp_offset(x)		(((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
 634#define __swp_entry(type, offset)	((swp_entry_t) { \
 635				(type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
 636/*
 637 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
 638 * swap type and offset we get from swap and convert that to pte to find a
 639 * matching pte in linux page table.
 640 * Clear bits not found in swap entries here.
 641 */
 642#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
 643#define __swp_entry_to_pte(x)	__pte((x).val | _PAGE_PTE)
 644#define __pmd_to_swp_entry(pmd)	(__pte_to_swp_entry(pmd_pte(pmd)))
 645#define __swp_entry_to_pmd(x)	(pte_pmd(__swp_entry_to_pte(x)))
 646
 647#ifdef CONFIG_MEM_SOFT_DIRTY
 648#define _PAGE_SWP_SOFT_DIRTY	_PAGE_SOFT_DIRTY
 649#else
 650#define _PAGE_SWP_SOFT_DIRTY	0UL
 651#endif /* CONFIG_MEM_SOFT_DIRTY */
 652
 653#define _PAGE_SWP_EXCLUSIVE	_PAGE_NON_IDEMPOTENT
 654
 655#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
 656static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
 657{
 658	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
 659}
 660
 661static inline bool pte_swp_soft_dirty(pte_t pte)
 662{
 663	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
 664}
 665
 666static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
 667{
 668	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY));
 669}
 670#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
 671
 672static inline pte_t pte_swp_mkexclusive(pte_t pte)
 673{
 674	return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
 675}
 676
 677static inline bool pte_swp_exclusive(pte_t pte)
 678{
 679	return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
 680}
 681
 682static inline pte_t pte_swp_clear_exclusive(pte_t pte)
 683{
 684	return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE));
 685}
 686
 687static inline bool check_pte_access(unsigned long access, unsigned long ptev)
 688{
 689	/*
 690	 * This check for _PAGE_RWX and _PAGE_PRESENT bits
 691	 */
 692	if (access & ~ptev)
 693		return false;
 694	/*
 695	 * This check for access to privilege space
 696	 */
 697	if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
 698		return false;
 699
 700	return true;
 701}
 702/*
 703 * Generic functions with hash/radix callbacks
 704 */
 705
 706static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
 707					   pte_t *ptep, pte_t entry,
 708					   unsigned long address,
 709					   int psize)
 710{
 711	if (radix_enabled())
 712		return radix__ptep_set_access_flags(vma, ptep, entry,
 713						    address, psize);
 714	return hash__ptep_set_access_flags(ptep, entry);
 715}
 716
 717#define __HAVE_ARCH_PTE_SAME
 718static inline int pte_same(pte_t pte_a, pte_t pte_b)
 719{
 720	if (radix_enabled())
 721		return radix__pte_same(pte_a, pte_b);
 722	return hash__pte_same(pte_a, pte_b);
 723}
 724
 725static inline int pte_none(pte_t pte)
 726{
 727	if (radix_enabled())
 728		return radix__pte_none(pte);
 729	return hash__pte_none(pte);
 730}
 731
 732static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 733				pte_t *ptep, pte_t pte, int percpu)
 734{
 735
 736	VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE)));
 737	/*
 738	 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE
 739	 * in all the callers.
 740	 */
 741	pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE));
 742
 743	if (radix_enabled())
 744		return radix__set_pte_at(mm, addr, ptep, pte, percpu);
 745	return hash__set_pte_at(mm, addr, ptep, pte, percpu);
 746}
 747
 748#define _PAGE_CACHE_CTL	(_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
 749
 750#define pgprot_noncached pgprot_noncached
 751static inline pgprot_t pgprot_noncached(pgprot_t prot)
 752{
 753	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 754			_PAGE_NON_IDEMPOTENT);
 755}
 756
 757#define pgprot_noncached_wc pgprot_noncached_wc
 758static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
 759{
 760	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 761			_PAGE_TOLERANT);
 762}
 763
 764#define pgprot_cached pgprot_cached
 765static inline pgprot_t pgprot_cached(pgprot_t prot)
 766{
 767	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
 768}
 769
 770#define pgprot_writecombine pgprot_writecombine
 771static inline pgprot_t pgprot_writecombine(pgprot_t prot)
 772{
 773	return pgprot_noncached_wc(prot);
 774}
 775/*
 776 * check a pte mapping have cache inhibited property
 777 */
 778static inline bool pte_ci(pte_t pte)
 779{
 780	__be64 pte_v = pte_raw(pte);
 781
 782	if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) ||
 783	    ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT)))
 784		return true;
 785	return false;
 786}
 787
 788static inline void pmd_clear(pmd_t *pmdp)
 789{
 790	if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
 791		/*
 792		 * Don't use this if we can possibly have a hash page table
 793		 * entry mapping this.
 794		 */
 795		WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
 796	}
 797	*pmdp = __pmd(0);
 798}
 799
 800static inline int pmd_none(pmd_t pmd)
 801{
 802	return !pmd_raw(pmd);
 803}
 804
 805static inline int pmd_present(pmd_t pmd)
 806{
 807	/*
 808	 * A pmd is considerent present if _PAGE_PRESENT is set.
 809	 * We also need to consider the pmd present which is marked
 810	 * invalid during a split. Hence we look for _PAGE_INVALID
 811	 * if we find _PAGE_PRESENT cleared.
 812	 */
 813	if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID))
 814		return true;
 815
 816	return false;
 817}
 818
 819static inline int pmd_is_serializing(pmd_t pmd)
 820{
 821	/*
 822	 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear
 823	 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate).
 824	 *
 825	 * This condition may also occur when flushing a pmd while flushing
 826	 * it (see ptep_modify_prot_start), so callers must ensure this
 827	 * case is fine as well.
 828	 */
 829	if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) ==
 830						cpu_to_be64(_PAGE_INVALID))
 831		return true;
 832
 833	return false;
 834}
 835
 836static inline int pmd_bad(pmd_t pmd)
 837{
 838	if (radix_enabled())
 839		return radix__pmd_bad(pmd);
 840	return hash__pmd_bad(pmd);
 841}
 842
 843static inline void pud_clear(pud_t *pudp)
 844{
 845	if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
 846		/*
 847		 * Don't use this if we can possibly have a hash page table
 848		 * entry mapping this.
 849		 */
 850		WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
 851	}
 852	*pudp = __pud(0);
 853}
 854
 855static inline int pud_none(pud_t pud)
 856{
 857	return !pud_raw(pud);
 858}
 859
 860static inline int pud_present(pud_t pud)
 861{
 862	return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
 863}
 864
 865extern struct page *pud_page(pud_t pud);
 866extern struct page *pmd_page(pmd_t pmd);
 867static inline pte_t pud_pte(pud_t pud)
 868{
 869	return __pte_raw(pud_raw(pud));
 870}
 871
 872static inline pud_t pte_pud(pte_t pte)
 873{
 874	return __pud_raw(pte_raw(pte));
 875}
 876
 877static inline pte_t *pudp_ptep(pud_t *pud)
 878{
 879	return (pte_t *)pud;
 880}
 881
 882#define pud_pfn(pud)		pte_pfn(pud_pte(pud))
 883#define pud_dirty(pud)		pte_dirty(pud_pte(pud))
 884#define pud_young(pud)		pte_young(pud_pte(pud))
 885#define pud_mkold(pud)		pte_pud(pte_mkold(pud_pte(pud)))
 886#define pud_wrprotect(pud)	pte_pud(pte_wrprotect(pud_pte(pud)))
 887#define pud_mkdirty(pud)	pte_pud(pte_mkdirty(pud_pte(pud)))
 888#define pud_mkclean(pud)	pte_pud(pte_mkclean(pud_pte(pud)))
 889#define pud_mkyoung(pud)	pte_pud(pte_mkyoung(pud_pte(pud)))
 890#define pud_mkwrite(pud)	pte_pud(pte_mkwrite_novma(pud_pte(pud)))
 891#define pud_write(pud)		pte_write(pud_pte(pud))
 892
 893#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
 894#define pud_soft_dirty(pmd)    pte_soft_dirty(pud_pte(pud))
 895#define pud_mksoft_dirty(pmd)  pte_pud(pte_mksoft_dirty(pud_pte(pud)))
 896#define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud)))
 897#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
 898
 899static inline int pud_bad(pud_t pud)
 900{
 901	if (radix_enabled())
 902		return radix__pud_bad(pud);
 903	return hash__pud_bad(pud);
 904}
 905
 906#define pud_access_permitted pud_access_permitted
 907static inline bool pud_access_permitted(pud_t pud, bool write)
 908{
 909	return pte_access_permitted(pud_pte(pud), write);
 910}
 911
 912#define __p4d_raw(x)	((p4d_t) { __pgd_raw(x) })
 913static inline __be64 p4d_raw(p4d_t x)
 914{
 915	return pgd_raw(x.pgd);
 916}
 917
 918#define p4d_write(p4d)		pte_write(p4d_pte(p4d))
 919
 920static inline void p4d_clear(p4d_t *p4dp)
 921{
 922	*p4dp = __p4d(0);
 923}
 924
 925static inline int p4d_none(p4d_t p4d)
 926{
 927	return !p4d_raw(p4d);
 928}
 929
 930static inline int p4d_present(p4d_t p4d)
 931{
 932	return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT));
 933}
 934
 935static inline pte_t p4d_pte(p4d_t p4d)
 936{
 937	return __pte_raw(p4d_raw(p4d));
 938}
 939
 940static inline p4d_t pte_p4d(pte_t pte)
 941{
 942	return __p4d_raw(pte_raw(pte));
 943}
 944
 945static inline int p4d_bad(p4d_t p4d)
 946{
 947	if (radix_enabled())
 948		return radix__p4d_bad(p4d);
 949	return hash__p4d_bad(p4d);
 950}
 951
 952#define p4d_access_permitted p4d_access_permitted
 953static inline bool p4d_access_permitted(p4d_t p4d, bool write)
 954{
 955	return pte_access_permitted(p4d_pte(p4d), write);
 956}
 957
 958extern struct page *p4d_page(p4d_t p4d);
 959
 960/* Pointers in the page table tree are physical addresses */
 961#define __pgtable_ptr_val(ptr)	__pa(ptr)
 962
 963static inline pud_t *p4d_pgtable(p4d_t p4d)
 964{
 965	return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS);
 966}
 967
 968static inline pmd_t *pud_pgtable(pud_t pud)
 969{
 970	return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS);
 971}
 972
 973#define pmd_ERROR(e) \
 974	pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 975#define pud_ERROR(e) \
 976	pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
 977#define pgd_ERROR(e) \
 978	pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 979
 980static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
 981{
 982	if (radix_enabled()) {
 983#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
 984		unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
 985		WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
 986#endif
 987		return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE);
 988	}
 989	return hash__map_kernel_page(ea, pa, prot);
 990}
 991
 992void unmap_kernel_page(unsigned long va);
 993
 994static inline int __meminit vmemmap_create_mapping(unsigned long start,
 995						   unsigned long page_size,
 996						   unsigned long phys)
 997{
 998	if (radix_enabled())
 999		return radix__vmemmap_create_mapping(start, page_size, phys);
1000	return hash__vmemmap_create_mapping(start, page_size, phys);
1001}
1002
1003#ifdef CONFIG_MEMORY_HOTPLUG
1004static inline void vmemmap_remove_mapping(unsigned long start,
1005					  unsigned long page_size)
1006{
1007	if (radix_enabled())
1008		return radix__vmemmap_remove_mapping(start, page_size);
1009	return hash__vmemmap_remove_mapping(start, page_size);
1010}
1011#endif
1012
1013static inline pte_t pmd_pte(pmd_t pmd)
1014{
1015	return __pte_raw(pmd_raw(pmd));
1016}
1017
1018static inline pmd_t pte_pmd(pte_t pte)
1019{
1020	return __pmd_raw(pte_raw(pte));
1021}
1022
1023static inline pte_t *pmdp_ptep(pmd_t *pmd)
1024{
1025	return (pte_t *)pmd;
1026}
1027#define pmd_pfn(pmd)		pte_pfn(pmd_pte(pmd))
1028#define pmd_dirty(pmd)		pte_dirty(pmd_pte(pmd))
1029#define pmd_young(pmd)		pte_young(pmd_pte(pmd))
1030#define pmd_mkold(pmd)		pte_pmd(pte_mkold(pmd_pte(pmd)))
1031#define pmd_wrprotect(pmd)	pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1032#define pmd_mkdirty(pmd)	pte_pmd(pte_mkdirty(pmd_pte(pmd)))
1033#define pmd_mkclean(pmd)	pte_pmd(pte_mkclean(pmd_pte(pmd)))
1034#define pmd_mkyoung(pmd)	pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1035#define pmd_mkwrite_novma(pmd)	pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
1036
1037#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1038#define pmd_soft_dirty(pmd)    pte_soft_dirty(pmd_pte(pmd))
1039#define pmd_mksoft_dirty(pmd)  pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1040#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1041
1042#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1043#define pmd_swp_mksoft_dirty(pmd)	pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)))
1044#define pmd_swp_soft_dirty(pmd)		pte_swp_soft_dirty(pmd_pte(pmd))
1045#define pmd_swp_clear_soft_dirty(pmd)	pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)))
1046#endif
1047#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1048
1049#ifdef CONFIG_NUMA_BALANCING
1050static inline int pmd_protnone(pmd_t pmd)
1051{
1052	return pte_protnone(pmd_pte(pmd));
1053}
1054#endif /* CONFIG_NUMA_BALANCING */
1055
1056#define pmd_write(pmd)		pte_write(pmd_pte(pmd))
1057
1058#define pmd_access_permitted pmd_access_permitted
1059static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1060{
1061	/*
1062	 * pmdp_invalidate sets this combination (which is not caught by
1063	 * !pte_present() check in pte_access_permitted), to prevent
1064	 * lock-free lookups, as part of the serialize_against_pte_lookup()
1065	 * synchronisation.
1066	 *
1067	 * This also catches the case where the PTE's hardware PRESENT bit is
1068	 * cleared while TLB is flushed, which is suboptimal but should not
1069	 * be frequent.
1070	 */
1071	if (pmd_is_serializing(pmd))
1072		return false;
1073
1074	return pte_access_permitted(pmd_pte(pmd), write);
1075}
1076
1077#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1078extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1079extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot);
1080extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1081extern pud_t pud_modify(pud_t pud, pgprot_t newprot);
1082extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1083		       pmd_t *pmdp, pmd_t pmd);
1084extern void set_pud_at(struct mm_struct *mm, unsigned long addr,
1085		       pud_t *pudp, pud_t pud);
1086
1087static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
1088					unsigned long addr, pmd_t *pmd)
1089{
1090}
1091
1092static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
1093					unsigned long addr, pud_t *pud)
1094{
1095}
1096
1097extern int hash__has_transparent_hugepage(void);
1098static inline int has_transparent_hugepage(void)
1099{
1100	if (radix_enabled())
1101		return radix__has_transparent_hugepage();
1102	return hash__has_transparent_hugepage();
1103}
1104#define has_transparent_hugepage has_transparent_hugepage
1105
1106static inline int has_transparent_pud_hugepage(void)
1107{
1108	if (radix_enabled())
1109		return radix__has_transparent_pud_hugepage();
1110	return 0;
1111}
1112#define has_transparent_pud_hugepage has_transparent_pud_hugepage
1113
1114static inline unsigned long
1115pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1116		    unsigned long clr, unsigned long set)
1117{
1118	if (radix_enabled())
1119		return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1120	return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1121}
1122
1123static inline unsigned long
1124pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp,
1125		    unsigned long clr, unsigned long set)
1126{
1127	if (radix_enabled())
1128		return radix__pud_hugepage_update(mm, addr, pudp, clr, set);
1129	BUG();
1130	return pud_val(*pudp);
1131}
1132
1133/*
1134 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1135 * the below will work for radix too
1136 */
1137static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1138					      unsigned long addr, pmd_t *pmdp)
1139{
1140	unsigned long old;
1141
1142	if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1143		return 0;
1144	old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1145	return ((old & _PAGE_ACCESSED) != 0);
1146}
1147
1148static inline int __pudp_test_and_clear_young(struct mm_struct *mm,
1149					      unsigned long addr, pud_t *pudp)
1150{
1151	unsigned long old;
1152
1153	if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1154		return 0;
1155	old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0);
1156	return ((old & _PAGE_ACCESSED) != 0);
1157}
1158
1159#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1160static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1161				      pmd_t *pmdp)
1162{
1163	if (pmd_write(*pmdp))
1164		pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1165}
1166
1167#define __HAVE_ARCH_PUDP_SET_WRPROTECT
1168static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1169				      pud_t *pudp)
1170{
1171	if (pud_write(*pudp))
1172		pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0);
1173}
1174
1175/*
1176 * Only returns true for a THP. False for pmd migration entry.
1177 * We also need to return true when we come across a pte that
1178 * in between a thp split. While splitting THP, we mark the pmd
1179 * invalid (pmdp_invalidate()) before we set it with pte page
1180 * address. A pmd_trans_huge() check against a pmd entry during that time
1181 * should return true.
1182 * We should not call this on a hugetlb entry. We should check for HugeTLB
1183 * entry using vma->vm_flags
1184 * The page table walk rule is explained in Documentation/mm/transhuge.rst
1185 */
1186static inline int pmd_trans_huge(pmd_t pmd)
1187{
1188	if (!pmd_present(pmd))
1189		return false;
1190
1191	if (radix_enabled())
1192		return radix__pmd_trans_huge(pmd);
1193	return hash__pmd_trans_huge(pmd);
1194}
1195
1196static inline int pud_trans_huge(pud_t pud)
1197{
1198	if (!pud_present(pud))
1199		return false;
1200
1201	if (radix_enabled())
1202		return radix__pud_trans_huge(pud);
1203	return 0;
1204}
1205
1206
1207#define __HAVE_ARCH_PMD_SAME
1208static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1209{
1210	if (radix_enabled())
1211		return radix__pmd_same(pmd_a, pmd_b);
1212	return hash__pmd_same(pmd_a, pmd_b);
1213}
1214
1215#define pud_same pud_same
1216static inline int pud_same(pud_t pud_a, pud_t pud_b)
1217{
1218	if (radix_enabled())
1219		return radix__pud_same(pud_a, pud_b);
1220	return hash__pud_same(pud_a, pud_b);
1221}
1222
1223
1224static inline pmd_t __pmd_mkhuge(pmd_t pmd)
1225{
1226	if (radix_enabled())
1227		return radix__pmd_mkhuge(pmd);
1228	return hash__pmd_mkhuge(pmd);
1229}
1230
1231static inline pud_t __pud_mkhuge(pud_t pud)
1232{
1233	if (radix_enabled())
1234		return radix__pud_mkhuge(pud);
1235	BUG();
1236	return pud;
1237}
1238
1239/*
1240 * pfn_pmd return a pmd_t that can be used as pmd pte entry.
1241 */
1242static inline pmd_t pmd_mkhuge(pmd_t pmd)
1243{
1244#ifdef CONFIG_DEBUG_VM
1245	if (radix_enabled())
1246		WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0);
1247	else
1248		WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) !=
1249			cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE));
1250#endif
1251	return pmd;
1252}
1253
1254static inline pud_t pud_mkhuge(pud_t pud)
1255{
1256#ifdef CONFIG_DEBUG_VM
1257	if (radix_enabled())
1258		WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0);
1259	else
1260		WARN_ON(1);
1261#endif
1262	return pud;
1263}
1264
1265
1266#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1267extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1268				 unsigned long address, pmd_t *pmdp,
1269				 pmd_t entry, int dirty);
1270#define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS
1271extern int pudp_set_access_flags(struct vm_area_struct *vma,
1272				 unsigned long address, pud_t *pudp,
1273				 pud_t entry, int dirty);
1274
1275#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1276extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1277				     unsigned long address, pmd_t *pmdp);
1278#define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG
1279extern int pudp_test_and_clear_young(struct vm_area_struct *vma,
1280				     unsigned long address, pud_t *pudp);
1281
1282
1283#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1284static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1285					    unsigned long addr, pmd_t *pmdp)
1286{
1287	if (radix_enabled())
1288		return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
1289	return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1290}
1291
1292#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
1293static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
1294					    unsigned long addr, pud_t *pudp)
1295{
1296	if (radix_enabled())
1297		return radix__pudp_huge_get_and_clear(mm, addr, pudp);
1298	BUG();
1299	return *pudp;
1300}
1301
1302static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1303					unsigned long address, pmd_t *pmdp)
1304{
1305	if (radix_enabled())
1306		return radix__pmdp_collapse_flush(vma, address, pmdp);
1307	return hash__pmdp_collapse_flush(vma, address, pmdp);
1308}
1309#define pmdp_collapse_flush pmdp_collapse_flush
1310
1311#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
1312pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
1313				   unsigned long addr,
1314				   pmd_t *pmdp, int full);
1315
1316#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
1317pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
1318				   unsigned long addr,
1319				   pud_t *pudp, int full);
1320
1321#define __HAVE_ARCH_PGTABLE_DEPOSIT
1322static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1323					      pmd_t *pmdp, pgtable_t pgtable)
1324{
1325	if (radix_enabled())
1326		return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1327	return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1328}
1329
1330#define __HAVE_ARCH_PGTABLE_WITHDRAW
1331static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1332						    pmd_t *pmdp)
1333{
1334	if (radix_enabled())
1335		return radix__pgtable_trans_huge_withdraw(mm, pmdp);
1336	return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1337}
1338
1339#define __HAVE_ARCH_PMDP_INVALIDATE
1340extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1341			     pmd_t *pmdp);
1342extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address,
1343			     pud_t *pudp);
1344
1345#define pmd_move_must_withdraw pmd_move_must_withdraw
1346struct spinlock;
1347extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1348				  struct spinlock *old_pmd_ptl,
1349				  struct vm_area_struct *vma);
1350/*
1351 * Hash translation mode use the deposited table to store hash pte
1352 * slot information.
1353 */
1354#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1355static inline bool arch_needs_pgtable_deposit(void)
1356{
1357	if (radix_enabled())
1358		return false;
1359	return true;
1360}
1361extern void serialize_against_pte_lookup(struct mm_struct *mm);
1362
1363#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1364
1365#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1366pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
1367void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1368			     pte_t *, pte_t, pte_t);
1369
1370/*
1371 * Returns true for a R -> RW upgrade of pte
1372 */
1373static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val)
1374{
1375	if (!(old_val & _PAGE_READ))
1376		return false;
1377
1378	if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE))
1379		return true;
1380
1381	return false;
1382}
1383
1384#endif /* __ASSEMBLER__ */
1385#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */