mmu.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
  3#define _ASM_POWERPC_BOOK3S_64_MMU_H_
  4
  5#include <asm/page.h>
  6
  7#ifndef __ASSEMBLER__
  8/*
  9 * Page size definition
 10 *
 11 *    shift : is the "PAGE_SHIFT" value for that page size
 12 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 13 *            directly to a slbmte "vsid" value
 14 *    penc  : is the HPTE encoding mask for the "LP" field:
 15 *
 16 */
 17struct mmu_psize_def {
 18	unsigned int	shift;	/* number of bits */
 19	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */
 20	unsigned int	tlbiel;	/* tlbiel supported for that page size */
 21	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
 22	unsigned long   h_rpt_pgsize; /* H_RPT_INVALIDATE page size encoding */
 23	union {
 24		unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
 25		unsigned long ap;	/* Ap encoding used by PowerISA 3.0 */
 26	};
 27};
 28extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 29#endif /* __ASSEMBLER__ */
 30
 31/* 64-bit classic hash table MMU */
 32#include <asm/book3s/64/mmu-hash.h>
 33
 34#ifndef __ASSEMBLER__
 35/*
 36 * ISA 3.0 partition and process table entry format
 37 */
 38struct prtb_entry {
 39	__be64 prtb0;
 40	__be64 prtb1;
 41};
 42extern struct prtb_entry *process_tb;
 43
 44struct patb_entry {
 45	__be64 patb0;
 46	__be64 patb1;
 47};
 48extern struct patb_entry *partition_tb;
 49
 50/* Bits in patb0 field */
 51#define PATB_HR		(1UL << 63)
 52#define RPDB_MASK	0x0fffffffffffff00UL
 53#define RPDB_SHIFT	(1UL << 8)
 54#define RTS1_SHIFT	61		/* top 2 bits of radix tree size */
 55#define RTS1_MASK	(3UL << RTS1_SHIFT)
 56#define RTS2_SHIFT	5		/* bottom 3 bits of radix tree size */
 57#define RTS2_MASK	(7UL << RTS2_SHIFT)
 58#define RPDS_MASK	0x1f		/* root page dir. size field */
 59
 60/* Bits in patb1 field */
 61#define PATB_GR		(1UL << 63)	/* guest uses radix; must match HR */
 62#define PRTS_MASK	0x1f		/* process table size field */
 63#define PRTB_MASK	0x0ffffffffffff000UL
 64
 65/* Number of supported LPID bits */
 66extern unsigned int mmu_lpid_bits;
 67
 68/* Number of supported PID bits */
 69extern unsigned int mmu_pid_bits;
 70
 71/* Base PID to allocate from */
 72extern unsigned int mmu_base_pid;
 73
 74extern unsigned long __ro_after_init memory_block_size;
 75
 76#define PRTB_SIZE_SHIFT	(mmu_pid_bits + 4)
 77#define PRTB_ENTRIES	(1ul << mmu_pid_bits)
 78
 79#define PATB_SIZE_SHIFT	(mmu_lpid_bits + 4)
 80#define PATB_ENTRIES	(1ul << mmu_lpid_bits)
 81
 82typedef unsigned long mm_context_id_t;
 83struct spinlock;
 84
 85/* Maximum possible number of NPUs in a system. */
 86#define NV_MAX_NPUS 8
 87
 88typedef struct {
 89	union {
 90		/*
 91		 * We use id as the PIDR content for radix. On hash we can use
 92		 * more than one id. The extended ids are used when we start
 93		 * having address above 512TB. We allocate one extended id
 94		 * for each 512TB. The new id is then used with the 49 bit
 95		 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits
 96		 * from EA and new context ids to build the new VAs.
 97		 */
 98		mm_context_id_t id;
 99#ifdef CONFIG_PPC_64S_HASH_MMU
100		mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
101#endif
102	};
103
104	/* Number of bits in the mm_cpumask */
105	atomic_t active_cpus;
106
107	/* Number of users of the external (Nest) MMU */
108	atomic_t copros;
109
110	/* Number of user space windows opened in process mm_context */
111	atomic_t vas_windows;
112
113#ifdef CONFIG_PPC_64S_HASH_MMU
114	struct hash_mm_context *hash_context;
115#endif
116
117	void __user *vdso;
118	/*
119	 * pagetable fragment support
120	 */
121	void *pte_frag;
122	void *pmd_frag;
123#ifdef CONFIG_SPAPR_TCE_IOMMU
124	struct list_head iommu_group_mem_list;
125#endif
126
127#ifdef CONFIG_PPC_MEM_KEYS
128	/*
129	 * Each bit represents one protection key.
130	 * bit set   -> key allocated
131	 * bit unset -> key available for allocation
132	 */
133	u32 pkey_allocation_map;
134	s16 execute_only_pkey; /* key holding execute-only protection */
135#endif
136} mm_context_t;
137
138#ifdef CONFIG_PPC_64S_HASH_MMU
139static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
140{
141	return ctx->hash_context->user_psize;
142}
143
144static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
145{
146	ctx->hash_context->user_psize = user_psize;
147}
148
149static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
150{
151	return ctx->hash_context->low_slices_psize;
152}
153
154static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
155{
156	return ctx->hash_context->high_slices_psize;
157}
158
159static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
160{
161	return ctx->hash_context->slb_addr_limit;
162}
163
164static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)
165{
166	ctx->hash_context->slb_addr_limit = limit;
167}
168
169static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
170{
171#ifdef CONFIG_PPC_64K_PAGES
172	if (psize == MMU_PAGE_64K)
173		return &ctx->hash_context->mask_64k;
174#endif
175#ifdef CONFIG_HUGETLB_PAGE
176	if (psize == MMU_PAGE_16M)
177		return &ctx->hash_context->mask_16m;
178	if (psize == MMU_PAGE_16G)
179		return &ctx->hash_context->mask_16g;
180#endif
181	BUG_ON(psize != MMU_PAGE_4K);
182
183	return &ctx->hash_context->mask_4k;
184}
185
186#ifdef CONFIG_PPC_SUBPAGE_PROT
187static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx)
188{
189	return ctx->hash_context->spt;
190}
191#endif
192
193/*
194 * The current system page and segment sizes
195 */
196extern int mmu_virtual_psize;
197extern int mmu_vmalloc_psize;
198extern int mmu_io_psize;
199#else /* CONFIG_PPC_64S_HASH_MMU */
200#ifdef CONFIG_PPC_64K_PAGES
201#define mmu_virtual_psize MMU_PAGE_64K
202#else
203#define mmu_virtual_psize MMU_PAGE_4K
204#endif
205#endif
206extern int mmu_linear_psize;
207extern int mmu_vmemmap_psize;
208
209/* MMU initialization */
210void mmu_early_init_devtree(void);
211void hash__early_init_devtree(void);
212void radix__early_init_devtree(void);
213#ifdef CONFIG_PPC_PKEY
214void pkey_early_init_devtree(void);
215#else
216static inline void pkey_early_init_devtree(void) {}
217#endif
218
219extern void hash__early_init_mmu(void);
220extern void radix__early_init_mmu(void);
221static inline void __init early_init_mmu(void)
222{
223	if (radix_enabled())
224		return radix__early_init_mmu();
225	return hash__early_init_mmu();
226}
227extern void hash__early_init_mmu_secondary(void);
228extern void radix__early_init_mmu_secondary(void);
229static inline void early_init_mmu_secondary(void)
230{
231	if (radix_enabled())
232		return radix__early_init_mmu_secondary();
233	return hash__early_init_mmu_secondary();
234}
235
236extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
237					 phys_addr_t first_memblock_size);
238static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
239					      phys_addr_t first_memblock_size)
240{
241	/*
242	 * Hash has more strict restrictions. At this point we don't
243	 * know which translations we will pick. Hence go with hash
244	 * restrictions.
245	 */
246	if (!early_radix_enabled())
247		hash__setup_initial_memory_limit(first_memblock_base,
248						 first_memblock_size);
249}
250
251#ifdef CONFIG_PPC_PSERIES
252void __init radix_init_pseries(void);
253#else
254static inline void radix_init_pseries(void) { }
255#endif
256
257#ifdef CONFIG_HOTPLUG_CPU
258#define arch_clear_mm_cpumask_cpu(cpu, mm)				\
259	do {								\
260		if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {		\
261			dec_mm_active_cpus(mm);				\
262			cpumask_clear_cpu(cpu, mm_cpumask(mm));		\
263		}							\
264	} while (0)
265
266void cleanup_cpu_mmu_context(void);
267#endif
268
269#ifdef CONFIG_PPC_64S_HASH_MMU
270static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
271{
272	int index = ea >> MAX_EA_BITS_PER_CONTEXT;
273
274	if (likely(index < ARRAY_SIZE(ctx->extended_id)))
275		return ctx->extended_id[index];
276
277	/* should never happen */
278	WARN_ON(1);
279	return 0;
280}
281
282static inline unsigned long get_user_vsid(mm_context_t *ctx,
283					  unsigned long ea, int ssize)
284{
285	unsigned long context = get_user_context(ctx, ea);
286
287	return get_vsid(context, ea, ssize);
288}
289#endif
290
291#endif /* __ASSEMBLER__ */
292#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */