hash.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
  3#define _ASM_POWERPC_BOOK3S_64_HASH_H
  4#ifdef __KERNEL__
  5
  6#include <asm/asm-const.h>
  7#include <asm/book3s/64/slice.h>
  8
  9/*
 10 * Common bits between 4K and 64K pages in a linux-style PTE.
 11 * Additional bits may be defined in pgtable-hash64-*.h
 12 *
 13 */
 14#define H_PTE_NONE_MASK		_PAGE_HPTEFLAGS
 15
 16#ifdef CONFIG_PPC_64K_PAGES
 17#include <asm/book3s/64/hash-64k.h>
 18#else
 19#include <asm/book3s/64/hash-4k.h>
 20#endif
 21
 22#define H_PTRS_PER_PTE		(1 << H_PTE_INDEX_SIZE)
 23#define H_PTRS_PER_PMD		(1 << H_PMD_INDEX_SIZE)
 24#define H_PTRS_PER_PUD		(1 << H_PUD_INDEX_SIZE)
 25
 26/* Bits to set in a PMD/PUD/PGD entry valid bit*/
 27#define HASH_PMD_VAL_BITS		(0x8000000000000000UL)
 28#define HASH_PUD_VAL_BITS		(0x8000000000000000UL)
 29#define HASH_PGD_VAL_BITS		(0x8000000000000000UL)
 30
 31/*
 32 * Size of EA range mapped by our pagetables.
 33 */
 34#define H_PGTABLE_EADDR_SIZE	(H_PTE_INDEX_SIZE + H_PMD_INDEX_SIZE + \
 35				 H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
 36#define H_PGTABLE_RANGE		(ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
 37/*
 38 * Top 2 bits are ignored in page table walk.
 39 */
 40#define EA_MASK			(~(0xcUL << 60))
 41
 42/*
 43 * We store the slot details in the second half of page table.
 44 * Increase the pud level table so that hugetlb ptes can be stored
 45 * at pud level.
 46 */
 47#if defined(CONFIG_HUGETLB_PAGE) &&  defined(CONFIG_PPC_64K_PAGES)
 48#define H_PUD_CACHE_INDEX	(H_PUD_INDEX_SIZE + 1)
 49#else
 50#define H_PUD_CACHE_INDEX	(H_PUD_INDEX_SIZE)
 51#endif
 52
 53/*
 54 * +------------------------------+
 55 * |                              |
 56 * |                              |
 57 * |                              |
 58 * +------------------------------+  Kernel virtual map end (0xc00e000000000000)
 59 * |                              |
 60 * |                              |
 61 * |      512TB/16TB of vmemmap   |
 62 * |                              |
 63 * |                              |
 64 * +------------------------------+  Kernel vmemmap  start
 65 * |                              |
 66 * |      512TB/16TB of IO map    |
 67 * |                              |
 68 * +------------------------------+  Kernel IO map start
 69 * |                              |
 70 * |      512TB/16TB of vmap      |
 71 * |                              |
 72 * +------------------------------+  Kernel virt start (0xc008000000000000)
 73 * |                              |
 74 * |                              |
 75 * |                              |
 76 * +------------------------------+  Kernel linear (0xc.....)
 77 */
 78
 79#define H_VMALLOC_START		H_KERN_VIRT_START
 80#define H_VMALLOC_SIZE		H_KERN_MAP_SIZE
 81#define H_VMALLOC_END		(H_VMALLOC_START + H_VMALLOC_SIZE)
 82
 83#define H_KERN_IO_START		H_VMALLOC_END
 84#define H_KERN_IO_SIZE		H_KERN_MAP_SIZE
 85#define H_KERN_IO_END		(H_KERN_IO_START + H_KERN_IO_SIZE)
 86
 87#define H_VMEMMAP_START		H_KERN_IO_END
 88#define H_VMEMMAP_SIZE		H_KERN_MAP_SIZE
 89#define H_VMEMMAP_END		(H_VMEMMAP_START + H_VMEMMAP_SIZE)
 90
 91#define NON_LINEAR_REGION_ID(ea)	((((unsigned long)ea - H_KERN_VIRT_START) >> REGION_SHIFT) + 2)
 92
 93/*
 94 * Region IDs
 95 */
 96#define USER_REGION_ID		0
 97#define LINEAR_MAP_REGION_ID	1
 98#define VMALLOC_REGION_ID	NON_LINEAR_REGION_ID(H_VMALLOC_START)
 99#define IO_REGION_ID		NON_LINEAR_REGION_ID(H_KERN_IO_START)
100#define VMEMMAP_REGION_ID	NON_LINEAR_REGION_ID(H_VMEMMAP_START)
101#define INVALID_REGION_ID	(VMEMMAP_REGION_ID + 1)
102
103/*
104 * Defines the address of the vmemap area, in its own region on
105 * hash table CPUs.
106 */
107
108/* PTEIDX nibble */
109#define _PTEIDX_SECONDARY	0x8
110#define _PTEIDX_GROUP_IX	0x7
111
112#define H_PMD_BAD_BITS		(PTE_TABLE_SIZE-1)
113#define H_PUD_BAD_BITS		(PMD_TABLE_SIZE-1)
114
115#ifndef __ASSEMBLER__
116static inline int get_region_id(unsigned long ea)
117{
118	int region_id;
119	int id = (ea >> 60UL);
120
121	if (id == 0)
122		return USER_REGION_ID;
123
124	if (id != (PAGE_OFFSET >> 60))
125		return INVALID_REGION_ID;
126
127	if (ea < H_KERN_VIRT_START)
128		return LINEAR_MAP_REGION_ID;
129
130	BUILD_BUG_ON(NON_LINEAR_REGION_ID(H_VMALLOC_START) != 2);
131
132	region_id = NON_LINEAR_REGION_ID(ea);
133	return region_id;
134}
135
136static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
137{
138	return (((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
139}
140
141#define	hash__pmd_bad(pmd)		(pmd_val(pmd) & H_PMD_BAD_BITS)
142
143/*
144 * pud comparison that will work with both pte and page table pointer.
145 */
146static inline int hash__pud_same(pud_t pud_a, pud_t pud_b)
147{
148	return (((pud_raw(pud_a) ^ pud_raw(pud_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
149}
150#define	hash__pud_bad(pud)		(pud_val(pud) & H_PUD_BAD_BITS)
151
152static inline int hash__p4d_bad(p4d_t p4d)
153{
154	return (p4d_val(p4d) == 0);
155}
156#ifdef CONFIG_STRICT_KERNEL_RWX
157extern void hash__mark_rodata_ro(void);
158extern void hash__mark_initmem_nx(void);
159#endif
160
161extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
162			    pte_t *ptep, unsigned long pte, int huge);
163unsigned long htab_convert_pte_flags(unsigned long pteflags, unsigned long flags);
164/* Atomic PTE updates */
165static inline unsigned long hash__pte_update_one(pte_t *ptep, unsigned long clr,
166						 unsigned long set)
167{
168	__be64 old_be, tmp_be;
169
170	__asm__ __volatile__(
171	"1:	ldarx	%0,0,%3		# pte_update\n\
172	and.	%1,%0,%6\n\
173	bne-	1b \n\
174	andc	%1,%0,%4 \n\
175	or	%1,%1,%7\n\
176	stdcx.	%1,0,%3 \n\
177	bne-	1b"
178	: "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
179	: "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep),
180	  "r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set))
181	: "cc" );
182
183	return be64_to_cpu(old_be);
184}
185
186static inline unsigned long hash__pte_update(struct mm_struct *mm,
187					 unsigned long addr,
188					 pte_t *ptep, unsigned long clr,
189					 unsigned long set,
190					 int huge)
191{
192	unsigned long old;
193
194	old = hash__pte_update_one(ptep, clr, set);
195
196	if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && huge) {
197		unsigned int psize = get_slice_psize(mm, addr);
198		int nb, i;
199
200		if (psize == MMU_PAGE_16M)
201			nb = SZ_16M / PMD_SIZE;
202		else if (psize == MMU_PAGE_16G)
203			nb = SZ_16G / PUD_SIZE;
204		else
205			nb = 1;
206
207		WARN_ON_ONCE(nb == 1);	/* Should never happen */
208
209		for (i = 1; i < nb; i++)
210			hash__pte_update_one(ptep + i, clr, set);
211	}
212	/* huge pages use the old page table lock */
213	if (!huge)
214		assert_pte_locked(mm, addr);
215
216	if (old & H_PAGE_HASHPTE)
217		hpte_need_flush(mm, addr, ptep, old, huge);
218
219	return old;
220}
221
222/* Set the dirty and/or accessed bits atomically in a linux PTE, this
223 * function doesn't need to flush the hash entry
224 */
225static inline void hash__ptep_set_access_flags(pte_t *ptep, pte_t entry)
226{
227	__be64 old, tmp, val, mask;
228
229	mask = cpu_to_be64(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_READ | _PAGE_WRITE |
230			   _PAGE_EXEC | _PAGE_SOFT_DIRTY);
231
232	val = pte_raw(entry) & mask;
233
234	__asm__ __volatile__(
235	"1:	ldarx	%0,0,%4\n\
236		and.	%1,%0,%6\n\
237		bne-	1b \n\
238		or	%0,%3,%0\n\
239		stdcx.	%0,0,%4\n\
240		bne-	1b"
241	:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
242	:"r" (val), "r" (ptep), "m" (*ptep), "r" (cpu_to_be64(H_PAGE_BUSY))
243	:"cc");
244}
245
246static inline int hash__pte_same(pte_t pte_a, pte_t pte_b)
247{
248	return (((pte_raw(pte_a) ^ pte_raw(pte_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
249}
250
251static inline int hash__pte_none(pte_t pte)
252{
253	return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0;
254}
255
256unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
257		int ssize, real_pte_t rpte, unsigned int subpg_index);
258
259/* This low level function performs the actual PTE insertion
260 * Setting the PTE depends on the MMU type and other factors. It's
261 * an horrible mess that I'm not going to try to clean up now but
262 * I'm keeping it in one place rather than spread around
263 */
264static inline void hash__set_pte_at(struct mm_struct *mm, unsigned long addr,
265				  pte_t *ptep, pte_t pte, int percpu)
266{
267	/*
268	 * Anything else just stores the PTE normally. That covers all 64-bit
269	 * cases, and 32-bit non-hash with 32-bit PTEs.
270	 */
271	*ptep = pte;
272}
273
274#ifdef CONFIG_TRANSPARENT_HUGEPAGE
275extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
276				   pmd_t *pmdp, unsigned long old_pmd);
277#else
278static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
279					  unsigned long addr, pmd_t *pmdp,
280					  unsigned long old_pmd)
281{
282	WARN(1, "%s called with THP disabled\n", __func__);
283}
284#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
285
286
287int hash__map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot);
288extern int __meminit hash__vmemmap_create_mapping(unsigned long start,
289					      unsigned long page_size,
290					      unsigned long phys);
291extern void hash__vmemmap_remove_mapping(unsigned long start,
292				     unsigned long page_size);
293
294int hash__create_section_mapping(unsigned long start, unsigned long end,
295				 int nid, pgprot_t prot);
296int hash__remove_section_mapping(unsigned long start, unsigned long end);
297
298#endif /* !__ASSEMBLER__ */
299#endif /* __KERNEL__ */
300#endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */