entry.S

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * OpenRISC entry.S
   4 *
   5 * Linux architectural port borrowing liberally from similar works of
   6 * others.  All original copyrights apply as per the original source
   7 * declaration.
   8 *
   9 * Modifications for the OpenRISC architecture:
  10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  11 * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
  12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  13 */
  14
  15#include <linux/linkage.h>
  16#include <linux/pgtable.h>
  17
  18#include <asm/processor.h>
  19#include <asm/unistd.h>
  20#include <asm/thread_info.h>
  21#include <asm/errno.h>
  22#include <asm/spr_defs.h>
  23#include <asm/page.h>
  24#include <asm/mmu.h>
  25#include <asm/asm-offsets.h>
  26
  27#define DISABLE_INTERRUPTS(t1,t2)			\
  28	l.mfspr t2,r0,SPR_SR				;\
  29	l.movhi	t1,hi(~(SPR_SR_IEE|SPR_SR_TEE))		;\
  30	l.ori	t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE))	;\
  31	l.and   t2,t2,t1				;\
  32	l.mtspr r0,t2,SPR_SR
  33
  34#define ENABLE_INTERRUPTS(t1)				\
  35	l.mfspr	t1,r0,SPR_SR				;\
  36	l.ori	t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE)		;\
  37	l.mtspr	r0,t1,SPR_SR
  38
  39/* =========================================================[ macros ]=== */
  40
  41#ifdef CONFIG_TRACE_IRQFLAGS
  42/*
  43 * Trace irq on/off creating a stack frame.
  44 */
  45#define TRACE_IRQS_OP(trace_op)					\
  46	l.sw 	-8(r1),r2	/* store frame pointer */		;\
  47	l.sw	-4(r1),r9	/* store return address */		;\
  48	l.addi	r2,r1,0		/* move sp to fp */			;\
  49	l.jal	trace_op						;\
  50	 l.addi	r1,r1,-8						;\
  51	l.ori	r1,r2,0		/* restore sp */			;\
  52	l.lwz	r9,-4(r1)	/* restore return address */		;\
  53	l.lwz	r2,-8(r1)	/* restore fp */			;\
  54/*
  55 * Trace irq on/off and save registers we need that would otherwise be
  56 * clobbered.
  57 */
  58#define TRACE_IRQS_SAVE(t1,trace_op)					\
  59	l.sw	-12(r1),t1	/* save extra reg */			;\
  60	l.sw 	-8(r1),r2	/* store frame pointer */		;\
  61	l.sw	-4(r1),r9	/* store return address */		;\
  62	l.addi	r2,r1,0		/* move sp to fp */			;\
  63	l.jal	trace_op						;\
  64	 l.addi	r1,r1,-12						;\
  65	l.ori	r1,r2,0		/* restore sp */			;\
  66	l.lwz	r9,-4(r1)	/* restore return address */		;\
  67	l.lwz	r2,-8(r1)	/* restore fp */			;\
  68	l.lwz	t1,-12(r1)	/* restore extra reg */
  69
  70#define TRACE_IRQS_OFF	TRACE_IRQS_OP(trace_hardirqs_off)
  71#define TRACE_IRQS_ON	TRACE_IRQS_OP(trace_hardirqs_on)
  72#define TRACE_IRQS_ON_SYSCALL						\
  73	TRACE_IRQS_SAVE(r10,trace_hardirqs_on)				;\
  74	l.lwz	r3,PT_GPR3(r1)						;\
  75	l.lwz	r4,PT_GPR4(r1)						;\
  76	l.lwz	r5,PT_GPR5(r1)						;\
  77	l.lwz	r6,PT_GPR6(r1)						;\
  78	l.lwz	r7,PT_GPR7(r1)						;\
  79	l.lwz	r8,PT_GPR8(r1)						;\
  80	l.lwz	r11,PT_GPR11(r1)
  81#define TRACE_IRQS_OFF_ENTRY						\
  82	l.lwz	r5,PT_SR(r1)						;\
  83	l.andi	r3,r5,(SPR_SR_IEE|SPR_SR_TEE)				;\
  84	l.sfeq	r5,r0		/* skip trace if irqs were already off */;\
  85	l.bf	1f							;\
  86	 l.nop								;\
  87	TRACE_IRQS_SAVE(r4,trace_hardirqs_off)				;\
  881:
  89#else
  90#define TRACE_IRQS_OFF
  91#define TRACE_IRQS_ON
  92#define TRACE_IRQS_OFF_ENTRY
  93#define TRACE_IRQS_ON_SYSCALL
  94#endif
  95
  96/*
  97 * We need to disable interrupts at beginning of RESTORE_ALL
  98 * since interrupt might come in after we've loaded EPC return address
  99 * and overwrite EPC with address somewhere in RESTORE_ALL
 100 * which is of course wrong!
 101 */
 102
 103#define RESTORE_ALL						\
 104	DISABLE_INTERRUPTS(r3,r4)				;\
 105	l.lwz   r3,PT_PC(r1)					;\
 106	l.mtspr r0,r3,SPR_EPCR_BASE				;\
 107	l.lwz   r3,PT_SR(r1)					;\
 108	l.mtspr r0,r3,SPR_ESR_BASE				;\
 109	l.lwz   r2,PT_GPR2(r1)					;\
 110	l.lwz   r3,PT_GPR3(r1)					;\
 111	l.lwz   r4,PT_GPR4(r1)					;\
 112	l.lwz   r5,PT_GPR5(r1)					;\
 113	l.lwz   r6,PT_GPR6(r1)					;\
 114	l.lwz   r7,PT_GPR7(r1)					;\
 115	l.lwz   r8,PT_GPR8(r1)					;\
 116	l.lwz   r9,PT_GPR9(r1)					;\
 117	l.lwz   r10,PT_GPR10(r1)					;\
 118	l.lwz   r11,PT_GPR11(r1)					;\
 119	l.lwz   r12,PT_GPR12(r1)					;\
 120	l.lwz   r13,PT_GPR13(r1)					;\
 121	l.lwz   r14,PT_GPR14(r1)					;\
 122	l.lwz   r15,PT_GPR15(r1)					;\
 123	l.lwz   r16,PT_GPR16(r1)					;\
 124	l.lwz   r17,PT_GPR17(r1)					;\
 125	l.lwz   r18,PT_GPR18(r1)					;\
 126	l.lwz   r19,PT_GPR19(r1)					;\
 127	l.lwz   r20,PT_GPR20(r1)					;\
 128	l.lwz   r21,PT_GPR21(r1)					;\
 129	l.lwz   r22,PT_GPR22(r1)					;\
 130	l.lwz   r23,PT_GPR23(r1)					;\
 131	l.lwz   r24,PT_GPR24(r1)					;\
 132	l.lwz   r25,PT_GPR25(r1)					;\
 133	l.lwz   r26,PT_GPR26(r1)					;\
 134	l.lwz   r27,PT_GPR27(r1)					;\
 135	l.lwz   r28,PT_GPR28(r1)					;\
 136	l.lwz   r29,PT_GPR29(r1)					;\
 137	l.lwz   r30,PT_GPR30(r1)					;\
 138	l.lwz   r31,PT_GPR31(r1)					;\
 139	l.lwz   r1,PT_SP(r1)					;\
 140	l.rfe
 141
 142
 143#define EXCEPTION_ENTRY(handler)				\
 144	.global	handler						;\
 145handler:							;\
 146	/* r1, EPCR, ESR a already saved */			;\
 147	l.sw	PT_GPR2(r1),r2					;\
 148	l.sw    PT_GPR3(r1),r3					;\
 149	/* r4 already save */					;\
 150	l.sw    PT_GPR5(r1),r5					;\
 151	l.sw    PT_GPR6(r1),r6					;\
 152	l.sw    PT_GPR7(r1),r7					;\
 153	l.sw    PT_GPR8(r1),r8					;\
 154	l.sw    PT_GPR9(r1),r9					;\
 155	/* r10 already saved */					;\
 156	l.sw    PT_GPR11(r1),r11					;\
 157	/* r12 already saved */					;\
 158	l.sw    PT_GPR13(r1),r13					;\
 159	l.sw    PT_GPR14(r1),r14					;\
 160	l.sw    PT_GPR15(r1),r15					;\
 161	l.sw    PT_GPR16(r1),r16					;\
 162	l.sw    PT_GPR17(r1),r17					;\
 163	l.sw    PT_GPR18(r1),r18					;\
 164	l.sw    PT_GPR19(r1),r19					;\
 165	l.sw    PT_GPR20(r1),r20					;\
 166	l.sw    PT_GPR21(r1),r21					;\
 167	l.sw    PT_GPR22(r1),r22					;\
 168	l.sw    PT_GPR23(r1),r23					;\
 169	l.sw    PT_GPR24(r1),r24					;\
 170	l.sw    PT_GPR25(r1),r25					;\
 171	l.sw    PT_GPR26(r1),r26					;\
 172	l.sw    PT_GPR27(r1),r27					;\
 173	l.sw    PT_GPR28(r1),r28					;\
 174	l.sw    PT_GPR29(r1),r29					;\
 175	/* r30 already save */					;\
 176	l.sw    PT_GPR31(r1),r31					;\
 177	TRACE_IRQS_OFF_ENTRY						;\
 178	/* Store -1 in orig_gpr11 for non-syscall exceptions */	;\
 179	l.addi	r30,r0,-1					;\
 180	l.sw	PT_ORIG_GPR11(r1),r30
 181
 182#define UNHANDLED_EXCEPTION(handler,vector)			\
 183	.global	handler						;\
 184handler:							;\
 185	/* r1, EPCR, ESR already saved */			;\
 186	l.sw    PT_GPR2(r1),r2					;\
 187	l.sw    PT_GPR3(r1),r3					;\
 188	l.sw    PT_GPR5(r1),r5					;\
 189	l.sw    PT_GPR6(r1),r6					;\
 190	l.sw    PT_GPR7(r1),r7					;\
 191	l.sw    PT_GPR8(r1),r8					;\
 192	l.sw    PT_GPR9(r1),r9					;\
 193	/* r10 already saved */					;\
 194	l.sw    PT_GPR11(r1),r11					;\
 195	/* r12 already saved */					;\
 196	l.sw    PT_GPR13(r1),r13					;\
 197	l.sw    PT_GPR14(r1),r14					;\
 198	l.sw    PT_GPR15(r1),r15					;\
 199	l.sw    PT_GPR16(r1),r16					;\
 200	l.sw    PT_GPR17(r1),r17					;\
 201	l.sw    PT_GPR18(r1),r18					;\
 202	l.sw    PT_GPR19(r1),r19					;\
 203	l.sw    PT_GPR20(r1),r20					;\
 204	l.sw    PT_GPR21(r1),r21					;\
 205	l.sw    PT_GPR22(r1),r22					;\
 206	l.sw    PT_GPR23(r1),r23					;\
 207	l.sw    PT_GPR24(r1),r24					;\
 208	l.sw    PT_GPR25(r1),r25					;\
 209	l.sw    PT_GPR26(r1),r26					;\
 210	l.sw    PT_GPR27(r1),r27					;\
 211	l.sw    PT_GPR28(r1),r28					;\
 212	l.sw    PT_GPR29(r1),r29					;\
 213	/* r30 already saved */						;\
 214	l.sw    PT_GPR31(r1),r31					;\
 215	/* Store -1 in orig_gpr11 for non-syscall exceptions */	;\
 216	l.addi	r30,r0,-1					;\
 217	l.sw	PT_ORIG_GPR11(r1),r30				;\
 218	l.addi	r3,r1,0						;\
 219	/* r4 is exception EA */				;\
 220	l.addi	r5,r0,vector					;\
 221	l.jal	unhandled_exception				;\
 222	 l.nop							;\
 223	l.j	_ret_from_exception				;\
 224	 l.nop
 225
 226/* clobbers 'reg' */
 227#define CLEAR_LWA_FLAG(reg)		\
 228	l.movhi	reg,hi(lwa_flag)	;\
 229	l.ori	reg,reg,lo(lwa_flag)	;\
 230	l.sw	0(reg),r0
 231/*
 232 * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
 233 *       contain the same values as when exception we're handling
 234 *	 occured. in fact they never do. if you need them use
 235 *	 values saved on stack (for SPR_EPC, SPR_ESR) or content
 236 *       of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
 237 *       in 'arch/openrisc/kernel/head.S'
 238 */
 239
 240/* =====================================================[ exceptions] === */
 241
 242	__REF
 243
 244/* ---[ 0x100: RESET exception ]----------------------------------------- */
 245
 246EXCEPTION_ENTRY(_tng_kernel_start)
 247	l.jal	_start
 248	 l.andi r0,r0,0
 249
 250/* ---[ 0x200: BUS exception ]------------------------------------------- */
 251
 252EXCEPTION_ENTRY(_bus_fault_handler)
 253	CLEAR_LWA_FLAG(r3)
 254	/* r4: EA of fault (set by EXCEPTION_HANDLE) */
 255	l.jal   do_bus_fault
 256	 l.addi  r3,r1,0 /* pt_regs */
 257
 258	l.j     _ret_from_exception
 259	 l.nop
 260
 261/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
 262EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
 263	CLEAR_LWA_FLAG(r3)
 264	l.and	r5,r5,r0
 265	l.j	1f
 266	 l.nop
 267
 268EXCEPTION_ENTRY(_data_page_fault_handler)
 269	CLEAR_LWA_FLAG(r3)
 270	/* set up parameters for do_page_fault */
 271	l.ori	r5,r0,0x300		   // exception vector
 2721:
 273	l.addi  r3,r1,0                    // pt_regs
 274	/* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 275
 276#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
 277	l.lwz   r6,PT_PC(r3)               // address of an offending insn
 278	l.lwz   r6,0(r6)                   // instruction that caused pf
 279
 280	l.srli  r6,r6,26                   // check opcode for jump insn
 281	l.sfeqi r6,0                       // l.j
 282	l.bf    8f
 283	l.sfeqi r6,1                       // l.jal
 284	l.bf    8f
 285	l.sfeqi r6,3                       // l.bnf
 286	l.bf    8f
 287	l.sfeqi r6,4                       // l.bf
 288	l.bf    8f
 289	l.sfeqi r6,0x11                    // l.jr
 290	l.bf    8f
 291	l.sfeqi r6,0x12                    // l.jalr
 292	l.bf    8f
 293	 l.nop
 294
 295	l.j     9f
 296	 l.nop
 297
 2988: // offending insn is in delay slot
 299	l.lwz   r6,PT_PC(r3)               // address of an offending insn
 300	l.addi  r6,r6,4
 301	l.lwz   r6,0(r6)                   // instruction that caused pf
 302	l.srli  r6,r6,26                   // get opcode
 3039: // offending instruction opcode loaded in r6
 304
 305#else
 306
 307	l.mfspr r6,r0,SPR_SR               // SR
 308	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
 309	l.sfne  r6,r0                      // exception happened in delay slot
 310	l.bnf   7f
 311	 l.lwz  r6,PT_PC(r3)               // address of an offending insn
 312
 313	l.addi	r6,r6,4                    // offending insn is in delay slot
 3147:
 315	l.lwz   r6,0(r6)                   // instruction that caused pf
 316	l.srli  r6,r6,26                   // check opcode for write access
 317#endif
 318
 319	l.sfgeui r6,0x33                   // check opcode for write access
 320	l.bnf   1f
 321	l.sfleui r6,0x37
 322	l.bnf   1f
 323	l.ori   r6,r0,0x1                  // write access
 324	l.j     2f
 325	 l.nop
 3261:	l.ori   r6,r0,0x0                  // !write access
 3272:
 328
 329	/* call fault.c handler in openrisc/mm/fault.c */
 330	l.jal   do_page_fault
 331	 l.nop
 332	l.j     _ret_from_exception
 333	 l.nop
 334
 335/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
 336EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
 337	CLEAR_LWA_FLAG(r3)
 338	l.and	r5,r5,r0
 339	l.j	1f
 340	 l.nop
 341
 342EXCEPTION_ENTRY(_insn_page_fault_handler)
 343	CLEAR_LWA_FLAG(r3)
 344	/* set up parameters for do_page_fault */
 345	l.ori	r5,r0,0x400		   // exception vector
 3461:
 347	l.addi  r3,r1,0                    // pt_regs
 348	/* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 349	l.ori	r6,r0,0x0		   // !write access
 350
 351	/* call fault.c handler in openrisc/mm/fault.c */
 352	l.jal   do_page_fault
 353	 l.nop
 354	l.j     _ret_from_exception
 355	 l.nop
 356
 357
 358/* ---[ 0x500: Timer exception ]----------------------------------------- */
 359
 360EXCEPTION_ENTRY(_timer_handler)
 361	CLEAR_LWA_FLAG(r3)
 362	l.jal	timer_interrupt
 363	 l.addi r3,r1,0 /* pt_regs */
 364
 365	l.j    _ret_from_intr
 366	 l.nop
 367
 368/* ---[ 0x600: Alignment exception ]-------------------------------------- */
 369
 370EXCEPTION_ENTRY(_alignment_handler)
 371	CLEAR_LWA_FLAG(r3)
 372	/* r4: EA of fault (set by EXCEPTION_HANDLE) */
 373	l.jal   do_unaligned_access
 374	 l.addi  r3,r1,0 /* pt_regs */
 375
 376	l.j     _ret_from_exception
 377	 l.nop
 378
 379#if 0
 380EXCEPTION_ENTRY(_alignment_handler)
 381//        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the effective address */
 382	l.addi	r2,r4,0
 383//        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
 384	l.lwz   r5,PT_PC(r1)
 385
 386	l.lwz   r3,0(r5)                /* Load insn */
 387	l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 388
 389	l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
 390	l.bf    jmp
 391	l.sfeqi r4,0x01
 392	l.bf    jmp
 393	l.sfeqi r4,0x03
 394	l.bf    jmp
 395	l.sfeqi r4,0x04
 396	l.bf    jmp
 397	l.sfeqi r4,0x11
 398	l.bf    jr
 399	l.sfeqi r4,0x12
 400	l.bf    jr
 401	l.nop
 402	l.j     1f
 403	l.addi  r5,r5,4                 /* Increment PC to get return insn address */
 404
 405jmp:
 406	l.slli  r4,r3,6                 /* Get the signed extended jump length */
 407	l.srai  r4,r4,4
 408
 409	l.lwz   r3,4(r5)                /* Load the real load/store insn */
 410
 411	l.add   r5,r5,r4                /* Calculate jump target address */
 412
 413	l.j     1f
 414	l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 415
 416jr:
 417	l.slli  r4,r3,9                 /* Shift to get the reg nb */
 418	l.andi  r4,r4,0x7c
 419
 420	l.lwz   r3,4(r5)                /* Load the real load/store insn */
 421
 422	l.add   r4,r4,r1                /* Load the jump register value from the stack */
 423	l.lwz   r5,0(r4)
 424
 425	l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 426
 427
 4281:
 429//	  l.mtspr r0,r5,SPR_EPCR_BASE
 430	l.sw	PT_PC(r1),r5
 431
 432	l.sfeqi r4,0x26
 433	l.bf    lhs
 434	l.sfeqi r4,0x25
 435	l.bf    lhz
 436	l.sfeqi r4,0x22
 437	l.bf    lws
 438	l.sfeqi r4,0x21
 439	l.bf    lwz
 440	l.sfeqi r4,0x37
 441	l.bf    sh
 442	l.sfeqi r4,0x35
 443	l.bf    sw
 444	l.nop
 445
 4461:      l.j     1b                      /* I don't know what to do */
 447	l.nop
 448
 449lhs:    l.lbs   r5,0(r2)
 450	l.slli  r5,r5,8
 451	l.lbz   r6,1(r2)
 452	l.or    r5,r5,r6
 453	l.srli  r4,r3,19
 454	l.andi  r4,r4,0x7c
 455	l.add   r4,r4,r1
 456	l.j     align_end
 457	l.sw    0(r4),r5
 458
 459lhz:    l.lbz   r5,0(r2)
 460	l.slli  r5,r5,8
 461	l.lbz   r6,1(r2)
 462	l.or    r5,r5,r6
 463	l.srli  r4,r3,19
 464	l.andi  r4,r4,0x7c
 465	l.add   r4,r4,r1
 466	l.j     align_end
 467	l.sw    0(r4),r5
 468
 469lws:    l.lbs   r5,0(r2)
 470	l.slli  r5,r5,24
 471	l.lbz   r6,1(r2)
 472	l.slli  r6,r6,16
 473	l.or    r5,r5,r6
 474	l.lbz   r6,2(r2)
 475	l.slli  r6,r6,8
 476	l.or    r5,r5,r6
 477	l.lbz   r6,3(r2)
 478	l.or    r5,r5,r6
 479	l.srli  r4,r3,19
 480	l.andi  r4,r4,0x7c
 481	l.add   r4,r4,r1
 482	l.j     align_end
 483	l.sw    0(r4),r5
 484
 485lwz:    l.lbz   r5,0(r2)
 486	l.slli  r5,r5,24
 487	l.lbz   r6,1(r2)
 488	l.slli  r6,r6,16
 489	l.or    r5,r5,r6
 490	l.lbz   r6,2(r2)
 491	l.slli  r6,r6,8
 492	l.or    r5,r5,r6
 493	l.lbz   r6,3(r2)
 494	l.or    r5,r5,r6
 495	l.srli  r4,r3,19
 496	l.andi  r4,r4,0x7c
 497	l.add   r4,r4,r1
 498	l.j     align_end
 499	l.sw    0(r4),r5
 500
 501sh:
 502	l.srli  r4,r3,9
 503	l.andi  r4,r4,0x7c
 504	l.add   r4,r4,r1
 505	l.lwz   r5,0(r4)
 506	l.sb    1(r2),r5
 507	l.srli  r5,r5,8
 508	l.j     align_end
 509	l.sb    0(r2),r5
 510
 511sw:
 512	l.srli  r4,r3,9
 513	l.andi  r4,r4,0x7c
 514	l.add   r4,r4,r1
 515	l.lwz   r5,0(r4)
 516	l.sb    3(r2),r5
 517	l.srli  r5,r5,8
 518	l.sb    2(r2),r5
 519	l.srli  r5,r5,8
 520	l.sb    1(r2),r5
 521	l.srli  r5,r5,8
 522	l.j     align_end
 523	l.sb    0(r2),r5
 524
 525align_end:
 526	l.j    _ret_from_intr
 527	l.nop
 528#endif
 529
 530/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
 531
 532EXCEPTION_ENTRY(_illegal_instruction_handler)
 533	/* r4: EA of fault (set by EXCEPTION_HANDLE) */
 534	l.jal   do_illegal_instruction
 535	 l.addi  r3,r1,0 /* pt_regs */
 536
 537	l.j     _ret_from_exception
 538	 l.nop
 539
 540/* ---[ 0x800: External interrupt exception ]---------------------------- */
 541
 542EXCEPTION_ENTRY(_external_irq_handler)
 543#ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
 544	l.lwz	r4,PT_SR(r1)		// were interrupts enabled ?
 545	l.andi	r4,r4,SPR_SR_IEE
 546	l.sfeqi	r4,0
 547	l.bnf	1f			// ext irq enabled, all ok.
 548	l.nop
 549
 550#ifdef CONFIG_PRINTK
 551	l.addi  r1,r1,-0x8
 552	l.movhi r3,hi(42f)
 553	l.ori	r3,r3,lo(42f)
 554	l.sw    0x0(r1),r3
 555	l.jal   _printk
 556	l.sw    0x4(r1),r4
 557	l.addi  r1,r1,0x8
 558
 559	.section .rodata, "a"
 56042:
 561		.string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
 562		.align 4
 563	.previous
 564#endif
 565
 566	l.ori	r4,r4,SPR_SR_IEE	// fix the bug
 567//	l.sw	PT_SR(r1),r4
 5681:
 569#endif
 570	CLEAR_LWA_FLAG(r3)
 571	l.addi	r3,r1,0
 572	l.movhi	r8,hi(generic_handle_arch_irq)
 573	l.ori	r8,r8,lo(generic_handle_arch_irq)
 574	l.jalr r8
 575	l.nop
 576	l.j    _ret_from_intr
 577	l.nop
 578
 579/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
 580
 581
 582/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
 583
 584
 585/* ---[ 0xb00: Range exception ]----------------------------------------- */
 586
 587UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
 588
 589/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
 590
 591/*
 592 * Syscalls are a special type of exception in that they are
 593 * _explicitly_ invoked by userspace and can therefore be
 594 * held to conform to the same ABI as normal functions with
 595 * respect to whether registers are preserved across the call
 596 * or not.
 597 */
 598
 599/* Upon syscall entry we just save the callee-saved registers
 600 * and not the call-clobbered ones.
 601 */
 602
 603_string_syscall_return:
 604	.string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
 605	.align 4
 606
 607ENTRY(_sys_call_handler)
 608	/* r1, EPCR, ESR a already saved */
 609	l.sw	PT_GPR2(r1),r2
 610	/* r3-r8 must be saved because syscall restart relies
 611	 * on us being able to restart the syscall args... technically
 612	 * they should be clobbered, otherwise
 613	 */
 614	l.sw    PT_GPR3(r1),r3
 615	/*
 616	 * r4 already saved
 617	 * r4 holds the EEAR address of the fault, use it as screatch reg and
 618	 * then load the original r4
 619	 */
 620	CLEAR_LWA_FLAG(r4)
 621	l.lwz	r4,PT_GPR4(r1)
 622	l.sw    PT_GPR5(r1),r5
 623	l.sw    PT_GPR6(r1),r6
 624	l.sw    PT_GPR7(r1),r7
 625	l.sw    PT_GPR8(r1),r8
 626	l.sw    PT_GPR9(r1),r9
 627	/* r10 already saved */
 628	l.sw    PT_GPR11(r1),r11
 629	/* orig_gpr11 must be set for syscalls */
 630	l.sw    PT_ORIG_GPR11(r1),r11
 631	/* r12,r13 already saved */
 632
 633	/* r14-r28 (even) aren't touched by the syscall fast path below
 634	 * so we don't need to save them.  However, the functions that return
 635	 * to userspace via a call to switch() DO need to save these because
 636	 * switch() effectively clobbers them... saving these registers for
 637	 * such functions is handled in their syscall wrappers (see fork, vfork,
 638	 * and clone, below).
 639
 640	/* r30 is the only register we clobber in the fast path */
 641	/* r30 already saved */
 642/*	l.sw    PT_GPR30(r1),r30 */
 643
 644_syscall_check_trace_enter:
 645	/* syscalls run with interrupts enabled */
 646	TRACE_IRQS_ON_SYSCALL
 647	ENABLE_INTERRUPTS(r29)		// enable interrupts, r29 is temp
 648
 649	/* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
 650	l.lwz	r30,TI_FLAGS(r10)
 651	l.andi	r30,r30,_TIF_SYSCALL_TRACE
 652	l.sfne	r30,r0
 653	l.bf	_syscall_trace_enter
 654	 l.nop
 655
 656_syscall_check:
 657	/* Ensure that the syscall number is reasonable */
 658	l.sfgeui r11,__NR_syscalls
 659	l.bf	_syscall_badsys
 660	 l.nop
 661
 662_syscall_call:
 663	l.movhi r29,hi(sys_call_table)
 664	l.ori   r29,r29,lo(sys_call_table)
 665	l.slli  r11,r11,2
 666	l.add   r29,r29,r11
 667	l.lwz   r29,0(r29)
 668
 669	l.jalr  r29
 670	 l.nop
 671
 672_syscall_return:
 673	/* All syscalls return here... just pay attention to ret_from_fork
 674	 * which does it in a round-about way.
 675	 */
 676	l.sw    PT_GPR11(r1),r11           // save return value
 677
 678#if 0
 679_syscall_debug:
 680	l.movhi r3,hi(_string_syscall_return)
 681	l.ori   r3,r3,lo(_string_syscall_return)
 682	l.ori   r27,r0,2
 683	l.sw    -4(r1),r27
 684	l.sw    -8(r1),r11
 685	l.lwz	r29,PT_ORIG_GPR11(r1)
 686	l.sw    -12(r1),r29
 687	l.lwz	r29,PT_GPR9(r1)
 688	l.sw    -16(r1),r29
 689	l.movhi r27,hi(_printk)
 690	l.ori   r27,r27,lo(_printk)
 691	l.jalr  r27
 692	 l.addi  r1,r1,-16
 693	l.addi  r1,r1,16
 694#endif
 695#if 0
 696_syscall_show_regs:
 697	l.movhi r27,hi(show_registers)
 698	l.ori   r27,r27,lo(show_registers)
 699	l.jalr  r27
 700	 l.or	r3,r1,r1
 701#endif
 702
 703_syscall_check_trace_leave:
 704	/* r30 is a callee-saved register so this should still hold the
 705	 * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
 706	 * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
 707	 */
 708	l.sfne	r30,r0
 709	l.bf	_syscall_trace_leave
 710	 l.nop
 711
 712/* This is where the exception-return code begins... interrupts need to be
 713 * disabled the rest of the way here because we can't afford to miss any
 714 * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
 715
 716_syscall_check_work:
 717#ifdef CONFIG_DEBUG_RSEQ
 718	l.jal	rseq_syscall
 719	 l.ori	r3,r1,0
 720#endif
 721	/* Here we need to disable interrupts */
 722	DISABLE_INTERRUPTS(r27,r29)
 723	TRACE_IRQS_OFF
 724	l.lwz	r30,TI_FLAGS(r10)
 725	l.andi	r30,r30,_TIF_WORK_MASK
 726	l.sfne	r30,r0
 727
 728	l.bnf	_syscall_resume_userspace
 729	 l.nop
 730
 731	/* Work pending follows a different return path, so we need to
 732	 * make sure that all the call-saved registers get into pt_regs
 733	 * before branching...
 734	 */
 735	l.sw    PT_GPR14(r1),r14
 736	l.sw    PT_GPR16(r1),r16
 737	l.sw    PT_GPR18(r1),r18
 738	l.sw    PT_GPR20(r1),r20
 739	l.sw    PT_GPR22(r1),r22
 740	l.sw    PT_GPR24(r1),r24
 741	l.sw    PT_GPR26(r1),r26
 742	l.sw    PT_GPR28(r1),r28
 743
 744	/* _work_pending needs to be called with interrupts disabled */
 745	l.j	_work_pending
 746	 l.nop
 747
 748_syscall_resume_userspace:
 749//	ENABLE_INTERRUPTS(r29)
 750
 751
 752/* This is the hot path for returning to userspace from a syscall.  If there's
 753 * work to be done and the branch to _work_pending was taken above, then the
 754 * return to userspace will be done via the normal exception return path...
 755 * that path restores _all_ registers and will overwrite the "clobbered"
 756 * registers with whatever garbage is in pt_regs -- that's OK because those
 757 * registers are clobbered anyway and because the extra work is insignificant
 758 * in the context of the extra work that _work_pending is doing.
 759
 760/* Once again, syscalls are special and only guarantee to preserve the
 761 * same registers as a normal function call */
 762
 763/* The assumption here is that the registers r14-r28 (even) are untouched and
 764 * don't need to be restored... be sure that that's really the case!
 765 */
 766
 767/* This is still too much... we should only be restoring what we actually
 768 * clobbered... we should even be using 'scratch' (odd) regs above so that
 769 * we don't need to restore anything, hardly...
 770 */
 771
 772	l.lwz	r2,PT_GPR2(r1)
 773
 774	/* Restore args */
 775	/* r3-r8 are technically clobbered, but syscall restart needs these
 776	 * to be restored...
 777	 */
 778	l.lwz	r3,PT_GPR3(r1)
 779	l.lwz	r4,PT_GPR4(r1)
 780	l.lwz	r5,PT_GPR5(r1)
 781	l.lwz	r6,PT_GPR6(r1)
 782	l.lwz	r7,PT_GPR7(r1)
 783	l.lwz	r8,PT_GPR8(r1)
 784
 785	l.lwz	r9,PT_GPR9(r1)
 786	l.lwz	r10,PT_GPR10(r1)
 787	l.lwz	r11,PT_GPR11(r1)
 788
 789	/* r30 is the only register we clobber in the fast path */
 790	l.lwz	r30,PT_GPR30(r1)
 791
 792	/* Here we use r13-r19 (odd) as scratch regs */
 793	l.lwz   r13,PT_PC(r1)
 794	l.lwz   r15,PT_SR(r1)
 795	l.lwz	r1,PT_SP(r1)
 796	/* Interrupts need to be disabled for setting EPCR and ESR
 797	 * so that another interrupt doesn't come in here and clobber
 798	 * them before we can use them for our l.rfe */
 799	DISABLE_INTERRUPTS(r17,r19)
 800	l.mtspr r0,r13,SPR_EPCR_BASE
 801	l.mtspr r0,r15,SPR_ESR_BASE
 802	l.rfe
 803
 804/* End of hot path!
 805 * Keep the below tracing and error handling out of the hot path...
 806*/
 807
 808_syscall_trace_enter:
 809	/* Here we pass pt_regs to do_syscall_trace_enter.  Make sure
 810	 * that function is really getting all the info it needs as
 811	 * pt_regs isn't a complete set of userspace regs, just the
 812	 * ones relevant to the syscall...
 813	 *
 814	 * Note use of delay slot for setting argument.
 815	 */
 816	l.jal	do_syscall_trace_enter
 817	 l.addi	r3,r1,0
 818
 819	/* Restore arguments (not preserved across do_syscall_trace_enter)
 820	 * so that we can do the syscall for real and return to the syscall
 821	 * hot path.
 822	 */
 823	l.lwz	r11,PT_GPR11(r1)
 824	l.lwz	r3,PT_GPR3(r1)
 825	l.lwz	r4,PT_GPR4(r1)
 826	l.lwz	r5,PT_GPR5(r1)
 827	l.lwz	r6,PT_GPR6(r1)
 828	l.lwz	r7,PT_GPR7(r1)
 829
 830	l.j	_syscall_check
 831	 l.lwz	r8,PT_GPR8(r1)
 832
 833_syscall_trace_leave:
 834	l.jal	do_syscall_trace_leave
 835	 l.addi	r3,r1,0
 836
 837	l.j	_syscall_check_work
 838	 l.nop
 839
 840_syscall_badsys:
 841	/* Here we effectively pretend to have executed an imaginary
 842	 * syscall that returns -ENOSYS and then return to the regular
 843	 * syscall hot path.
 844	 * Note that "return value" is set in the delay slot...
 845	 */
 846	l.j	_syscall_return
 847	 l.addi	r11,r0,-ENOSYS
 848
 849/******* END SYSCALL HANDLING *******/
 850
 851/* ---[ 0xd00: Floating Point exception ]-------------------------------- */
 852
 853EXCEPTION_ENTRY(_fpe_trap_handler)
 854	CLEAR_LWA_FLAG(r3)
 855
 856	/* r4: EA of fault (set by EXCEPTION_HANDLE) */
 857	l.jal   do_fpe_trap
 858	 l.addi  r3,r1,0 /* pt_regs */
 859
 860	l.j     _ret_from_exception
 861	 l.nop
 862
 863/* ---[ 0xe00: Trap exception ]------------------------------------------ */
 864
 865EXCEPTION_ENTRY(_trap_handler)
 866	CLEAR_LWA_FLAG(r3)
 867	/* r4: EA of fault (set by EXCEPTION_HANDLE) */
 868	l.jal   do_trap
 869	 l.addi  r3,r1,0 /* pt_regs */
 870
 871	l.j     _ret_from_exception
 872	 l.nop
 873
 874/* ---[ 0xf00: Reserved exception ]-------------------------------------- */
 875
 876UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
 877
 878/* ---[ 0x1000: Reserved exception ]------------------------------------- */
 879
 880UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
 881
 882/* ---[ 0x1100: Reserved exception ]------------------------------------- */
 883
 884UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
 885
 886/* ---[ 0x1200: Reserved exception ]------------------------------------- */
 887
 888UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
 889
 890/* ---[ 0x1300: Reserved exception ]------------------------------------- */
 891
 892UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
 893
 894/* ---[ 0x1400: Reserved exception ]------------------------------------- */
 895
 896UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
 897
 898/* ---[ 0x1500: Reserved exception ]------------------------------------- */
 899
 900UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
 901
 902/* ---[ 0x1600: Reserved exception ]------------------------------------- */
 903
 904UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
 905
 906/* ---[ 0x1700: Reserved exception ]------------------------------------- */
 907
 908UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
 909
 910/* ---[ 0x1800: Reserved exception ]------------------------------------- */
 911
 912UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
 913
 914/* ---[ 0x1900: Reserved exception ]------------------------------------- */
 915
 916UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
 917
 918/* ---[ 0x1a00: Reserved exception ]------------------------------------- */
 919
 920UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
 921
 922/* ---[ 0x1b00: Reserved exception ]------------------------------------- */
 923
 924UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
 925
 926/* ---[ 0x1c00: Reserved exception ]------------------------------------- */
 927
 928UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
 929
 930/* ---[ 0x1d00: Reserved exception ]------------------------------------- */
 931
 932UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
 933
 934/* ---[ 0x1e00: Reserved exception ]------------------------------------- */
 935
 936UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
 937
 938/* ---[ 0x1f00: Reserved exception ]------------------------------------- */
 939
 940UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
 941
 942/* ========================================================[ return ] === */
 943
 944_resume_userspace:
 945	DISABLE_INTERRUPTS(r3,r4)
 946	TRACE_IRQS_OFF
 947	l.lwz	r4,TI_FLAGS(r10)
 948	l.andi	r13,r4,_TIF_WORK_MASK
 949	l.sfeqi	r13,0
 950	l.bf	_restore_all
 951	 l.nop
 952
 953_work_pending:
 954	l.lwz	r5,PT_ORIG_GPR11(r1)
 955	l.sfltsi r5,0
 956	l.bnf	1f
 957	 l.nop
 958	l.andi	r5,r5,0
 9591:
 960	l.jal	do_work_pending
 961	 l.ori	r3,r1,0			/* pt_regs */
 962
 963	l.sfeqi	r11,0
 964	l.bf	_restore_all
 965	 l.nop
 966	l.sfltsi r11,0
 967	l.bnf	1f
 968	 l.nop
 969	l.and	r11,r11,r0
 970	l.ori	r11,r11,__NR_restart_syscall
 971	l.j	_syscall_check_trace_enter
 972	 l.nop
 9731:
 974	l.lwz	r11,PT_ORIG_GPR11(r1)
 975	/* Restore arg registers */
 976	l.lwz	r3,PT_GPR3(r1)
 977	l.lwz	r4,PT_GPR4(r1)
 978	l.lwz	r5,PT_GPR5(r1)
 979	l.lwz	r6,PT_GPR6(r1)
 980	l.lwz	r7,PT_GPR7(r1)
 981	l.j	_syscall_check_trace_enter
 982	 l.lwz	r8,PT_GPR8(r1)
 983
 984_restore_all:
 985#ifdef CONFIG_TRACE_IRQFLAGS
 986	l.lwz	r4,PT_SR(r1)
 987	l.andi	r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
 988	l.sfeq	r3,r0		/* skip trace if irqs were off */
 989	l.bf	skip_hardirqs_on
 990	 l.nop
 991	TRACE_IRQS_ON
 992skip_hardirqs_on:
 993#endif
 994	RESTORE_ALL
 995	/* This returns to userspace code */
 996
 997
 998ENTRY(_ret_from_intr)
 999ENTRY(_ret_from_exception)
1000	l.lwz	r4,PT_SR(r1)
1001	l.andi	r3,r4,SPR_SR_SM
1002	l.sfeqi	r3,0
1003	l.bnf	_restore_all
1004	 l.nop
1005	l.j	_resume_userspace
1006	 l.nop
1007
1008ENTRY(ret_from_fork)
1009	l.jal	schedule_tail
1010	 l.nop
1011
1012	/* Check if we are a kernel thread */
1013	l.sfeqi	r20,0
1014	l.bf	1f
1015	 l.nop
1016
1017	/* ...we are a kernel thread so invoke the requested callback */
1018	l.jalr	r20
1019	 l.or	r3,r22,r0
1020
10211:
1022	/* _syscall_returns expect r11 to contain return value */
1023	l.lwz	r11,PT_GPR11(r1)
1024
1025	/* The syscall fast path return expects call-saved registers
1026	 * r14-r28 to be untouched, so we restore them here as they
1027	 * will have been effectively clobbered when arriving here
1028	 * via the call to switch()
1029	 */
1030	l.lwz	r14,PT_GPR14(r1)
1031	l.lwz	r16,PT_GPR16(r1)
1032	l.lwz	r18,PT_GPR18(r1)
1033	l.lwz	r20,PT_GPR20(r1)
1034	l.lwz	r22,PT_GPR22(r1)
1035	l.lwz	r24,PT_GPR24(r1)
1036	l.lwz	r26,PT_GPR26(r1)
1037	l.lwz	r28,PT_GPR28(r1)
1038
1039	l.j	_syscall_return
1040	 l.nop
1041
1042/* ========================================================[ switch ] === */
1043
1044/*
1045 * This routine switches between two different tasks.  The process
1046 * state of one is saved on its kernel stack.  Then the state
1047 * of the other is restored from its kernel stack.  The memory
1048 * management hardware is updated to the second process's state.
1049 * Finally, we can return to the second process, via the 'return'.
1050 *
1051 * Note: there are two ways to get to the "going out" portion
1052 * of this code; either by coming in via the entry (_switch)
1053 * or via "fork" which must set up an environment equivalent
1054 * to the "_switch" path.  If you change this (or in particular, the
1055 * SAVE_REGS macro), you'll have to change the fork code also.
1056 */
1057
1058
1059/* _switch MUST never lay on page boundry, cause it runs from
1060 * effective addresses and beeing interrupted by iTLB miss would kill it.
1061 * dTLB miss seems to never accour in the bad place since data accesses
1062 * are from task structures which are always page aligned.
1063 *
1064 * The problem happens in RESTORE_ALL where we first set the EPCR
1065 * register, then load the previous register values and only at the end call
1066 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
1067 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
1068 * holds for ESR)
1069 *
1070 * To avoid this problems it is sufficient to align _switch to
1071 * some nice round number smaller than it's size...
1072 */
1073
1074/* ABI rules apply here... we either enter _switch via schedule() or via
1075 * an imaginary call to which we shall return at return_from_fork.  Either
1076 * way, we are a function call and only need to preserve the callee-saved
1077 * registers when we return.  As such, we don't need to save the registers
1078 * on the stack that we won't be returning as they were...
1079 */
1080
1081	.align 0x400
1082ENTRY(_switch)
1083	/* We don't store SR as _switch only gets called in a context where
1084	 * the SR will be the same going in and coming out... */
1085
1086	/* Set up new pt_regs struct for saving task state */
1087	l.addi  r1,r1,-(INT_FRAME_SIZE)
1088
1089	/* No need to store r1/PT_SP as it goes into KSP below */
1090	l.sw    PT_GPR2(r1),r2
1091	l.sw    PT_GPR9(r1),r9
1092
1093	/* Save callee-saved registers to the new pt_regs */
1094	l.sw    PT_GPR14(r1),r14
1095	l.sw    PT_GPR16(r1),r16
1096	l.sw    PT_GPR18(r1),r18
1097	l.sw    PT_GPR20(r1),r20
1098	l.sw    PT_GPR22(r1),r22
1099	l.sw    PT_GPR24(r1),r24
1100	l.sw    PT_GPR26(r1),r26
1101	l.sw    PT_GPR28(r1),r28
1102	l.sw    PT_GPR30(r1),r30
1103
1104	l.addi	r11,r10,0			/* Save old 'current' to 'last' return value*/
1105
1106	/* We use thread_info->ksp for storing the address of the above
1107	 * structure so that we can get back to it later... we don't want
1108	 * to lose the value of thread_info->ksp, though, so store it as
1109	 * pt_regs->sp so that we can easily restore it when we are made
1110	 * live again...
1111	 */
1112
1113	/* Save the old value of thread_info->ksp as pt_regs->sp */
1114	l.lwz	r29,TI_KSP(r10)
1115	l.sw	PT_SP(r1),r29
1116
1117	/* Swap kernel stack pointers */
1118	l.sw    TI_KSP(r10),r1			/* Save old stack pointer */
1119	l.or	r10,r4,r0			/* Set up new current_thread_info */
1120	l.lwz   r1,TI_KSP(r10)			/* Load new stack pointer */
1121
1122	/* Restore the old value of thread_info->ksp */
1123	l.lwz	r29,PT_SP(r1)
1124	l.sw	TI_KSP(r10),r29
1125
1126	/* ...and restore the registers, except r11 because the return value
1127	 * has already been set above.
1128	 */
1129	l.lwz   r2,PT_GPR2(r1)
1130	l.lwz   r9,PT_GPR9(r1)
1131	/* No need to restore r10 */
1132	/* ...and do not restore r11 */
1133
1134	/* Restore callee-saved registers */
1135	l.lwz   r14,PT_GPR14(r1)
1136	l.lwz   r16,PT_GPR16(r1)
1137	l.lwz   r18,PT_GPR18(r1)
1138	l.lwz   r20,PT_GPR20(r1)
1139	l.lwz   r22,PT_GPR22(r1)
1140	l.lwz   r24,PT_GPR24(r1)
1141	l.lwz   r26,PT_GPR26(r1)
1142	l.lwz   r28,PT_GPR28(r1)
1143	l.lwz   r30,PT_GPR30(r1)
1144
1145	/* Unwind stack to pre-switch state */
1146	l.addi  r1,r1,(INT_FRAME_SIZE)
1147
1148	/* Return via the link-register back to where we 'came from', where
1149	 * that may be either schedule(), ret_from_fork(), or
1150	 * ret_from_kernel_thread().  If we are returning to a new thread,
1151	 * we are expected to have set up the arg to schedule_tail already,
1152	 * hence we do so here unconditionally:
1153	 */
1154	l.lwz   r3,TI_TASK(r3)		/* Load 'prev' as schedule_tail arg */
1155	l.jr	r9
1156	 l.nop
1157
1158/* ==================================================================== */
1159
1160/* These all use the delay slot for setting the argument register, so the
1161 * jump is always happening after the l.addi instruction.
1162 *
1163 * These are all just wrappers that don't touch the link-register r9, so the
1164 * return from the "real" syscall function will return back to the syscall
1165 * code that did the l.jal that brought us here.
1166 */
1167
1168/* fork requires that we save all the callee-saved registers because they
1169 * are all effectively clobbered by the call to _switch.  Here we store
1170 * all the registers that aren't touched by the syscall fast path and thus
1171 * weren't saved there.
1172 */
1173
1174_fork_save_extra_regs_and_call:
1175	l.sw    PT_GPR14(r1),r14
1176	l.sw    PT_GPR16(r1),r16
1177	l.sw    PT_GPR18(r1),r18
1178	l.sw    PT_GPR20(r1),r20
1179	l.sw    PT_GPR22(r1),r22
1180	l.sw    PT_GPR24(r1),r24
1181	l.sw    PT_GPR26(r1),r26
1182	l.jr	r29
1183	 l.sw    PT_GPR28(r1),r28
1184
1185ENTRY(__sys_clone)
1186	l.movhi	r29,hi(sys_clone)
1187	l.j	_fork_save_extra_regs_and_call
1188	 l.ori	r29,r29,lo(sys_clone)
1189
1190ENTRY(__sys_clone3)
1191	l.movhi	r29,hi(sys_clone3)
1192	l.j	_fork_save_extra_regs_and_call
1193	 l.ori	r29,r29,lo(sys_clone3)
1194
1195ENTRY(__sys_fork)
1196	l.movhi	r29,hi(sys_fork)
1197	l.j	_fork_save_extra_regs_and_call
1198	 l.ori	r29,r29,lo(sys_fork)
1199
1200ENTRY(sys_rt_sigreturn)
1201	l.jal	_sys_rt_sigreturn
1202	 l.addi	r3,r1,0
1203	l.sfne	r30,r0
1204	l.bnf	_no_syscall_trace
1205	 l.nop
1206	l.jal	do_syscall_trace_leave
1207	 l.addi	r3,r1,0
1208_no_syscall_trace:
1209	l.j	_resume_userspace
1210	 l.nop
1211
1212/* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1213 * The functions takes a variable number of parameters depending on which
1214 * particular flavour of atomic you want... parameter 1 is a flag identifying
1215 * the atomic in question.  Currently, this function implements the
1216 * following variants:
1217 *
1218 * XCHG:
1219 *  @flag: 1
1220 *  @ptr1:
1221 *  @ptr2:
1222 * Atomically exchange the values in pointers 1 and 2.
1223 *
1224 */
1225
1226ENTRY(sys_or1k_atomic)
1227	/* FIXME: This ignores r3 and always does an XCHG */
1228	DISABLE_INTERRUPTS(r17,r19)
1229	l.lwz	r29,0(r4)
1230	l.lwz	r27,0(r5)
1231	l.sw	0(r4),r27
1232	l.sw	0(r5),r29
1233	ENABLE_INTERRUPTS(r17)
1234	l.jr	r9
1235	 l.or	r11,r0,r0
1236
1237/* ============================================================[ EOF ]=== */