pgtable.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * OpenRISC Linux
  4 *
  5 * Linux architectural port borrowing liberally from similar works of
  6 * others.  All original copyrights apply as per the original source
  7 * declaration.
  8 *
  9 * OpenRISC implementation:
 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
 12 * et al.
 13 */
 14
 15/* or1k pgtable.h - macros and functions to manipulate page tables
 16 *
 17 * Based on:
 18 * include/asm-cris/pgtable.h
 19 */
 20
 21#ifndef __ASM_OPENRISC_PGTABLE_H
 22#define __ASM_OPENRISC_PGTABLE_H
 23
 24#include <asm-generic/pgtable-nopmd.h>
 25
 26#ifndef __ASSEMBLER__
 27#include <asm/mmu.h>
 28#include <asm/fixmap.h>
 29
 30/*
 31 * The Linux memory management assumes a three-level page table setup. On
 32 * or1k, we use that, but "fold" the mid level into the top-level page
 33 * table. Since the MMU TLB is software loaded through an interrupt, it
 34 * supports any page table structure, so we could have used a three-level
 35 * setup, but for the amounts of memory we normally use, a two-level is
 36 * probably more efficient.
 37 *
 38 * This file contains the functions and defines necessary to modify and use
 39 * the or1k page table tree.
 40 */
 41
 42extern void paging_init(void);
 43
 44/* Certain architectures need to do special things when pte's
 45 * within a page table are directly modified.  Thus, the following
 46 * hook is made available.
 47 */
 48#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
 49
 50/*
 51 * (pmds are folded into pgds so this doesn't get actually called,
 52 * but the define is needed for a generic inline function.)
 53 */
 54#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
 55
 56#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
 57#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 58#define PGDIR_MASK	(~(PGDIR_SIZE-1))
 59
 60/*
 61 * entries per page directory level: we use a two-level, so
 62 * we don't really have any PMD directory physically.
 63 * pointers are 4 bytes so we can use the page size and
 64 * divide it by 4 (shift by 2).
 65 */
 66#define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
 67
 68#define PTRS_PER_PGD	(1UL << (32-PGDIR_SHIFT))
 69
 70/* calculate how many PGD entries a user-level program can use
 71 * the first mappable virtual address is 0
 72 * (TASK_SIZE is the maximum virtual address space)
 73 */
 74
 75#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 76
 77/*
 78 * Kernels own virtual memory area.
 79 */
 80
 81/*
 82 * The size and location of the vmalloc area are chosen so that modules
 83 * placed in this area aren't more than a 28-bit signed offset from any
 84 * kernel functions that they may need.  This greatly simplifies handling
 85 * of the relocations for l.j and l.jal instructions as we don't need to
 86 * introduce any trampolines for reaching "distant" code.
 87 *
 88 * 64 MB of vmalloc area is comparable to what's available on other arches.
 89 */
 90
 91#define VMALLOC_START	(PAGE_OFFSET-0x04000000UL)
 92#define VMALLOC_END	(PAGE_OFFSET)
 93#define VMALLOC_VMADDR(x) ((unsigned long)(x))
 94
 95/* Define some higher level generic page attributes.
 96 *
 97 * If you change _PAGE_CI definition be sure to change it in
 98 * io.h for ioremap() too.
 99 */
100
101/*
102 * An OR32 PTE looks like this:
103 *
104 * |  31 ... 10 |  9  |  8 ... 6  |  5  |  4  |  3  |  2  |  1  |  0  |
105 *  Phys pg.num    L     PP Index    D     A    WOM   WBC   CI    CC
106 *
107 *  L  : link
108 *  PPI: Page protection index
109 *  D  : Dirty
110 *  A  : Accessed
111 *  WOM: Weakly ordered memory
112 *  WBC: Write-back cache
113 *  CI : Cache inhibit
114 *  CC : Cache coherent
115 *
116 * The protection bits below should correspond to the layout of the actual
117 * PTE as per above
118 */
119
120#define _PAGE_CC       0x001 /* software: pte contains a translation */
121#define _PAGE_CI       0x002 /* cache inhibit          */
122#define _PAGE_WBC      0x004 /* write back cache       */
123#define _PAGE_WOM      0x008 /* weakly ordered memory  */
124
125#define _PAGE_A        0x010 /* accessed               */
126#define _PAGE_D        0x020 /* dirty                  */
127#define _PAGE_URE      0x040 /* user read enable       */
128#define _PAGE_UWE      0x080 /* user write enable      */
129
130#define _PAGE_SRE      0x100 /* superuser read enable  */
131#define _PAGE_SWE      0x200 /* superuser write enable */
132#define _PAGE_EXEC     0x400 /* software: page is executable */
133#define _PAGE_U_SHARED 0x800 /* software: page is shared in user space */
134
135/* 0x001 is cache coherency bit, which should always be set to
136 *       1 - for SMP (when we support it)
137 *       0 - otherwise
138 *
139 * we just reuse this bit in software for _PAGE_PRESENT and
140 * force it to 0 when loading it into TLB.
141 */
142#define _PAGE_PRESENT  _PAGE_CC
143#define _PAGE_USER     _PAGE_URE
144#define _PAGE_WRITE    (_PAGE_UWE | _PAGE_SWE)
145#define _PAGE_DIRTY    _PAGE_D
146#define _PAGE_ACCESSED _PAGE_A
147#define _PAGE_NO_CACHE _PAGE_CI
148#define _PAGE_SHARED   _PAGE_U_SHARED
149#define _PAGE_READ     (_PAGE_URE | _PAGE_SRE)
150
151#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
152#define _PAGE_BASE     (_PAGE_PRESENT | _PAGE_ACCESSED)
153#define _PAGE_ALL      (_PAGE_PRESENT | _PAGE_ACCESSED)
154#define _KERNPG_TABLE \
155	(_PAGE_BASE | _PAGE_SRE | _PAGE_SWE | _PAGE_ACCESSED | _PAGE_DIRTY)
156
157/* We borrow bit 11 to store the exclusive marker in swap PTEs. */
158#define _PAGE_SWP_EXCLUSIVE	_PAGE_U_SHARED
159
160#define PAGE_NONE       __pgprot(_PAGE_ALL)
161#define PAGE_READONLY   __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
162#define PAGE_READONLY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
163#define PAGE_SHARED \
164	__pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
165		 | _PAGE_SHARED)
166#define PAGE_SHARED_X \
167	__pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
168		 | _PAGE_SHARED | _PAGE_EXEC)
169#define PAGE_COPY       __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
170#define PAGE_COPY_X     __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
171
172#define PAGE_KERNEL \
173	__pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
174		 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
175#define PAGE_KERNEL_RO \
176	__pgprot(_PAGE_ALL | _PAGE_SRE \
177		 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
178#define PAGE_KERNEL_NOCACHE \
179	__pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
180		 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC | _PAGE_CI)
181
182/* zero page used for uninitialized stuff */
183extern unsigned long empty_zero_page[2048];
184#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
185
186#define pte_none(x)	(!pte_val(x))
187#define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
188#define pte_clear(mm, addr, xp)	do { pte_val(*(xp)) = 0; } while (0)
189
190#define pmd_none(x)	(!pmd_val(x))
191#define	pmd_bad(x)	((pmd_val(x) & (~PAGE_MASK)) != _KERNPG_TABLE)
192#define pmd_present(x)	(pmd_val(x) & _PAGE_PRESENT)
193#define pmd_clear(xp)	do { pmd_val(*(xp)) = 0; } while (0)
194
195/*
196 * The following only work if pte_present() is true.
197 * Undefined behaviour if not..
198 */
199
200static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_READ; }
201static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
202static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC; }
203static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
204static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
205
206static inline pte_t pte_wrprotect(pte_t pte)
207{
208	pte_val(pte) &= ~(_PAGE_WRITE);
209	return pte;
210}
211
212static inline pte_t pte_rdprotect(pte_t pte)
213{
214	pte_val(pte) &= ~(_PAGE_READ);
215	return pte;
216}
217
218static inline pte_t pte_exprotect(pte_t pte)
219{
220	pte_val(pte) &= ~(_PAGE_EXEC);
221	return pte;
222}
223
224static inline pte_t pte_mkclean(pte_t pte)
225{
226	pte_val(pte) &= ~(_PAGE_DIRTY);
227	return pte;
228}
229
230static inline pte_t pte_mkold(pte_t pte)
231{
232	pte_val(pte) &= ~(_PAGE_ACCESSED);
233	return pte;
234}
235
236static inline pte_t pte_mkwrite_novma(pte_t pte)
237{
238	pte_val(pte) |= _PAGE_WRITE;
239	return pte;
240}
241
242static inline pte_t pte_mkread(pte_t pte)
243{
244	pte_val(pte) |= _PAGE_READ;
245	return pte;
246}
247
248static inline pte_t pte_mkexec(pte_t pte)
249{
250	pte_val(pte) |= _PAGE_EXEC;
251	return pte;
252}
253
254static inline pte_t pte_mkdirty(pte_t pte)
255{
256	pte_val(pte) |= _PAGE_DIRTY;
257	return pte;
258}
259
260static inline pte_t pte_mkyoung(pte_t pte)
261{
262	pte_val(pte) |= _PAGE_ACCESSED;
263	return pte;
264}
265
266/*
267 * Conversion functions: convert a page and protection to a page entry,
268 * and a page entry and page directory to the page they refer to.
269 */
270
271/* What actually goes as arguments to the various functions is less than
272 * obvious, but a rule of thumb is that struct page's goes as struct page *,
273 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
274 * addresses (the 0xc0xxxxxx's) goes as void *'s.
275 */
276
277static inline pte_t __mk_pte(void *page, pgprot_t pgprot)
278{
279	pte_t pte;
280	/* the PTE needs a physical address */
281	pte_val(pte) = __pa(page) | pgprot_val(pgprot);
282	return pte;
283}
284
285#define mk_pte_phys(physpage, pgprot) \
286({                                                                      \
287	pte_t __pte;                                                    \
288									\
289	pte_val(__pte) = (physpage) + pgprot_val(pgprot);               \
290	__pte;                                                          \
291})
292
293static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
294{
295	pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
296	return pte;
297}
298
299
300/*
301 * pte_val refers to a page in the 0x0xxxxxxx physical DRAM interval
302 * __pte_page(pte_val) refers to the "virtual" DRAM interval
303 * pte_pagenr refers to the page-number counted starting from the virtual
304 * DRAM start
305 */
306
307static inline unsigned long __pte_page(pte_t pte)
308{
309	/* the PTE contains a physical address */
310	return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
311}
312
313#define pte_pagenr(pte)         ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
314
315/* permanent address of a page */
316
317#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
318#define pte_page(pte)		(mem_map+pte_pagenr(pte))
319
320/*
321 * only the pte's themselves need to point to physical DRAM (see above)
322 * the pagetable links are purely handled within the kernel SW and thus
323 * don't need the __pa and __va transformations.
324 */
325static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
326{
327	pmd_val(*pmdp) = _KERNPG_TABLE | (unsigned long) ptep;
328}
329
330#define pmd_pfn(pmd)		(pmd_val(pmd) >> PAGE_SHIFT)
331#define pmd_page(pmd)		(pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
332
333static inline unsigned long pmd_page_vaddr(pmd_t pmd)
334{
335	return ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK));
336}
337
338#define __pmd_offset(address) \
339	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
340
341#define PFN_PTE_SHIFT		PAGE_SHIFT
342#define pte_pfn(x)		((unsigned long)(((x).pte)) >> PAGE_SHIFT)
343#define pfn_pte(pfn, prot)  __pte((((pfn) << PAGE_SHIFT)) | pgprot_val(prot))
344
345#define pte_ERROR(e) \
346	printk(KERN_ERR "%s:%d: bad pte %p(%08lx).\n", \
347	       __FILE__, __LINE__, &(e), pte_val(e))
348#define pgd_ERROR(e) \
349	printk(KERN_ERR "%s:%d: bad pgd %p(%08lx).\n", \
350	       __FILE__, __LINE__, &(e), pgd_val(e))
351
352extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
353
354struct vm_area_struct;
355
356static inline void update_tlb(struct vm_area_struct *vma,
357	unsigned long address, pte_t *pte)
358{
359}
360
361extern void update_cache(struct vm_area_struct *vma,
362	unsigned long address, pte_t *pte);
363
364static inline void update_mmu_cache_range(struct vm_fault *vmf,
365		struct vm_area_struct *vma, unsigned long address,
366		pte_t *ptep, unsigned int nr)
367{
368	update_tlb(vma, address, ptep);
369	update_cache(vma, address, ptep);
370}
371
372#define update_mmu_cache(vma, addr, ptep) \
373	update_mmu_cache_range(NULL, vma, addr, ptep, 1)
374
375/* __PHX__ FIXME, SWAP, this probably doesn't work */
376
377/*
378 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
379 * are !pte_none() && !pte_present().
380 *
381 * Format of swap PTEs:
382 *
383 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
384 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
385 *   <-------------- offset ---------------> E <- type --> 0 0 0 0 0
386 *
387 *   E is the exclusive marker that is not stored in swap entries.
388 *   The zero'ed bits include _PAGE_PRESENT.
389 */
390#define __swp_type(x)			(((x).val >> 5) & 0x3f)
391#define __swp_offset(x)			((x).val >> 12)
392#define __swp_entry(type, offset) \
393	((swp_entry_t) { (((type) & 0x3f) << 5) | ((offset) << 12) })
394#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
395#define __swp_entry_to_pte(x)		((pte_t) { (x).val })
396
397static inline bool pte_swp_exclusive(pte_t pte)
398{
399	return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
400}
401
402static inline pte_t pte_swp_mkexclusive(pte_t pte)
403{
404	pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
405	return pte;
406}
407
408static inline pte_t pte_swp_clear_exclusive(pte_t pte)
409{
410	pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
411	return pte;
412}
413
414typedef pte_t *pte_addr_t;
415
416#endif /* __ASSEMBLER__ */
417#endif /* __ASM_OPENRISC_PGTABLE_H */