cpuinfo.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2013 Altera Corporation
  4 * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
  5 *
  6 * Based on cpuinfo.c from microblaze
  7 */
  8
  9#include <linux/kernel.h>
 10#include <linux/init.h>
 11#include <linux/delay.h>
 12#include <linux/seq_file.h>
 13#include <linux/string.h>
 14#include <linux/of.h>
 15#include <asm/cpuinfo.h>
 16
 17struct cpuinfo cpuinfo;
 18
 19#define err_cpu(x) \
 20	pr_err("ERROR: Nios II " x " different for kernel and DTS\n")
 21
 22static inline u32 fcpu(struct device_node *cpu, const char *n)
 23{
 24	u32 val = 0;
 25
 26	of_property_read_u32(cpu, n, &val);
 27
 28	return val;
 29}
 30
 31void __init setup_cpuinfo(void)
 32{
 33	struct device_node *cpu;
 34	const char *str;
 35	int len;
 36
 37	cpu = of_get_cpu_node(0, NULL);
 38	if (!cpu)
 39		panic("%s: No CPU found in devicetree!\n", __func__);
 40
 41	if (!of_property_read_bool(cpu, "altr,has-initda"))
 42		panic("initda instruction is unimplemented. Please update your "
 43			"hardware system to have more than 4-byte line data "
 44			"cache\n");
 45
 46	cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency");
 47
 48	str = of_get_property(cpu, "altr,implementation", &len);
 49	strscpy(cpuinfo.cpu_impl, str ?: "<unknown>");
 50
 51	cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div");
 52	cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul");
 53	cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx");
 54	cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx");
 55	cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx");
 56	cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu");
 57
 58	if (IS_ENABLED(CONFIG_NIOS2_HW_DIV_SUPPORT) && !cpuinfo.has_div)
 59		err_cpu("DIV");
 60
 61	if (IS_ENABLED(CONFIG_NIOS2_HW_MUL_SUPPORT) && !cpuinfo.has_mul)
 62		err_cpu("MUL");
 63
 64	if (IS_ENABLED(CONFIG_NIOS2_HW_MULX_SUPPORT) && !cpuinfo.has_mulx)
 65		err_cpu("MULX");
 66
 67	if (IS_ENABLED(CONFIG_NIOS2_BMX_SUPPORT) && !cpuinfo.has_bmx)
 68		err_cpu("BMX");
 69
 70	if (IS_ENABLED(CONFIG_NIOS2_CDX_SUPPORT) && !cpuinfo.has_cdx)
 71		err_cpu("CDX");
 72
 73	cpuinfo.tlb_num_ways = fcpu(cpu, "altr,tlb-num-ways");
 74	if (!cpuinfo.tlb_num_ways)
 75		panic("altr,tlb-num-ways can't be 0. Please check your hardware "
 76			"system\n");
 77	cpuinfo.icache_line_size = fcpu(cpu, "icache-line-size");
 78	cpuinfo.icache_size = fcpu(cpu, "icache-size");
 79	if (CONFIG_NIOS2_ICACHE_SIZE != cpuinfo.icache_size)
 80		pr_warn("Warning: icache size configuration mismatch "
 81		"(0x%x vs 0x%x) of CONFIG_NIOS2_ICACHE_SIZE vs "
 82		"device tree icache-size\n",
 83		CONFIG_NIOS2_ICACHE_SIZE, cpuinfo.icache_size);
 84
 85	cpuinfo.dcache_line_size = fcpu(cpu, "dcache-line-size");
 86	if (CONFIG_NIOS2_DCACHE_LINE_SIZE != cpuinfo.dcache_line_size)
 87		pr_warn("Warning: dcache line size configuration mismatch "
 88		"(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_LINE_SIZE vs "
 89		"device tree dcache-line-size\n",
 90		CONFIG_NIOS2_DCACHE_LINE_SIZE, cpuinfo.dcache_line_size);
 91	cpuinfo.dcache_size = fcpu(cpu, "dcache-size");
 92	if (CONFIG_NIOS2_DCACHE_SIZE != cpuinfo.dcache_size)
 93		pr_warn("Warning: dcache size configuration mismatch "
 94			"(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_SIZE vs "
 95			"device tree dcache-size\n",
 96			CONFIG_NIOS2_DCACHE_SIZE, cpuinfo.dcache_size);
 97
 98	cpuinfo.tlb_pid_num_bits = fcpu(cpu, "altr,pid-num-bits");
 99	cpuinfo.tlb_num_ways_log2 = ilog2(cpuinfo.tlb_num_ways);
100	cpuinfo.tlb_num_entries = fcpu(cpu, "altr,tlb-num-entries");
101	cpuinfo.tlb_num_lines = cpuinfo.tlb_num_entries / cpuinfo.tlb_num_ways;
102	cpuinfo.tlb_ptr_sz = fcpu(cpu, "altr,tlb-ptr-sz");
103
104	cpuinfo.reset_addr = fcpu(cpu, "altr,reset-addr");
105	cpuinfo.exception_addr = fcpu(cpu, "altr,exception-addr");
106	cpuinfo.fast_tlb_miss_exc_addr = fcpu(cpu, "altr,fast-tlb-miss-addr");
107
108	of_node_put(cpu);
109}
110
111#ifdef CONFIG_PROC_FS
112
113/*
114 * Get CPU information for use by the procfs.
115 */
116static int show_cpuinfo(struct seq_file *m, void *v)
117{
118	const u32 clockfreq = cpuinfo.cpu_clock_freq;
119
120	seq_printf(m,
121		   "CPU:\t\tNios II/%s\n"
122		   "REV:\t\t%i\n"
123		   "MMU:\t\t%s\n"
124		   "FPU:\t\tnone\n"
125		   "Clocking:\t%u.%02u MHz\n"
126		   "BogoMips:\t%lu.%02lu\n"
127		   "Calibration:\t%lu loops\n",
128		   cpuinfo.cpu_impl,
129		   CONFIG_NIOS2_ARCH_REVISION,
130		   cpuinfo.mmu ? "present" : "none",
131		   clockfreq / 1000000, (clockfreq / 100000) % 10,
132		   (loops_per_jiffy * HZ) / 500000,
133		   ((loops_per_jiffy * HZ) / 5000) % 100,
134		   (loops_per_jiffy * HZ));
135
136	seq_printf(m,
137		   "HW:\n"
138		   " MUL:\t\t%s\n"
139		   " MULX:\t\t%s\n"
140		   " DIV:\t\t%s\n"
141		   " BMX:\t\t%s\n"
142		   " CDX:\t\t%s\n",
143		   str_yes_no(cpuinfo.has_mul),
144		   str_yes_no(cpuinfo.has_mulx),
145		   str_yes_no(cpuinfo.has_div),
146		   str_yes_no(cpuinfo.has_bmx),
147		   str_yes_no(cpuinfo.has_cdx));
148
149	seq_printf(m,
150		   "Icache:\t\t%ukB, line length: %u\n",
151		   cpuinfo.icache_size >> 10,
152		   cpuinfo.icache_line_size);
153
154	seq_printf(m,
155		   "Dcache:\t\t%ukB, line length: %u\n",
156		   cpuinfo.dcache_size >> 10,
157		   cpuinfo.dcache_line_size);
158
159	seq_printf(m,
160		   "TLB:\t\t%u ways, %u entries, %u PID bits\n",
161		   cpuinfo.tlb_num_ways,
162		   cpuinfo.tlb_num_entries,
163		   cpuinfo.tlb_pid_num_bits);
164
165	return 0;
166}
167
168static void *cpuinfo_start(struct seq_file *m, loff_t *pos)
169{
170	unsigned long i = *pos;
171
172	return i < num_possible_cpus() ? (void *) (i + 1) : NULL;
173}
174
175static void *cpuinfo_next(struct seq_file *m, void *v, loff_t *pos)
176{
177	++*pos;
178	return cpuinfo_start(m, pos);
179}
180
181static void cpuinfo_stop(struct seq_file *m, void *v)
182{
183}
184
185const struct seq_operations cpuinfo_op = {
186	.start	= cpuinfo_start,
187	.next	= cpuinfo_next,
188	.stop	= cpuinfo_stop,
189	.show	= show_cpuinfo
190};
191
192#endif /* CONFIG_PROC_FS */