FILE
pci-rt3883.c
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linux-6.19.14/arch/mips/pci/pci-rt3883.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Ralink RT3662/RT3883 SoC PCI support 4 * 5 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 6 * 7 * Parts of this file are based on Ralink's 2.6.21 BSP 8 */ 9 10#include <linux/types.h> 11#include <linux/pci.h> 12#include <linux/io.h> 13#include <linux/init.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/irqdomain.h> 17#include <linux/of.h> 18#include <linux/of_irq.h> 19#include <linux/of_pci.h> 20#include <linux/platform_device.h> 21 22#include <asm/mach-ralink/rt3883.h> 23#include <asm/mach-ralink/ralink_regs.h> 24 25#define RT3883_MEMORY_BASE 0x00000000 26#define RT3883_MEMORY_SIZE 0x02000000 27 28#define RT3883_PCI_REG_PCICFG 0x00 29#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf 30#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 31#define RT3883_PCICFG_PCIRST BIT(1) 32#define RT3883_PCI_REG_PCIRAW 0x04 33#define RT3883_PCI_REG_PCIINT 0x08 34#define RT3883_PCI_REG_PCIENA 0x0c 35 36#define RT3883_PCI_REG_CFGADDR 0x20 37#define RT3883_PCI_REG_CFGDATA 0x24 38#define RT3883_PCI_REG_MEMBASE 0x28 39#define RT3883_PCI_REG_IOBASE 0x2c 40#define RT3883_PCI_REG_ARBCTL 0x80 41 42#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) 43#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) 44#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) 45#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) 46#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) 47#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) 48#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) 49 50#define RT3883_PCI_MODE_NONE 0 51#define RT3883_PCI_MODE_PCI BIT(0) 52#define RT3883_PCI_MODE_PCIE BIT(1) 53#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) 54 55#define RT3883_PCI_IRQ_COUNT 32 56 57#define RT3883_P2P_BR_DEVNUM 1 58 59struct rt3883_pci_controller { 60 void __iomem *base; 61 62 struct device_node *intc_of_node; 63 struct irq_domain *irq_domain; 64 65 struct pci_controller pci_controller; 66 struct resource io_res; 67 struct resource mem_res; 68 69 bool pcie_ready; 70}; 71 72static inline struct rt3883_pci_controller * 73pci_bus_to_rt3883_controller(struct pci_bus *bus) 74{ 75 struct pci_controller *hose; 76 77 hose = (struct pci_controller *) bus->sysdata; 78 return container_of(hose, struct rt3883_pci_controller, pci_controller); 79} 80 81static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, 82 unsigned reg) 83{ 84 return ioread32(rpc->base + reg); 85} 86 87static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, 88 u32 val, unsigned reg) 89{ 90 iowrite32(val, rpc->base + reg); 91} 92 93static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, 94 unsigned int func, unsigned int where) 95{ 96 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 97 0x80000000; 98} 99 100static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, 101 unsigned bus, unsigned slot, 102 unsigned func, unsigned reg) 103{ 104 u32 address; 105 106 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 107 108 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 109 110 return rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 111} 112 113static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, 114 unsigned bus, unsigned slot, 115 unsigned func, unsigned reg, u32 val) 116{ 117 u32 address; 118 119 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 120 121 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 122 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); 123} 124 125static void rt3883_pci_irq_handler(struct irq_desc *desc) 126{ 127 struct rt3883_pci_controller *rpc; 128 u32 pending; 129 130 rpc = irq_desc_get_handler_data(desc); 131 132 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & 133 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 134 135 if (!pending) { 136 spurious_interrupt(); 137 return; 138 } 139 140 while (pending) { 141 unsigned bit = __ffs(pending); 142 143 generic_handle_domain_irq(rpc->irq_domain, bit); 144 145 pending &= ~BIT(bit); 146 } 147} 148 149static void rt3883_pci_irq_unmask(struct irq_data *d) 150{ 151 struct rt3883_pci_controller *rpc; 152 u32 t; 153 154 rpc = irq_data_get_irq_chip_data(d); 155 156 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 157 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 158 /* flush write */ 159 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 160} 161 162static void rt3883_pci_irq_mask(struct irq_data *d) 163{ 164 struct rt3883_pci_controller *rpc; 165 u32 t; 166 167 rpc = irq_data_get_irq_chip_data(d); 168 169 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 170 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 171 /* flush write */ 172 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 173} 174 175static struct irq_chip rt3883_pci_irq_chip = { 176 .name = "RT3883 PCI", 177 .irq_mask = rt3883_pci_irq_mask, 178 .irq_unmask = rt3883_pci_irq_unmask, 179 .irq_mask_ack = rt3883_pci_irq_mask, 180}; 181 182static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, 183 irq_hw_number_t hw) 184{ 185 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); 186 irq_set_chip_data(irq, d->host_data); 187 188 return 0; 189} 190 191static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { 192 .map = rt3883_pci_irq_map, 193 .xlate = irq_domain_xlate_onecell, 194}; 195 196static int rt3883_pci_irq_init(struct device *dev, 197 struct rt3883_pci_controller *rpc) 198{ 199 int irq; 200 201 irq = irq_of_parse_and_map(rpc->intc_of_node, 0); 202 if (irq == 0) { 203 dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node); 204 return -EINVAL; 205 } 206 207 /* disable all interrupts */ 208 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); 209 210 rpc->irq_domain = 211 irq_domain_create_linear(of_fwnode_handle(rpc->intc_of_node), 212 RT3883_PCI_IRQ_COUNT, 213 &rt3883_pci_irq_domain_ops, 214 rpc); 215 if (!rpc->irq_domain) { 216 dev_err(dev, "unable to add IRQ domain\n"); 217 return -ENODEV; 218 } 219 220 irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc); 221 222 return 0; 223} 224 225static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, 226 int where, int size, u32 *val) 227{ 228 struct rt3883_pci_controller *rpc; 229 u32 address; 230 u32 data; 231 232 rpc = pci_bus_to_rt3883_controller(bus); 233 234 if (!rpc->pcie_ready && bus->number == 1) 235 return PCIBIOS_DEVICE_NOT_FOUND; 236 237 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 238 PCI_FUNC(devfn), where); 239 240 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 241 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 242 243 switch (size) { 244 case 1: 245 *val = (data >> ((where & 3) << 3)) & 0xff; 246 break; 247 case 2: 248 *val = (data >> ((where & 3) << 3)) & 0xffff; 249 break; 250 case 4: 251 *val = data; 252 break; 253 } 254 255 return PCIBIOS_SUCCESSFUL; 256} 257 258static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, 259 int where, int size, u32 val) 260{ 261 struct rt3883_pci_controller *rpc; 262 u32 address; 263 u32 data; 264 265 rpc = pci_bus_to_rt3883_controller(bus); 266 267 if (!rpc->pcie_ready && bus->number == 1) 268 return PCIBIOS_DEVICE_NOT_FOUND; 269 270 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 271 PCI_FUNC(devfn), where); 272 273 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 274 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 275 276 switch (size) { 277 case 1: 278 data = (data & ~(0xff << ((where & 3) << 3))) | 279 (val << ((where & 3) << 3)); 280 break; 281 case 2: 282 data = (data & ~(0xffff << ((where & 3) << 3))) | 283 (val << ((where & 3) << 3)); 284 break; 285 case 4: 286 data = val; 287 break; 288 } 289 290 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); 291 292 return PCIBIOS_SUCCESSFUL; 293} 294 295static struct pci_ops rt3883_pci_ops = { 296 .read = rt3883_pci_config_read, 297 .write = rt3883_pci_config_write, 298}; 299 300static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) 301{ 302 u32 syscfg1; 303 u32 rstctrl; 304 u32 clkcfg1; 305 u32 t; 306 307 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 308 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); 309 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 310 311 if (mode & RT3883_PCI_MODE_PCIE) { 312 rstctrl |= RT3883_RSTCTRL_PCIE; 313 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 314 315 /* setup PCI PAD drive mode */ 316 syscfg1 &= ~(0x30); 317 syscfg1 |= (2 << 4); 318 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 319 320 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 321 t &= ~BIT(31); 322 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 323 324 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 325 t &= 0x80ffffff; 326 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 327 328 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 329 t |= 0xa << 24; 330 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 331 332 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 333 t |= BIT(31); 334 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 335 336 msleep(50); 337 338 rstctrl &= ~RT3883_RSTCTRL_PCIE; 339 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 340 } 341 342 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); 343 344 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); 345 346 if (mode & RT3883_PCI_MODE_PCI) { 347 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; 348 rstctrl &= ~RT3883_RSTCTRL_PCI; 349 } 350 351 if (mode & RT3883_PCI_MODE_PCIE) { 352 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; 353 rstctrl &= ~RT3883_RSTCTRL_PCIE; 354 } 355 356 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 357 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 358 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); 359 360 msleep(500); 361 362 /* 363 * setup the device number of the P2P bridge 364 * and de-assert the reset line 365 */ 366 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); 367 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); 368 369 /* flush write */ 370 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); 371 msleep(500); 372 373 if (mode & RT3883_PCI_MODE_PCIE) { 374 msleep(500); 375 376 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); 377 378 rpc->pcie_ready = t & BIT(0); 379 380 if (!rpc->pcie_ready) { 381 /* reset the PCIe block */ 382 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 383 t |= RT3883_RSTCTRL_PCIE; 384 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 385 t &= ~RT3883_RSTCTRL_PCIE; 386 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 387 388 /* turn off PCIe clock */ 389 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 390 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; 391 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); 392 393 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 394 t &= ~0xf000c080; 395 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 396 } 397 } 398 399 /* enable PCI arbiter */ 400 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); 401} 402 403static int rt3883_pci_probe(struct platform_device *pdev) 404{ 405 struct rt3883_pci_controller *rpc; 406 struct device *dev = &pdev->dev; 407 struct device_node *np = dev->of_node; 408 struct device_node *child; 409 u32 val; 410 int err; 411 int mode; 412 413 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 414 if (!rpc) 415 return -ENOMEM; 416 417 rpc->base = devm_platform_ioremap_resource(pdev, 0); 418 if (IS_ERR(rpc->base)) 419 return PTR_ERR(rpc->base); 420 421 /* find the interrupt controller child node */ 422 for_each_child_of_node(np, child) { 423 if (of_property_read_bool(child, "interrupt-controller")) { 424 rpc->intc_of_node = child; 425 break; 426 } 427 } 428 429 if (!rpc->intc_of_node) { 430 dev_err(dev, "%pOF has no %s child node", 431 np, "interrupt controller"); 432 return -EINVAL; 433 } 434 435 /* find the PCI host bridge child node */ 436 for_each_child_of_node(np, child) { 437 if (of_node_is_type(child, "pci")) { 438 rpc->pci_controller.of_node = child; 439 break; 440 } 441 } 442 443 if (!rpc->pci_controller.of_node) { 444 dev_err(dev, "%pOF has no %s child node", 445 np, "PCI host bridge"); 446 err = -EINVAL; 447 goto err_put_intc_node; 448 } 449 450 mode = RT3883_PCI_MODE_NONE; 451 for_each_available_child_of_node(rpc->pci_controller.of_node, child) { 452 int devfn; 453 454 if (!of_node_is_type(child, "pci")) 455 continue; 456 457 devfn = of_pci_get_devfn(child); 458 if (devfn < 0) 459 continue; 460 461 switch (PCI_SLOT(devfn)) { 462 case 1: 463 mode |= RT3883_PCI_MODE_PCIE; 464 break; 465 466 case 17: 467 case 18: 468 mode |= RT3883_PCI_MODE_PCI; 469 break; 470 } 471 } 472 473 if (mode == RT3883_PCI_MODE_NONE) { 474 dev_err(dev, "unable to determine PCI mode\n"); 475 err = -EINVAL; 476 goto err_put_hb_node; 477 } 478 479 dev_info(dev, "mode:%s%s\n", 480 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", 481 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); 482 483 rt3883_pci_preinit(rpc, mode); 484 485 rpc->pci_controller.pci_ops = &rt3883_pci_ops; 486 rpc->pci_controller.io_resource = &rpc->io_res; 487 rpc->pci_controller.mem_resource = &rpc->mem_res; 488 489 /* Load PCI I/O and memory resources from DT */ 490 pci_load_of_ranges(&rpc->pci_controller, 491 rpc->pci_controller.of_node); 492 493 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); 494 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); 495 496 ioport_resource.start = rpc->io_res.start; 497 ioport_resource.end = rpc->io_res.end; 498 499 /* PCI */ 500 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); 501 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); 502 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); 503 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); 504 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); 505 506 /* PCIe */ 507 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); 508 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); 509 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); 510 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); 511 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); 512 513 err = rt3883_pci_irq_init(dev, rpc); 514 if (err) 515 goto err_put_hb_node; 516 517 /* PCIe */ 518 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); 519 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 520 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); 521 522 /* PCI */ 523 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); 524 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 525 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); 526 527 if (mode == RT3883_PCI_MODE_PCIE) { 528 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); 529 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); 530 531 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 532 PCI_BASE_ADDRESS_0, 533 RT3883_MEMORY_BASE); 534 /* flush write */ 535 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 536 PCI_BASE_ADDRESS_0); 537 } else { 538 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 539 PCI_IO_BASE, 0x00000101); 540 } 541 542 register_pci_controller(&rpc->pci_controller); 543 544 return 0; 545 546err_put_hb_node: 547 of_node_put(rpc->pci_controller.of_node); 548err_put_intc_node: 549 of_node_put(rpc->intc_of_node); 550 return err; 551} 552 553int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 554{ 555 return of_irq_parse_and_map_pci(dev, slot, pin); 556} 557 558int pcibios_plat_dev_init(struct pci_dev *dev) 559{ 560 return 0; 561} 562 563static const struct of_device_id rt3883_pci_ids[] = { 564 { .compatible = "ralink,rt3883-pci" }, 565 {}, 566}; 567 568static struct platform_driver rt3883_pci_driver = { 569 .probe = rt3883_pci_probe, 570 .driver = { 571 .name = "rt3883-pci", 572 .of_match_table = of_match_ptr(rt3883_pci_ids), 573 }, 574}; 575 576static int __init rt3883_pci_init(void) 577{ 578 return platform_driver_register(&rt3883_pci_driver); 579} 580 581postcore_initcall(rt3883_pci_init);
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