cs5536_ehci.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * the EHCI Virtual Support Module of AMD CS5536
  4 *
  5 * Copyright (C) 2007 Lemote, Inc.
  6 * Author : jlliu, liujl@lemote.com
  7 *
  8 * Copyright (C) 2009 Lemote, Inc.
  9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
 10 */
 11
 12#include <cs5536/cs5536.h>
 13#include <cs5536/cs5536_pci.h>
 14
 15void pci_ehci_write_reg(int reg, u32 value)
 16{
 17	u32 hi = 0, lo = value;
 18
 19	switch (reg) {
 20	case PCI_COMMAND:
 21		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
 22		if (value & PCI_COMMAND_MASTER)
 23			hi |= PCI_COMMAND_MASTER;
 24		else
 25			hi &= ~PCI_COMMAND_MASTER;
 26
 27		if (value & PCI_COMMAND_MEMORY)
 28			hi |= PCI_COMMAND_MEMORY;
 29		else
 30			hi &= ~PCI_COMMAND_MEMORY;
 31		_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
 32		break;
 33	case PCI_STATUS:
 34		if (value & PCI_STATUS_PARITY) {
 35			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
 36			if (lo & SB_PARE_ERR_FLAG) {
 37				lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
 38				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
 39			}
 40		}
 41		break;
 42	case PCI_BAR0_REG:
 43		if (value == PCI_BAR_RANGE_MASK) {
 44			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
 45			lo |= SOFT_BAR_EHCI_FLAG;
 46			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
 47		} else if ((value & 0x01) == 0x00) {
 48			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
 49			lo = value;
 50			_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
 51
 52			value &= 0xfffffff0;
 53			hi = 0x40000000 | ((value & 0xff000000) >> 24);
 54			lo = 0x000fffff | ((value & 0x00fff000) << 8);
 55			_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
 56		}
 57		break;
 58	case PCI_EHCI_LEGSMIEN_REG:
 59		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
 60		hi &= 0x003f0000;
 61		hi |= (value & 0x3f) << 16;
 62		_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
 63		break;
 64	case PCI_EHCI_FLADJ_REG:
 65		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
 66		hi &= ~0x00003f00;
 67		hi |= value & 0x00003f00;
 68		_wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
 69		break;
 70	default:
 71		break;
 72	}
 73}
 74
 75u32 pci_ehci_read_reg(int reg)
 76{
 77	u32 conf_data = 0;
 78	u32 hi, lo;
 79
 80	switch (reg) {
 81	case PCI_VENDOR_ID:
 82		conf_data =
 83		    CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
 84		break;
 85	case PCI_COMMAND:
 86		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
 87		if (hi & PCI_COMMAND_MASTER)
 88			conf_data |= PCI_COMMAND_MASTER;
 89		if (hi & PCI_COMMAND_MEMORY)
 90			conf_data |= PCI_COMMAND_MEMORY;
 91		break;
 92	case PCI_STATUS:
 93		conf_data |= PCI_STATUS_66MHZ;
 94		conf_data |= PCI_STATUS_FAST_BACK;
 95		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
 96		if (lo & SB_PARE_ERR_FLAG)
 97			conf_data |= PCI_STATUS_PARITY;
 98		conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
 99		break;
100	case PCI_CLASS_REVISION:
101		_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
102		conf_data = lo & 0x000000ff;
103		conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
104		break;
105	case PCI_CACHE_LINE_SIZE:
106		conf_data =
107		    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
108					    PCI_NORMAL_LATENCY_TIMER);
109		break;
110	case PCI_BAR0_REG:
111		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
112		if (lo & SOFT_BAR_EHCI_FLAG) {
113			conf_data = CS5536_EHCI_RANGE |
114			    PCI_BASE_ADDRESS_SPACE_MEMORY;
115			lo &= ~SOFT_BAR_EHCI_FLAG;
116			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
117		} else {
118			_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
119			conf_data = lo & 0xfffff000;
120		}
121		break;
122	case PCI_CARDBUS_CIS:
123		conf_data = PCI_CARDBUS_CIS_POINTER;
124		break;
125	case PCI_SUBSYSTEM_VENDOR_ID:
126		conf_data =
127		    CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
128		break;
129	case PCI_ROM_ADDRESS:
130		conf_data = PCI_EXPANSION_ROM_BAR;
131		break;
132	case PCI_CAPABILITY_LIST:
133		conf_data = PCI_CAPLIST_USB_POINTER;
134		break;
135	case PCI_INTERRUPT_LINE:
136		conf_data =
137		    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
138		break;
139	case PCI_EHCI_LEGSMIEN_REG:
140		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
141		conf_data = (hi & 0x003f0000) >> 16;
142		break;
143	case PCI_EHCI_LEGSMISTS_REG:
144		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
145		conf_data = (hi & 0x3f000000) >> 24;
146		break;
147	case PCI_EHCI_FLADJ_REG:
148		_rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
149		conf_data = hi & 0x00003f00;
150		break;
151	default:
152		break;
153	}
154
155	return conf_data;
156}