smp-cps.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2013 Imagination Technologies
  4 * Author: Paul Burton <paul.burton@mips.com>
  5 */
  6
  7#include <linux/cpu.h>
  8#include <linux/delay.h>
  9#include <linux/io.h>
 10#include <linux/memblock.h>
 11#include <linux/sched/task_stack.h>
 12#include <linux/sched/hotplug.h>
 13#include <linux/slab.h>
 14#include <linux/smp.h>
 15#include <linux/types.h>
 16#include <linux/irq.h>
 17
 18#include <asm/bcache.h>
 19#include <asm/mips-cps.h>
 20#include <asm/mips_mt.h>
 21#include <asm/mipsregs.h>
 22#include <asm/pm-cps.h>
 23#include <asm/r4kcache.h>
 24#include <asm/regdef.h>
 25#include <asm/smp.h>
 26#include <asm/smp-cps.h>
 27#include <asm/time.h>
 28#include <asm/uasm.h>
 29
 30#define BEV_VEC_SIZE	0x500
 31#define BEV_VEC_ALIGN	0x1000
 32
 33enum label_id {
 34	label_not_nmi = 1,
 35};
 36
 37UASM_L_LA(_not_nmi)
 38
 39static u64 core_entry_reg;
 40static phys_addr_t cps_vec_pa;
 41
 42struct cluster_boot_config *mips_cps_cluster_bootcfg;
 43
 44static void power_up_other_cluster(unsigned int cluster)
 45{
 46	u32 stat, seq_state;
 47	unsigned int timeout;
 48
 49	mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0,
 50			   CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 51	stat = read_cpc_co_stat_conf();
 52	mips_cm_unlock_other();
 53
 54	seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
 55	seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 56	if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5)
 57		return;
 58
 59	/* Set endianness & power up the CM */
 60	mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
 61	write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN));
 62	write_cpc_redir_pwrup_ctl(1);
 63	mips_cm_unlock_other();
 64
 65	/* Wait for the CM to start up */
 66	timeout = 1000;
 67	mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0,
 68			   CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 69	while (1) {
 70		stat = read_cpc_co_stat_conf();
 71		seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
 72		seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 73		if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5)
 74			break;
 75
 76		if (timeout) {
 77			mdelay(1);
 78			timeout--;
 79		} else {
 80			pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n",
 81				cluster, stat);
 82			mdelay(1000);
 83		}
 84	}
 85
 86	mips_cm_unlock_other();
 87}
 88
 89static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
 90{
 91	return min(smp_max_threads, mips_cps_numvps(cluster, core));
 92}
 93
 94static void __init *mips_cps_build_core_entry(void *addr)
 95{
 96	extern void (*nmi_handler)(void);
 97	u32 *p = addr;
 98	u32 val;
 99	struct uasm_label labels[2];
100	struct uasm_reloc relocs[2];
101	struct uasm_label *l = labels;
102	struct uasm_reloc *r = relocs;
103
104	memset(labels, 0, sizeof(labels));
105	memset(relocs, 0, sizeof(relocs));
106
107	uasm_i_mfc0(&p, GPR_K0, C0_STATUS);
108	UASM_i_LA(&p, GPR_T9, ST0_NMI);
109	uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9);
110
111	uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi);
112	uasm_i_nop(&p);
113	UASM_i_LA(&p, GPR_K0, (long)&nmi_handler);
114
115	uasm_l_not_nmi(&l, p);
116
117	val = CAUSEF_IV;
118	uasm_i_lui(&p, GPR_K0, val >> 16);
119	uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);
120	uasm_i_mtc0(&p, GPR_K0, C0_CAUSE);
121	val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64;
122	uasm_i_lui(&p, GPR_K0, val >> 16);
123	uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);
124	uasm_i_mtc0(&p, GPR_K0, C0_STATUS);
125	uasm_i_ehb(&p);
126	uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK);
127	UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base);
128#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT)
129	UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot)));
130#else
131	UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot)));
132#endif
133	uasm_i_jr(&p, GPR_T9);
134	uasm_i_nop(&p);
135
136	uasm_resolve_relocs(relocs, labels);
137
138	return p;
139}
140
141static bool __init check_64bit_reset(void)
142{
143	bool cx_64bit_reset = false;
144
145	mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
146	write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE);
147	if ((read_gcr_co_reset64_base() & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) ==
148	    CM_GCR_Cx_RESET64_BASE_BEVEXCBASE)
149		cx_64bit_reset = true;
150	mips_cm_unlock_other();
151
152	return cx_64bit_reset;
153}
154
155static int __init allocate_cps_vecs(void)
156{
157	/* Try to allocate in KSEG1 first */
158	cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
159						0x0, CSEGX_SIZE - 1);
160
161	if (cps_vec_pa)
162		core_entry_reg = CKSEG1ADDR(cps_vec_pa) &
163					CM_GCR_Cx_RESET_BASE_BEVEXCBASE;
164
165	if (!cps_vec_pa && mips_cm_is64) {
166		phys_addr_t end;
167
168		if (check_64bit_reset()) {
169			pr_info("VP Local Reset Exception Base support 47 bits address\n");
170			end = MEMBLOCK_ALLOC_ANYWHERE;
171		} else {
172			end = SZ_4G - 1;
173		}
174		cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 0, end);
175		if (cps_vec_pa) {
176			if (check_64bit_reset())
177				core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) |
178					CM_GCR_Cx_RESET_BASE_MODE;
179			else
180				core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) |
181					CM_GCR_Cx_RESET_BASE_MODE;
182		}
183	}
184
185	if (!cps_vec_pa)
186		return -ENOMEM;
187
188	return 0;
189}
190
191static void __init setup_cps_vecs(void)
192{
193	void *cps_vec;
194
195	cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa);
196	mips_cps_build_core_entry(cps_vec);
197
198	memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
199	memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
200	memcpy(cps_vec + 0x300, &excep_cache, 0x80);
201	memcpy(cps_vec + 0x380, &excep_genex, 0x80);
202	memcpy(cps_vec + 0x400, &excep_intex, 0x80);
203	memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
204
205	/* Make sure no prefetched data in cache */
206	blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE);
207	bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE);
208	__sync();
209}
210
211static void __init cps_smp_setup(void)
212{
213	unsigned int nclusters, ncores, nvpes, core_vpes;
214	int cl, c, v;
215
216	/* Detect & record VPE topology */
217	nvpes = 0;
218	nclusters = mips_cps_numclusters();
219	pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
220	for (cl = 0; cl < nclusters; cl++) {
221		if (cl > 0)
222			pr_cont(",");
223		pr_cont("{");
224
225		if (mips_cm_revision() >= CM_REV_CM3_5)
226			power_up_other_cluster(cl);
227
228		ncores = mips_cps_numcores(cl);
229		for (c = 0; c < ncores; c++) {
230			core_vpes = core_vpe_count(cl, c);
231
232			if (c > 0)
233				pr_cont(",");
234			pr_cont("%u", core_vpes);
235
236			/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
237			if (!cl && !c)
238				smp_num_siblings = core_vpes;
239			cpumask_set_cpu(nvpes, &__cpu_primary_thread_mask);
240
241			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
242				cpu_set_cluster(&cpu_data[nvpes + v], cl);
243				cpu_set_core(&cpu_data[nvpes + v], c);
244				cpu_set_vpe_id(&cpu_data[nvpes + v], v);
245			}
246
247			nvpes += core_vpes;
248		}
249
250		pr_cont("}");
251	}
252	pr_cont(" total %u\n", nvpes);
253
254	/* Indicate present CPUs (CPU being synonymous with VPE) */
255	for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
256		set_cpu_possible(v, true);
257		set_cpu_present(v, true);
258		__cpu_number_map[v] = v;
259		__cpu_logical_map[v] = v;
260	}
261
262	/* Set a coherent default CCA (CWB) */
263	change_c0_config(CONF_CM_CMASK, 0x5);
264
265	/* Initialise core 0 */
266	mips_cps_core_init();
267
268	/* Make core 0 coherent with everything */
269	write_gcr_cl_coherence(0xff);
270
271	if (allocate_cps_vecs())
272		pr_err("Failed to allocate CPS vectors\n");
273
274	if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
275		write_gcr_bev_base(core_entry_reg);
276
277#ifdef CONFIG_MIPS_MT_FPAFF
278	/* If we have an FPU, enroll ourselves in the FPU-full mask */
279	if (cpu_has_fpu)
280		cpumask_set_cpu(0, &mt_fpu_cpumask);
281#endif /* CONFIG_MIPS_MT_FPAFF */
282}
283
284unsigned long calibrate_delay_is_known(void)
285{
286	int first_cpu_cluster = 0;
287
288	/* The calibration has to be done on the primary CPU of the cluster */
289	if (mips_cps_first_online_in_cluster(&first_cpu_cluster))
290		return 0;
291
292	return cpu_data[first_cpu_cluster].udelay_val;
293}
294
295static void __init cps_prepare_cpus(unsigned int max_cpus)
296{
297	unsigned int nclusters, ncores, core_vpes, nvpe = 0, c, cl, cca;
298	bool cca_unsuitable, cores_limited;
299	struct cluster_boot_config *cluster_bootcfg;
300	struct core_boot_config *core_bootcfg;
301
302	mips_mt_set_cpuoptions();
303
304	if (!core_entry_reg) {
305		pr_err("core_entry address unsuitable, disabling smp-cps\n");
306		goto err_out;
307	}
308
309	/* Detect whether the CCA is unsuited to multi-core SMP */
310	cca = read_c0_config() & CONF_CM_CMASK;
311	switch (cca) {
312	case 0x4: /* CWBE */
313	case 0x5: /* CWB */
314		/* The CCA is coherent, multi-core is fine */
315		cca_unsuitable = false;
316		break;
317
318	default:
319		/* CCA is not coherent, multi-core is not usable */
320		cca_unsuitable = true;
321	}
322
323	/* Warn the user if the CCA prevents multi-core */
324	cores_limited = false;
325	if (cca_unsuitable || cpu_has_dc_aliases) {
326		for_each_present_cpu(c) {
327			if (cpus_are_siblings(smp_processor_id(), c))
328				continue;
329
330			set_cpu_present(c, false);
331			cores_limited = true;
332		}
333	}
334	if (cores_limited)
335		pr_warn("Using only one core due to %s%s%s\n",
336			cca_unsuitable ? "unsuitable CCA" : "",
337			(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
338			cpu_has_dc_aliases ? "dcache aliasing" : "");
339
340	setup_cps_vecs();
341
342	/* Allocate cluster boot configuration structs */
343	nclusters = mips_cps_numclusters();
344	mips_cps_cluster_bootcfg = kcalloc(nclusters,
345					   sizeof(*mips_cps_cluster_bootcfg),
346					   GFP_KERNEL);
347	if (!mips_cps_cluster_bootcfg)
348		goto err_out;
349
350	if (nclusters > 1)
351		mips_cm_update_property();
352
353	for (cl = 0; cl < nclusters; cl++) {
354		/* Allocate core boot configuration structs */
355		ncores = mips_cps_numcores(cl);
356		core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg),
357					GFP_KERNEL);
358		if (!core_bootcfg)
359			goto err_out;
360		mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg;
361
362		mips_cps_cluster_bootcfg[cl].core_power =
363			kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long),
364				GFP_KERNEL);
365		if (!mips_cps_cluster_bootcfg[cl].core_power)
366			goto err_out;
367
368		/* Allocate VPE boot configuration structs */
369		for (c = 0; c < ncores; c++) {
370			int v;
371			core_vpes = core_vpe_count(cl, c);
372			core_bootcfg[c].vpe_config = kcalloc(core_vpes,
373					sizeof(*core_bootcfg[c].vpe_config),
374					GFP_KERNEL);
375			for (v = 0; v < core_vpes; v++)
376				cpumask_set_cpu(nvpe++, &mips_cps_cluster_bootcfg[cl].cpumask);
377			if (!core_bootcfg[c].vpe_config)
378				goto err_out;
379		}
380	}
381
382	/* Mark this CPU as powered up & booted */
383	cl = cpu_cluster(&current_cpu_data);
384	c = cpu_core(&current_cpu_data);
385	cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
386	cpu_smt_set_num_threads(core_vpes, core_vpes);
387	core_bootcfg = &cluster_bootcfg->core_config[c];
388	bitmap_set(cluster_bootcfg->core_power, cpu_core(&current_cpu_data), 1);
389	atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(&current_cpu_data));
390
391	return;
392err_out:
393	/* Clean up allocations */
394	if (mips_cps_cluster_bootcfg) {
395		for (cl = 0; cl < nclusters; cl++) {
396			cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
397			ncores = mips_cps_numcores(cl);
398			for (c = 0; c < ncores; c++) {
399				core_bootcfg = &cluster_bootcfg->core_config[c];
400				kfree(core_bootcfg->vpe_config);
401			}
402			kfree(mips_cps_cluster_bootcfg[c].core_config);
403		}
404		kfree(mips_cps_cluster_bootcfg);
405		mips_cps_cluster_bootcfg = NULL;
406	}
407
408	/* Effectively disable SMP by declaring CPUs not present */
409	for_each_possible_cpu(c) {
410		if (c == 0)
411			continue;
412		set_cpu_present(c, false);
413	}
414}
415
416static void init_cluster_l2(void)
417{
418	u32 l2_cfg, l2sm_cop, result;
419
420	while (!mips_cm_is_l2_hci_broken) {
421		l2_cfg = read_gcr_redir_l2_ram_config();
422
423		/* If HCI is not supported, use the state machine below */
424		if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT))
425			break;
426		if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED))
427			break;
428
429		/* If the HCI_DONE bit is set, we're finished */
430		if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE)
431			return;
432	}
433
434	l2sm_cop = read_gcr_redir_l2sm_cop();
435	if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT),
436		 "L2 init not supported on this system yet"))
437		return;
438
439	/* Clear L2 tag registers */
440	write_gcr_redir_l2_tag_state(0);
441	write_gcr_redir_l2_ecc(0);
442
443	/* Ensure the L2 tag writes complete before the state machine starts */
444	mb();
445
446	/* Wait for the L2 state machine to be idle */
447	do {
448		l2sm_cop = read_gcr_redir_l2sm_cop();
449	} while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING);
450
451	/* Start a store tag operation */
452	l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG;
453	l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE);
454	l2sm_cop |= CM_GCR_L2SM_COP_CMD_START;
455	write_gcr_redir_l2sm_cop(l2sm_cop);
456
457	/* Ensure the state machine starts before we poll for completion */
458	mb();
459
460	/* Wait for the operation to be complete */
461	do {
462		l2sm_cop = read_gcr_redir_l2sm_cop();
463		result = l2sm_cop & CM_GCR_L2SM_COP_RESULT;
464		result >>= __ffs(CM_GCR_L2SM_COP_RESULT);
465	} while (!result);
466
467	WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK,
468	     "L2 state machine failed cache init with error %u\n", result);
469}
470
471static void boot_core(unsigned int cluster, unsigned int core,
472		      unsigned int vpe_id)
473{
474	struct cluster_boot_config *cluster_cfg;
475	u32 access, stat, seq_state;
476	unsigned int timeout, ncores;
477
478	cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
479	ncores = mips_cps_numcores(cluster);
480
481	if ((cluster != cpu_cluster(&current_cpu_data)) &&
482	    bitmap_empty(cluster_cfg->core_power, ncores)) {
483		power_up_other_cluster(cluster);
484
485		mips_cm_lock_other(cluster, core, 0,
486				   CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
487
488		/* Ensure cluster GCRs are where we expect */
489		write_gcr_redir_base(read_gcr_base());
490		write_gcr_redir_cpc_base(read_gcr_cpc_base());
491		write_gcr_redir_gic_base(read_gcr_gic_base());
492
493		init_cluster_l2();
494
495		/* Mirror L2 configuration */
496		write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base());
497		write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control());
498		write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b());
499
500		/* Mirror ECC/parity setup */
501		write_gcr_redir_err_control(read_gcr_err_control());
502
503		/* Set BEV base */
504		write_gcr_redir_bev_base(core_entry_reg);
505
506		mips_cm_unlock_other();
507	}
508
509	if (cluster != cpu_cluster(&current_cpu_data)) {
510		mips_cm_lock_other(cluster, core, 0,
511				   CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
512
513		/* Ensure the core can access the GCRs */
514		access = read_gcr_redir_access();
515		access |= BIT(core);
516		write_gcr_redir_access(access);
517
518		mips_cm_unlock_other();
519	} else {
520		/* Ensure the core can access the GCRs */
521		access = read_gcr_access();
522		access |= BIT(core);
523		write_gcr_access(access);
524	}
525
526	/* Select the appropriate core */
527	mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
528
529	/* Set its reset vector */
530	if (mips_cm_is64)
531		write_gcr_co_reset64_base(core_entry_reg);
532	else
533		write_gcr_co_reset_base(core_entry_reg);
534
535	/* Ensure its coherency is disabled */
536	write_gcr_co_coherence(0);
537
538	/* Start it with the legacy memory map and exception base */
539	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
540
541	/* Ensure the core can access the GCRs */
542	if (mips_cm_revision() < CM_REV_CM3)
543		set_gcr_access(1 << core);
544	else
545		set_gcr_access_cm3(1 << core);
546
547	if (mips_cpc_present()) {
548		/* Reset the core */
549		mips_cpc_lock_other(core);
550
551		if (mips_cm_revision() >= CM_REV_CM3) {
552			/* Run only the requested VP following the reset */
553			write_cpc_co_vp_stop(0xf);
554			write_cpc_co_vp_run(1 << vpe_id);
555
556			/*
557			 * Ensure that the VP_RUN register is written before the
558			 * core leaves reset.
559			 */
560			wmb();
561		}
562
563		write_cpc_co_cmd(CPC_Cx_CMD_RESET);
564
565		timeout = 100;
566		while (true) {
567			stat = read_cpc_co_stat_conf();
568			seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
569			seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
570
571			/* U6 == coherent execution, ie. the core is up */
572			if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
573				break;
574
575			/* Delay a little while before we start warning */
576			if (timeout) {
577				timeout--;
578				mdelay(10);
579				continue;
580			}
581
582			pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
583				core, stat);
584			mdelay(1000);
585		}
586
587		mips_cpc_unlock_other();
588	} else {
589		/* Take the core out of reset */
590		write_gcr_co_reset_release(0);
591	}
592
593	mips_cm_unlock_other();
594
595	/* The core is now powered up */
596	bitmap_set(cluster_cfg->core_power, core, 1);
597
598	/*
599	 * Restore CM_PWRUP=0 so that the CM can power down if all the cores in
600	 * the cluster do (eg. if they're all removed via hotplug.
601	 */
602	if (mips_cm_revision() >= CM_REV_CM3_5) {
603		mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
604		write_cpc_redir_pwrup_ctl(0);
605		mips_cm_unlock_other();
606	}
607}
608
609static void remote_vpe_boot(void *dummy)
610{
611	unsigned int cluster = cpu_cluster(&current_cpu_data);
612	unsigned core = cpu_core(&current_cpu_data);
613	struct cluster_boot_config *cluster_cfg =
614		&mips_cps_cluster_bootcfg[cluster];
615	struct core_boot_config *core_cfg = &cluster_cfg->core_config[core];
616
617	mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
618}
619
620static int cps_boot_secondary(int cpu, struct task_struct *idle)
621{
622	unsigned int cluster = cpu_cluster(&cpu_data[cpu]);
623	unsigned core = cpu_core(&cpu_data[cpu]);
624	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
625	struct cluster_boot_config *cluster_cfg =
626		&mips_cps_cluster_bootcfg[cluster];
627	struct core_boot_config *core_cfg = &cluster_cfg->core_config[core];
628	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
629	unsigned int remote;
630	int err;
631
632	vpe_cfg->pc = (unsigned long)&smp_bootstrap;
633	vpe_cfg->sp = __KSTK_TOS(idle);
634	vpe_cfg->gp = (unsigned long)task_thread_info(idle);
635
636	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
637
638	preempt_disable();
639
640	if (!test_bit(core, cluster_cfg->core_power)) {
641		/* Boot a VPE on a powered down core */
642		boot_core(cluster, core, vpe_id);
643		goto out;
644	}
645
646	if (cpu_has_vp) {
647		mips_cm_lock_other(cluster, core, vpe_id,
648				   CM_GCR_Cx_OTHER_BLOCK_LOCAL);
649		if (mips_cm_is64)
650			write_gcr_co_reset64_base(core_entry_reg);
651		else
652			write_gcr_co_reset_base(core_entry_reg);
653		mips_cm_unlock_other();
654	}
655
656	if (!cpus_are_siblings(cpu, smp_processor_id())) {
657		/* Boot a VPE on another powered up core */
658		for (remote = 0; remote < NR_CPUS; remote++) {
659			if (!cpus_are_siblings(cpu, remote))
660				continue;
661			if (cpu_online(remote))
662				break;
663		}
664		if (remote >= NR_CPUS) {
665			pr_crit("No online CPU in core %u to start CPU%d\n",
666				core, cpu);
667			goto out;
668		}
669
670		err = smp_call_function_single(remote, remote_vpe_boot,
671					       NULL, 1);
672		if (err)
673			panic("Failed to call remote CPU\n");
674		goto out;
675	}
676
677	BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
678
679	/* Boot a VPE on this core */
680	mips_cps_boot_vpes(core_cfg, vpe_id);
681out:
682	preempt_enable();
683	return 0;
684}
685
686static void cps_init_secondary(void)
687{
688	int core = cpu_core(&current_cpu_data);
689
690	/* Disable MT - we only want to run 1 TC per VPE */
691	if (cpu_has_mipsmt)
692		dmt();
693
694	if (mips_cm_revision() >= CM_REV_CM3) {
695		unsigned int ident = read_gic_vl_ident();
696
697		/*
698		 * Ensure that our calculation of the VP ID matches up with
699		 * what the GIC reports, otherwise we'll have configured
700		 * interrupts incorrectly.
701		 */
702		BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
703	}
704
705	if (core > 0 && !read_gcr_cl_coherence())
706		pr_warn("Core %u is not in coherent domain\n", core);
707
708	if (cpu_has_veic)
709		clear_c0_status(ST0_IM);
710	else
711		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
712					 STATUSF_IP4 | STATUSF_IP5 |
713					 STATUSF_IP6 | STATUSF_IP7);
714}
715
716static void cps_smp_finish(void)
717{
718	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
719
720#ifdef CONFIG_MIPS_MT_FPAFF
721	/* If we have an FPU, enroll ourselves in the FPU-full mask */
722	if (cpu_has_fpu)
723		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
724#endif /* CONFIG_MIPS_MT_FPAFF */
725
726	local_irq_enable();
727}
728
729#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
730
731enum cpu_death {
732	CPU_DEATH_HALT,
733	CPU_DEATH_POWER,
734};
735
736static void cps_shutdown_this_cpu(enum cpu_death death)
737{
738	unsigned int cpu, core, vpe_id;
739
740	cpu = smp_processor_id();
741	core = cpu_core(&cpu_data[cpu]);
742
743	if (death == CPU_DEATH_HALT) {
744		vpe_id = cpu_vpe_id(&cpu_data[cpu]);
745
746		pr_debug("Halting core %d VP%d\n", core, vpe_id);
747		if (cpu_has_mipsmt) {
748			/* Halt this TC */
749			write_c0_tchalt(TCHALT_H);
750			instruction_hazard();
751		} else if (cpu_has_vp) {
752			write_cpc_cl_vp_stop(1 << vpe_id);
753
754			/* Ensure that the VP_STOP register is written */
755			wmb();
756		}
757	} else {
758		if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
759			pr_debug("Gating power to core %d\n", core);
760			/* Power down the core */
761			cps_pm_enter_state(CPS_PM_POWER_GATED);
762		}
763	}
764}
765
766#ifdef CONFIG_KEXEC_CORE
767
768static void cps_kexec_nonboot_cpu(void)
769{
770	if (cpu_has_mipsmt || cpu_has_vp)
771		cps_shutdown_this_cpu(CPU_DEATH_HALT);
772	else
773		cps_shutdown_this_cpu(CPU_DEATH_POWER);
774}
775
776#endif /* CONFIG_KEXEC_CORE */
777
778#endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */
779
780#ifdef CONFIG_HOTPLUG_CPU
781
782static int cps_cpu_disable(void)
783{
784	unsigned cpu = smp_processor_id();
785	struct cluster_boot_config *cluster_cfg;
786	struct core_boot_config *core_cfg;
787
788	if (!cps_pm_support_state(CPS_PM_POWER_GATED))
789		return -EINVAL;
790
791	cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(&current_cpu_data)];
792	core_cfg = &cluster_cfg->core_config[cpu_core(&current_cpu_data)];
793	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
794	smp_mb__after_atomic();
795	set_cpu_online(cpu, false);
796	calculate_cpu_foreign_map();
797	irq_migrate_all_off_this_cpu();
798
799	return 0;
800}
801
802static unsigned cpu_death_sibling;
803static enum cpu_death cpu_death;
804
805void play_dead(void)
806{
807	unsigned int cpu;
808
809	local_irq_disable();
810	idle_task_exit();
811	cpu = smp_processor_id();
812	cpu_death = CPU_DEATH_POWER;
813
814	pr_debug("CPU%d going offline\n", cpu);
815
816	if (cpu_has_mipsmt || cpu_has_vp) {
817		/* Look for another online VPE within the core */
818		for_each_online_cpu(cpu_death_sibling) {
819			if (!cpus_are_siblings(cpu, cpu_death_sibling))
820				continue;
821
822			/*
823			 * There is an online VPE within the core. Just halt
824			 * this TC and leave the core alone.
825			 */
826			cpu_death = CPU_DEATH_HALT;
827			break;
828		}
829	}
830
831	cpuhp_ap_report_dead();
832
833	cps_shutdown_this_cpu(cpu_death);
834
835	/* This should never be reached */
836	panic("Failed to offline CPU %u", cpu);
837}
838
839static void wait_for_sibling_halt(void *ptr_cpu)
840{
841	unsigned cpu = (unsigned long)ptr_cpu;
842	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
843	unsigned halted;
844	unsigned long flags;
845
846	do {
847		local_irq_save(flags);
848		settc(vpe_id);
849		halted = read_tc_c0_tchalt();
850		local_irq_restore(flags);
851	} while (!(halted & TCHALT_H));
852}
853
854static void cps_cpu_die(unsigned int cpu) { }
855
856static void cps_cleanup_dead_cpu(unsigned cpu)
857{
858	unsigned int cluster = cpu_cluster(&cpu_data[cpu]);
859	unsigned core = cpu_core(&cpu_data[cpu]);
860	unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
861	ktime_t fail_time;
862	unsigned stat;
863	int err;
864	struct cluster_boot_config *cluster_cfg;
865
866	cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
867
868	/*
869	 * Now wait for the CPU to actually offline. Without doing this that
870	 * offlining may race with one or more of:
871	 *
872	 *   - Onlining the CPU again.
873	 *   - Powering down the core if another VPE within it is offlined.
874	 *   - A sibling VPE entering a non-coherent state.
875	 *
876	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
877	 * with which we could race, so do nothing.
878	 */
879	if (cpu_death == CPU_DEATH_POWER) {
880		/*
881		 * Wait for the core to enter a powered down or clock gated
882		 * state, the latter happening when a JTAG probe is connected
883		 * in which case the CPC will refuse to power down the core.
884		 */
885		fail_time = ktime_add_ms(ktime_get(), 2000);
886		do {
887			mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
888			mips_cpc_lock_other(core);
889			stat = read_cpc_co_stat_conf();
890			stat &= CPC_Cx_STAT_CONF_SEQSTATE;
891			stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
892			mips_cpc_unlock_other();
893			mips_cm_unlock_other();
894
895			if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
896			    stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
897			    stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
898				break;
899
900			/*
901			 * The core ought to have powered down, but didn't &
902			 * now we don't really know what state it's in. It's
903			 * likely that its _pwr_up pin has been wired to logic
904			 * 1 & it powered back up as soon as we powered it
905			 * down...
906			 *
907			 * The best we can do is warn the user & continue in
908			 * the hope that the core is doing nothing harmful &
909			 * might behave properly if we online it later.
910			 */
911			if (WARN(ktime_after(ktime_get(), fail_time),
912				 "CPU%u hasn't powered down, seq. state %u\n",
913				 cpu, stat))
914				break;
915		} while (1);
916
917		/* Indicate the core is powered off */
918		bitmap_clear(cluster_cfg->core_power, core, 1);
919	} else if (cpu_has_mipsmt) {
920		/*
921		 * Have a CPU with access to the offlined CPUs registers wait
922		 * for its TC to halt.
923		 */
924		err = smp_call_function_single(cpu_death_sibling,
925					       wait_for_sibling_halt,
926					       (void *)(unsigned long)cpu, 1);
927		if (err)
928			panic("Failed to call remote sibling CPU\n");
929	} else if (cpu_has_vp) {
930		do {
931			mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
932			stat = read_cpc_co_vp_running();
933			mips_cm_unlock_other();
934		} while (stat & (1 << vpe_id));
935	}
936}
937
938#endif /* CONFIG_HOTPLUG_CPU */
939
940static const struct plat_smp_ops cps_smp_ops = {
941	.smp_setup		= cps_smp_setup,
942	.prepare_cpus		= cps_prepare_cpus,
943	.boot_secondary		= cps_boot_secondary,
944	.init_secondary		= cps_init_secondary,
945	.smp_finish		= cps_smp_finish,
946	.send_ipi_single	= mips_smp_send_ipi_single,
947	.send_ipi_mask		= mips_smp_send_ipi_mask,
948#ifdef CONFIG_HOTPLUG_CPU
949	.cpu_disable		= cps_cpu_disable,
950	.cpu_die		= cps_cpu_die,
951	.cleanup_dead_cpu	= cps_cleanup_dead_cpu,
952#endif
953#ifdef CONFIG_KEXEC_CORE
954	.kexec_nonboot_cpu	= cps_kexec_nonboot_cpu,
955#endif
956};
957
958bool mips_cps_smp_in_use(void)
959{
960	extern const struct plat_smp_ops *mp_ops;
961	return mp_ops == &cps_smp_ops;
962}
963
964int register_cps_smp_ops(void)
965{
966	if (!mips_cm_present()) {
967		pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
968		return -ENODEV;
969	}
970
971	/* check we have a GIC - we need one for IPIs */
972	if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
973		pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
974		return -ENODEV;
975	}
976
977	register_smp_ops(&cps_smp_ops);
978	return 0;
979}