perf_event_mipsxx.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Linux performance counter support for MIPS.
   4 *
   5 * Copyright (C) 2010 MIPS Technologies, Inc.
   6 * Copyright (C) 2011 Cavium Networks, Inc.
   7 * Author: Deng-Cheng Zhu
   8 *
   9 * This code is based on the implementation for ARM, which is in turn
  10 * based on the sparc64 perf event code and the x86 code. Performance
  11 * counter access is based on the MIPS Oprofile code. And the callchain
  12 * support references the code of MIPS stacktrace.c.
  13 */
  14
  15#include <linux/cpumask.h>
  16#include <linux/interrupt.h>
  17#include <linux/smp.h>
  18#include <linux/kernel.h>
  19#include <linux/perf_event.h>
  20#include <linux/uaccess.h>
  21
  22#include <asm/irq.h>
  23#include <asm/irq_regs.h>
  24#include <asm/stacktrace.h>
  25#include <asm/time.h> /* For perf_irq */
  26
  27#define MIPS_MAX_HWEVENTS 4
  28#define MIPS_TCS_PER_COUNTER 2
  29#define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
  30
  31struct cpu_hw_events {
  32	/* Array of events on this cpu. */
  33	struct perf_event	*events[MIPS_MAX_HWEVENTS];
  34
  35	/*
  36	 * Set the bit (indexed by the counter number) when the counter
  37	 * is used for an event.
  38	 */
  39	unsigned long		used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
  40
  41	/*
  42	 * Software copy of the control register for each performance counter.
  43	 * MIPS CPUs vary in performance counters. They use this differently,
  44	 * and even may not use it.
  45	 */
  46	unsigned int		saved_ctrl[MIPS_MAX_HWEVENTS];
  47};
  48DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  49	.saved_ctrl = {0},
  50};
  51
  52/* The description of MIPS performance events. */
  53struct mips_perf_event {
  54	unsigned int event_id;
  55	/*
  56	 * MIPS performance counters are indexed starting from 0.
  57	 * CNTR_EVEN indicates the indexes of the counters to be used are
  58	 * even numbers.
  59	 */
  60	unsigned int cntr_mask;
  61	#define CNTR_EVEN	0x55555555
  62	#define CNTR_ODD	0xaaaaaaaa
  63	#define CNTR_ALL	0xffffffff
  64	enum {
  65		T  = 0,
  66		V  = 1,
  67		P  = 2,
  68	} range;
  69};
  70
  71static struct mips_perf_event raw_event;
  72static DEFINE_MUTEX(raw_event_mutex);
  73
  74#define C(x) PERF_COUNT_HW_CACHE_##x
  75
  76struct mips_pmu {
  77	u64		max_period;
  78	u64		valid_count;
  79	u64		overflow;
  80	const char	*name;
  81	int		irq;
  82	u64		(*read_counter)(unsigned int idx);
  83	void		(*write_counter)(unsigned int idx, u64 val);
  84	const struct mips_perf_event *(*map_raw_event)(u64 config);
  85	const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
  86	const struct mips_perf_event (*cache_event_map)
  87				[PERF_COUNT_HW_CACHE_MAX]
  88				[PERF_COUNT_HW_CACHE_OP_MAX]
  89				[PERF_COUNT_HW_CACHE_RESULT_MAX];
  90	unsigned int	num_counters;
  91};
  92
  93static int counter_bits;
  94static struct mips_pmu mipspmu;
  95
  96#define M_PERFCTL_EVENT(event)		(((event) << MIPS_PERFCTRL_EVENT_S) & \
  97					 MIPS_PERFCTRL_EVENT)
  98#define M_PERFCTL_VPEID(vpe)		((vpe)	  << MIPS_PERFCTRL_VPEID_S)
  99
 100#ifdef CONFIG_CPU_BMIPS5000
 101#define M_PERFCTL_MT_EN(filter)		0
 102#else /* !CONFIG_CPU_BMIPS5000 */
 103#define M_PERFCTL_MT_EN(filter)		(filter)
 104#endif /* CONFIG_CPU_BMIPS5000 */
 105
 106#define	   M_TC_EN_ALL			M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
 107#define	   M_TC_EN_VPE			M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
 108#define	   M_TC_EN_TC			M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
 109
 110#define M_PERFCTL_COUNT_EVENT_WHENEVER	(MIPS_PERFCTRL_EXL |		\
 111					 MIPS_PERFCTRL_K |		\
 112					 MIPS_PERFCTRL_U |		\
 113					 MIPS_PERFCTRL_S |		\
 114					 MIPS_PERFCTRL_IE)
 115
 116#ifdef CONFIG_MIPS_MT_SMP
 117#define M_PERFCTL_CONFIG_MASK		0x3fff801f
 118#else
 119#define M_PERFCTL_CONFIG_MASK		0x1f
 120#endif
 121
 122#define CNTR_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
 123
 124#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 125static DEFINE_RWLOCK(pmuint_rwlock);
 126
 127#if defined(CONFIG_CPU_BMIPS5000)
 128#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
 129			 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
 130#else
 131#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
 132			 0 : cpu_vpe_id(&current_cpu_data))
 133#endif
 134
 135/* Copied from op_model_mipsxx.c */
 136static unsigned int vpe_shift(void)
 137{
 138	if (num_possible_cpus() > 1)
 139		return 1;
 140
 141	return 0;
 142}
 143
 144static unsigned int counters_total_to_per_cpu(unsigned int counters)
 145{
 146	return counters >> vpe_shift();
 147}
 148
 149#else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 150#define vpe_id()	0
 151
 152#endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 153
 154static void resume_local_counters(void);
 155static void pause_local_counters(void);
 156static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
 157static int mipsxx_pmu_handle_shared_irq(void);
 158
 159/* 0: Not Loongson-3
 160 * 1: Loongson-3A1000/3B1000/3B1500
 161 * 2: Loongson-3A2000/3A3000
 162 * 3: Loongson-3A4000+
 163 */
 164
 165#define LOONGSON_PMU_TYPE0 0
 166#define LOONGSON_PMU_TYPE1 1
 167#define LOONGSON_PMU_TYPE2 2
 168#define LOONGSON_PMU_TYPE3 3
 169
 170static inline int get_loongson3_pmu_type(void)
 171{
 172	if (boot_cpu_type() != CPU_LOONGSON64)
 173		return LOONGSON_PMU_TYPE0;
 174	if ((boot_cpu_data.processor_id & PRID_COMP_MASK) == PRID_COMP_LEGACY)
 175		return LOONGSON_PMU_TYPE1;
 176	if ((boot_cpu_data.processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C)
 177		return LOONGSON_PMU_TYPE2;
 178	if ((boot_cpu_data.processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G)
 179		return LOONGSON_PMU_TYPE3;
 180
 181	return LOONGSON_PMU_TYPE0;
 182}
 183
 184static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
 185{
 186	if (vpe_id() == 1)
 187		idx = (idx + 2) & 3;
 188	return idx;
 189}
 190
 191static u64 mipsxx_pmu_read_counter(unsigned int idx)
 192{
 193	idx = mipsxx_pmu_swizzle_perf_idx(idx);
 194
 195	switch (idx) {
 196	case 0:
 197		/*
 198		 * The counters are unsigned, we must cast to truncate
 199		 * off the high bits.
 200		 */
 201		return (u32)read_c0_perfcntr0();
 202	case 1:
 203		return (u32)read_c0_perfcntr1();
 204	case 2:
 205		return (u32)read_c0_perfcntr2();
 206	case 3:
 207		return (u32)read_c0_perfcntr3();
 208	default:
 209		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 210		return 0;
 211	}
 212}
 213
 214static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
 215{
 216	u64 mask = CNTR_BIT_MASK(counter_bits);
 217	idx = mipsxx_pmu_swizzle_perf_idx(idx);
 218
 219	switch (idx) {
 220	case 0:
 221		return read_c0_perfcntr0_64() & mask;
 222	case 1:
 223		return read_c0_perfcntr1_64() & mask;
 224	case 2:
 225		return read_c0_perfcntr2_64() & mask;
 226	case 3:
 227		return read_c0_perfcntr3_64() & mask;
 228	default:
 229		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 230		return 0;
 231	}
 232}
 233
 234static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
 235{
 236	idx = mipsxx_pmu_swizzle_perf_idx(idx);
 237
 238	switch (idx) {
 239	case 0:
 240		write_c0_perfcntr0(val);
 241		return;
 242	case 1:
 243		write_c0_perfcntr1(val);
 244		return;
 245	case 2:
 246		write_c0_perfcntr2(val);
 247		return;
 248	case 3:
 249		write_c0_perfcntr3(val);
 250		return;
 251	}
 252}
 253
 254static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
 255{
 256	val &= CNTR_BIT_MASK(counter_bits);
 257	idx = mipsxx_pmu_swizzle_perf_idx(idx);
 258
 259	switch (idx) {
 260	case 0:
 261		write_c0_perfcntr0_64(val);
 262		return;
 263	case 1:
 264		write_c0_perfcntr1_64(val);
 265		return;
 266	case 2:
 267		write_c0_perfcntr2_64(val);
 268		return;
 269	case 3:
 270		write_c0_perfcntr3_64(val);
 271		return;
 272	}
 273}
 274
 275static unsigned int mipsxx_pmu_read_control(unsigned int idx)
 276{
 277	idx = mipsxx_pmu_swizzle_perf_idx(idx);
 278
 279	switch (idx) {
 280	case 0:
 281		return read_c0_perfctrl0();
 282	case 1:
 283		return read_c0_perfctrl1();
 284	case 2:
 285		return read_c0_perfctrl2();
 286	case 3:
 287		return read_c0_perfctrl3();
 288	default:
 289		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 290		return 0;
 291	}
 292}
 293
 294static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
 295{
 296	idx = mipsxx_pmu_swizzle_perf_idx(idx);
 297
 298	switch (idx) {
 299	case 0:
 300		write_c0_perfctrl0(val);
 301		return;
 302	case 1:
 303		write_c0_perfctrl1(val);
 304		return;
 305	case 2:
 306		write_c0_perfctrl2(val);
 307		return;
 308	case 3:
 309		write_c0_perfctrl3(val);
 310		return;
 311	}
 312}
 313
 314static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
 315				    struct hw_perf_event *hwc)
 316{
 317	int i;
 318	unsigned long cntr_mask;
 319
 320	/*
 321	 * We only need to care the counter mask. The range has been
 322	 * checked definitely.
 323	 */
 324	if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
 325		cntr_mask = (hwc->event_base >> 10) & 0xffff;
 326	else
 327		cntr_mask = (hwc->event_base >> 8) & 0xffff;
 328
 329	for (i = mipspmu.num_counters - 1; i >= 0; i--) {
 330		/*
 331		 * Note that some MIPS perf events can be counted by both
 332		 * even and odd counters, whereas many other are only by
 333		 * even _or_ odd counters. This introduces an issue that
 334		 * when the former kind of event takes the counter the
 335		 * latter kind of event wants to use, then the "counter
 336		 * allocation" for the latter event will fail. In fact if
 337		 * they can be dynamically swapped, they both feel happy.
 338		 * But here we leave this issue alone for now.
 339		 */
 340		if (test_bit(i, &cntr_mask) &&
 341			!test_and_set_bit(i, cpuc->used_mask))
 342			return i;
 343	}
 344
 345	return -EAGAIN;
 346}
 347
 348static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
 349{
 350	struct perf_event *event = container_of(evt, struct perf_event, hw);
 351	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 352	unsigned int range = evt->event_base >> 24;
 353
 354	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 355
 356	if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
 357		cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0x3ff) |
 358			(evt->config_base & M_PERFCTL_CONFIG_MASK) |
 359			/* Make sure interrupt enabled. */
 360			MIPS_PERFCTRL_IE;
 361	else
 362		cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
 363			(evt->config_base & M_PERFCTL_CONFIG_MASK) |
 364			/* Make sure interrupt enabled. */
 365			MIPS_PERFCTRL_IE;
 366
 367	if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
 368		/* enable the counter for the calling thread */
 369		cpuc->saved_ctrl[idx] |=
 370			(1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
 371	} else if (IS_ENABLED(CONFIG_MIPS_MT_SMP) && range > V) {
 372		/* The counter is processor wide. Set it up to count all TCs. */
 373		pr_debug("Enabling perf counter for all TCs\n");
 374		cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
 375	} else {
 376		unsigned int cpu, ctrl;
 377
 378		/*
 379		 * Set up the counter for a particular CPU when event->cpu is
 380		 * a valid CPU number. Otherwise set up the counter for the CPU
 381		 * scheduling this thread.
 382		 */
 383		cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
 384
 385		ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
 386		ctrl |= M_TC_EN_VPE;
 387		cpuc->saved_ctrl[idx] |= ctrl;
 388		pr_debug("Enabling perf counter for CPU%d\n", cpu);
 389	}
 390	/*
 391	 * We do not actually let the counter run. Leave it until start().
 392	 */
 393}
 394
 395static void mipsxx_pmu_disable_event(int idx)
 396{
 397	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 398	unsigned long flags;
 399
 400	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 401
 402	local_irq_save(flags);
 403	cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
 404		~M_PERFCTL_COUNT_EVENT_WHENEVER;
 405	mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
 406	local_irq_restore(flags);
 407}
 408
 409static int mipspmu_event_set_period(struct perf_event *event,
 410				    struct hw_perf_event *hwc,
 411				    int idx)
 412{
 413	u64 left = local64_read(&hwc->period_left);
 414	u64 period = hwc->sample_period;
 415	int ret = 0;
 416
 417	if (unlikely((left + period) & (1ULL << 63))) {
 418		/* left underflowed by more than period. */
 419		left = period;
 420		local64_set(&hwc->period_left, left);
 421		hwc->last_period = period;
 422		ret = 1;
 423	} else	if (unlikely((left + period) <= period)) {
 424		/* left underflowed by less than period. */
 425		left += period;
 426		local64_set(&hwc->period_left, left);
 427		hwc->last_period = period;
 428		ret = 1;
 429	}
 430
 431	if (left > mipspmu.max_period) {
 432		left = mipspmu.max_period;
 433		local64_set(&hwc->period_left, left);
 434	}
 435
 436	local64_set(&hwc->prev_count, mipspmu.overflow - left);
 437
 438	if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
 439		mipsxx_pmu_write_control(idx,
 440				M_PERFCTL_EVENT(hwc->event_base & 0x3ff));
 441
 442	mipspmu.write_counter(idx, mipspmu.overflow - left);
 443
 444	perf_event_update_userpage(event);
 445
 446	return ret;
 447}
 448
 449static void mipspmu_event_update(struct perf_event *event,
 450				 struct hw_perf_event *hwc,
 451				 int idx)
 452{
 453	u64 prev_raw_count, new_raw_count;
 454	u64 delta;
 455
 456again:
 457	prev_raw_count = local64_read(&hwc->prev_count);
 458	new_raw_count = mipspmu.read_counter(idx);
 459
 460	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 461				new_raw_count) != prev_raw_count)
 462		goto again;
 463
 464	delta = new_raw_count - prev_raw_count;
 465
 466	local64_add(delta, &event->count);
 467	local64_sub(delta, &hwc->period_left);
 468}
 469
 470static void mipspmu_start(struct perf_event *event, int flags)
 471{
 472	struct hw_perf_event *hwc = &event->hw;
 473
 474	if (flags & PERF_EF_RELOAD)
 475		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 476
 477	hwc->state = 0;
 478
 479	/* Set the period for the event. */
 480	mipspmu_event_set_period(event, hwc, hwc->idx);
 481
 482	/* Enable the event. */
 483	mipsxx_pmu_enable_event(hwc, hwc->idx);
 484}
 485
 486static void mipspmu_stop(struct perf_event *event, int flags)
 487{
 488	struct hw_perf_event *hwc = &event->hw;
 489
 490	if (!(hwc->state & PERF_HES_STOPPED)) {
 491		/* We are working on a local event. */
 492		mipsxx_pmu_disable_event(hwc->idx);
 493		barrier();
 494		mipspmu_event_update(event, hwc, hwc->idx);
 495		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 496	}
 497}
 498
 499static int mipspmu_add(struct perf_event *event, int flags)
 500{
 501	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 502	struct hw_perf_event *hwc = &event->hw;
 503	int idx;
 504	int err = 0;
 505
 506	perf_pmu_disable(event->pmu);
 507
 508	/* To look for a free counter for this event. */
 509	idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
 510	if (idx < 0) {
 511		err = idx;
 512		goto out;
 513	}
 514
 515	/*
 516	 * If there is an event in the counter we are going to use then
 517	 * make sure it is disabled.
 518	 */
 519	event->hw.idx = idx;
 520	mipsxx_pmu_disable_event(idx);
 521	cpuc->events[idx] = event;
 522
 523	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 524	if (flags & PERF_EF_START)
 525		mipspmu_start(event, PERF_EF_RELOAD);
 526
 527	/* Propagate our changes to the userspace mapping. */
 528	perf_event_update_userpage(event);
 529
 530out:
 531	perf_pmu_enable(event->pmu);
 532	return err;
 533}
 534
 535static void mipspmu_del(struct perf_event *event, int flags)
 536{
 537	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 538	struct hw_perf_event *hwc = &event->hw;
 539	int idx = hwc->idx;
 540
 541	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 542
 543	mipspmu_stop(event, PERF_EF_UPDATE);
 544	cpuc->events[idx] = NULL;
 545	clear_bit(idx, cpuc->used_mask);
 546
 547	perf_event_update_userpage(event);
 548}
 549
 550static void mipspmu_read(struct perf_event *event)
 551{
 552	struct hw_perf_event *hwc = &event->hw;
 553
 554	/* Don't read disabled counters! */
 555	if (hwc->idx < 0)
 556		return;
 557
 558	mipspmu_event_update(event, hwc, hwc->idx);
 559}
 560
 561static void mipspmu_enable(struct pmu *pmu)
 562{
 563#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 564	write_unlock(&pmuint_rwlock);
 565#endif
 566	resume_local_counters();
 567}
 568
 569/*
 570 * MIPS performance counters can be per-TC. The control registers can
 571 * not be directly accessed across CPUs. Hence if we want to do global
 572 * control, we need cross CPU calls. on_each_cpu() can help us, but we
 573 * can not make sure this function is called with interrupts enabled. So
 574 * here we pause local counters and then grab a rwlock and leave the
 575 * counters on other CPUs alone. If any counter interrupt raises while
 576 * we own the write lock, simply pause local counters on that CPU and
 577 * spin in the handler. Also we know we won't be switched to another
 578 * CPU after pausing local counters and before grabbing the lock.
 579 */
 580static void mipspmu_disable(struct pmu *pmu)
 581{
 582	pause_local_counters();
 583#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 584	write_lock(&pmuint_rwlock);
 585#endif
 586}
 587
 588static atomic_t active_events = ATOMIC_INIT(0);
 589static DEFINE_MUTEX(pmu_reserve_mutex);
 590static int (*save_perf_irq)(void);
 591
 592static int mipspmu_get_irq(void)
 593{
 594	int err;
 595
 596	if (mipspmu.irq >= 0) {
 597		/* Request my own irq handler. */
 598		err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
 599				  IRQF_PERCPU | IRQF_NOBALANCING |
 600				  IRQF_NO_THREAD | IRQF_NO_SUSPEND |
 601				  IRQF_SHARED,
 602				  "mips_perf_pmu", &mipspmu);
 603		if (err) {
 604			pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
 605				mipspmu.irq);
 606		}
 607	} else if (cp0_perfcount_irq < 0) {
 608		/*
 609		 * We are sharing the irq number with the timer interrupt.
 610		 */
 611		save_perf_irq = perf_irq;
 612		perf_irq = mipsxx_pmu_handle_shared_irq;
 613		err = 0;
 614	} else {
 615		pr_warn("The platform hasn't properly defined its interrupt controller\n");
 616		err = -ENOENT;
 617	}
 618
 619	return err;
 620}
 621
 622static void mipspmu_free_irq(void)
 623{
 624	if (mipspmu.irq >= 0)
 625		free_irq(mipspmu.irq, &mipspmu);
 626	else if (cp0_perfcount_irq < 0)
 627		perf_irq = save_perf_irq;
 628}
 629
 630/*
 631 * mipsxx/rm9000/loongson2 have different performance counters, they have
 632 * specific low-level init routines.
 633 */
 634static void reset_counters(void *arg);
 635static int __hw_perf_event_init(struct perf_event *event);
 636
 637static void hw_perf_event_destroy(struct perf_event *event)
 638{
 639	if (atomic_dec_and_mutex_lock(&active_events,
 640				&pmu_reserve_mutex)) {
 641		/*
 642		 * We must not call the destroy function with interrupts
 643		 * disabled.
 644		 */
 645		on_each_cpu(reset_counters,
 646			(void *)(long)mipspmu.num_counters, 1);
 647		mipspmu_free_irq();
 648		mutex_unlock(&pmu_reserve_mutex);
 649	}
 650}
 651
 652static int mipspmu_event_init(struct perf_event *event)
 653{
 654	int err = 0;
 655
 656	/* does not support taken branch sampling */
 657	if (has_branch_stack(event))
 658		return -EOPNOTSUPP;
 659
 660	switch (event->attr.type) {
 661	case PERF_TYPE_RAW:
 662	case PERF_TYPE_HARDWARE:
 663	case PERF_TYPE_HW_CACHE:
 664		break;
 665
 666	default:
 667		return -ENOENT;
 668	}
 669
 670	if (event->cpu >= 0 && !cpu_online(event->cpu))
 671		return -ENODEV;
 672
 673	if (!atomic_inc_not_zero(&active_events)) {
 674		mutex_lock(&pmu_reserve_mutex);
 675		if (atomic_read(&active_events) == 0)
 676			err = mipspmu_get_irq();
 677
 678		if (!err)
 679			atomic_inc(&active_events);
 680		mutex_unlock(&pmu_reserve_mutex);
 681	}
 682
 683	if (err)
 684		return err;
 685
 686	return __hw_perf_event_init(event);
 687}
 688
 689static struct pmu pmu = {
 690	.pmu_enable	= mipspmu_enable,
 691	.pmu_disable	= mipspmu_disable,
 692	.event_init	= mipspmu_event_init,
 693	.add		= mipspmu_add,
 694	.del		= mipspmu_del,
 695	.start		= mipspmu_start,
 696	.stop		= mipspmu_stop,
 697	.read		= mipspmu_read,
 698};
 699
 700static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
 701{
 702/*
 703 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
 704 * event_id.
 705 */
 706#ifdef CONFIG_MIPS_MT_SMP
 707	if (num_possible_cpus() > 1)
 708		return ((unsigned int)pev->range << 24) |
 709			(pev->cntr_mask & 0xffff00) |
 710			(pev->event_id & 0xff);
 711	else
 712#endif /* CONFIG_MIPS_MT_SMP */
 713	{
 714		if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
 715			return (pev->cntr_mask & 0xfffc00) |
 716				(pev->event_id & 0x3ff);
 717		else
 718			return (pev->cntr_mask & 0xffff00) |
 719				(pev->event_id & 0xff);
 720	}
 721}
 722
 723static const struct mips_perf_event *mipspmu_map_general_event(int idx)
 724{
 725
 726	if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
 727		return ERR_PTR(-EOPNOTSUPP);
 728	return &(*mipspmu.general_event_map)[idx];
 729}
 730
 731static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
 732{
 733	unsigned int cache_type, cache_op, cache_result;
 734	const struct mips_perf_event *pev;
 735
 736	cache_type = (config >> 0) & 0xff;
 737	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 738		return ERR_PTR(-EINVAL);
 739
 740	cache_op = (config >> 8) & 0xff;
 741	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 742		return ERR_PTR(-EINVAL);
 743
 744	cache_result = (config >> 16) & 0xff;
 745	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 746		return ERR_PTR(-EINVAL);
 747
 748	pev = &((*mipspmu.cache_event_map)
 749					[cache_type]
 750					[cache_op]
 751					[cache_result]);
 752
 753	if (pev->cntr_mask == 0)
 754		return ERR_PTR(-EOPNOTSUPP);
 755
 756	return pev;
 757
 758}
 759
 760static int validate_group(struct perf_event *event)
 761{
 762	struct perf_event *sibling, *leader = event->group_leader;
 763	struct cpu_hw_events fake_cpuc;
 764
 765	memset(&fake_cpuc, 0, sizeof(fake_cpuc));
 766
 767	if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
 768		return -EINVAL;
 769
 770	for_each_sibling_event(sibling, leader) {
 771		if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
 772			return -EINVAL;
 773	}
 774
 775	if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
 776		return -EINVAL;
 777
 778	return 0;
 779}
 780
 781/* This is needed by specific irq handlers in perf_event_*.c */
 782static void handle_associated_event(struct cpu_hw_events *cpuc,
 783				    int idx, struct perf_sample_data *data,
 784				    struct pt_regs *regs)
 785{
 786	struct perf_event *event = cpuc->events[idx];
 787	struct hw_perf_event *hwc = &event->hw;
 788
 789	mipspmu_event_update(event, hwc, idx);
 790	data->period = event->hw.last_period;
 791	if (!mipspmu_event_set_period(event, hwc, idx))
 792		return;
 793
 794	perf_event_overflow(event, data, regs);
 795}
 796
 797
 798static int __n_counters(void)
 799{
 800	if (!cpu_has_perf)
 801		return 0;
 802	if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
 803		return 1;
 804	if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
 805		return 2;
 806	if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
 807		return 3;
 808
 809	return 4;
 810}
 811
 812static int n_counters(void)
 813{
 814	int counters;
 815
 816	switch (current_cpu_type()) {
 817	case CPU_R10000:
 818		counters = 2;
 819		break;
 820
 821	case CPU_R12000:
 822	case CPU_R14000:
 823	case CPU_R16000:
 824		counters = 4;
 825		break;
 826
 827	default:
 828		counters = __n_counters();
 829	}
 830
 831	return counters;
 832}
 833
 834static void loongson3_reset_counters(void *arg)
 835{
 836	int counters = (int)(long)arg;
 837
 838	switch (counters) {
 839	case 4:
 840		mipsxx_pmu_write_control(3, 0);
 841		mipspmu.write_counter(3, 0);
 842		mipsxx_pmu_write_control(3, 127<<5);
 843		mipspmu.write_counter(3, 0);
 844		mipsxx_pmu_write_control(3, 191<<5);
 845		mipspmu.write_counter(3, 0);
 846		mipsxx_pmu_write_control(3, 255<<5);
 847		mipspmu.write_counter(3, 0);
 848		mipsxx_pmu_write_control(3, 319<<5);
 849		mipspmu.write_counter(3, 0);
 850		mipsxx_pmu_write_control(3, 383<<5);
 851		mipspmu.write_counter(3, 0);
 852		mipsxx_pmu_write_control(3, 575<<5);
 853		mipspmu.write_counter(3, 0);
 854		fallthrough;
 855	case 3:
 856		mipsxx_pmu_write_control(2, 0);
 857		mipspmu.write_counter(2, 0);
 858		mipsxx_pmu_write_control(2, 127<<5);
 859		mipspmu.write_counter(2, 0);
 860		mipsxx_pmu_write_control(2, 191<<5);
 861		mipspmu.write_counter(2, 0);
 862		mipsxx_pmu_write_control(2, 255<<5);
 863		mipspmu.write_counter(2, 0);
 864		mipsxx_pmu_write_control(2, 319<<5);
 865		mipspmu.write_counter(2, 0);
 866		mipsxx_pmu_write_control(2, 383<<5);
 867		mipspmu.write_counter(2, 0);
 868		mipsxx_pmu_write_control(2, 575<<5);
 869		mipspmu.write_counter(2, 0);
 870		fallthrough;
 871	case 2:
 872		mipsxx_pmu_write_control(1, 0);
 873		mipspmu.write_counter(1, 0);
 874		mipsxx_pmu_write_control(1, 127<<5);
 875		mipspmu.write_counter(1, 0);
 876		mipsxx_pmu_write_control(1, 191<<5);
 877		mipspmu.write_counter(1, 0);
 878		mipsxx_pmu_write_control(1, 255<<5);
 879		mipspmu.write_counter(1, 0);
 880		mipsxx_pmu_write_control(1, 319<<5);
 881		mipspmu.write_counter(1, 0);
 882		mipsxx_pmu_write_control(1, 383<<5);
 883		mipspmu.write_counter(1, 0);
 884		mipsxx_pmu_write_control(1, 575<<5);
 885		mipspmu.write_counter(1, 0);
 886		fallthrough;
 887	case 1:
 888		mipsxx_pmu_write_control(0, 0);
 889		mipspmu.write_counter(0, 0);
 890		mipsxx_pmu_write_control(0, 127<<5);
 891		mipspmu.write_counter(0, 0);
 892		mipsxx_pmu_write_control(0, 191<<5);
 893		mipspmu.write_counter(0, 0);
 894		mipsxx_pmu_write_control(0, 255<<5);
 895		mipspmu.write_counter(0, 0);
 896		mipsxx_pmu_write_control(0, 319<<5);
 897		mipspmu.write_counter(0, 0);
 898		mipsxx_pmu_write_control(0, 383<<5);
 899		mipspmu.write_counter(0, 0);
 900		mipsxx_pmu_write_control(0, 575<<5);
 901		mipspmu.write_counter(0, 0);
 902		break;
 903	}
 904}
 905
 906static void reset_counters(void *arg)
 907{
 908	int counters = (int)(long)arg;
 909
 910	if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) {
 911		loongson3_reset_counters(arg);
 912		return;
 913	}
 914
 915	switch (counters) {
 916	case 4:
 917		mipsxx_pmu_write_control(3, 0);
 918		mipspmu.write_counter(3, 0);
 919		fallthrough;
 920	case 3:
 921		mipsxx_pmu_write_control(2, 0);
 922		mipspmu.write_counter(2, 0);
 923		fallthrough;
 924	case 2:
 925		mipsxx_pmu_write_control(1, 0);
 926		mipspmu.write_counter(1, 0);
 927		fallthrough;
 928	case 1:
 929		mipsxx_pmu_write_control(0, 0);
 930		mipspmu.write_counter(0, 0);
 931		break;
 932	}
 933}
 934
 935/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
 936static const struct mips_perf_event mipsxxcore_event_map
 937				[PERF_COUNT_HW_MAX] = {
 938	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 939	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 940	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
 941	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 942};
 943
 944/* 74K/proAptiv core has different branch event code. */
 945static const struct mips_perf_event mipsxxcore_event_map2
 946				[PERF_COUNT_HW_MAX] = {
 947	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 948	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 949	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
 950	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
 951};
 952
 953static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
 954	[PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },
 955	[PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },
 956	/* These only count dcache, not icache */
 957	[PERF_COUNT_HW_CACHE_REFERENCES]    = { 0x45, CNTR_EVEN | CNTR_ODD },
 958	[PERF_COUNT_HW_CACHE_MISSES]        = { 0x48, CNTR_EVEN | CNTR_ODD },
 959	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
 960	[PERF_COUNT_HW_BRANCH_MISSES]       = { 0x16, CNTR_EVEN | CNTR_ODD },
 961};
 962
 963static const struct mips_perf_event loongson3_event_map1[PERF_COUNT_HW_MAX] = {
 964	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
 965	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
 966	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
 967	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
 968};
 969
 970static const struct mips_perf_event loongson3_event_map2[PERF_COUNT_HW_MAX] = {
 971	[PERF_COUNT_HW_CPU_CYCLES] = { 0x80, CNTR_ALL },
 972	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x81, CNTR_ALL },
 973	[PERF_COUNT_HW_CACHE_MISSES] = { 0x18, CNTR_ALL },
 974	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x94, CNTR_ALL },
 975	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x9c, CNTR_ALL },
 976};
 977
 978static const struct mips_perf_event loongson3_event_map3[PERF_COUNT_HW_MAX] = {
 979	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_ALL },
 980	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_ALL },
 981	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x1c, CNTR_ALL },
 982	[PERF_COUNT_HW_CACHE_MISSES] = { 0x1d, CNTR_ALL },
 983	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_ALL },
 984	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x08, CNTR_ALL },
 985};
 986
 987static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
 988	[PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
 989	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
 990	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
 991	[PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL	 },
 992	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
 993	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
 994	[PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
 995};
 996
 997static const struct mips_perf_event bmips5000_event_map
 998				[PERF_COUNT_HW_MAX] = {
 999	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
1000	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
1001	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
1002};
1003
1004/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
1005static const struct mips_perf_event mipsxxcore_cache_map
1006				[PERF_COUNT_HW_CACHE_MAX]
1007				[PERF_COUNT_HW_CACHE_OP_MAX]
1008				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1009[C(L1D)] = {
1010	/*
1011	 * Like some other architectures (e.g. ARM), the performance
1012	 * counters don't differentiate between read and write
1013	 * accesses/misses, so this isn't strictly correct, but it's the
1014	 * best we can do. Writes and reads get combined.
1015	 */
1016	[C(OP_READ)] = {
1017		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
1018		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1019	},
1020	[C(OP_WRITE)] = {
1021		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
1022		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1023	},
1024},
1025[C(L1I)] = {
1026	[C(OP_READ)] = {
1027		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
1028		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
1029	},
1030	[C(OP_WRITE)] = {
1031		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
1032		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
1033	},
1034	[C(OP_PREFETCH)] = {
1035		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
1036		/*
1037		 * Note that MIPS has only "hit" events countable for
1038		 * the prefetch operation.
1039		 */
1040	},
1041},
1042[C(LL)] = {
1043	[C(OP_READ)] = {
1044		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
1045		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
1046	},
1047	[C(OP_WRITE)] = {
1048		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
1049		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
1050	},
1051},
1052[C(DTLB)] = {
1053	[C(OP_READ)] = {
1054		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1055		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1056	},
1057	[C(OP_WRITE)] = {
1058		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1059		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1060	},
1061},
1062[C(ITLB)] = {
1063	[C(OP_READ)] = {
1064		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
1065		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
1066	},
1067	[C(OP_WRITE)] = {
1068		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
1069		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
1070	},
1071},
1072[C(BPU)] = {
1073	/* Using the same code for *HW_BRANCH* */
1074	[C(OP_READ)] = {
1075		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
1076		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1077	},
1078	[C(OP_WRITE)] = {
1079		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
1080		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1081	},
1082},
1083};
1084
1085/* 74K/proAptiv core has completely different cache event map. */
1086static const struct mips_perf_event mipsxxcore_cache_map2
1087				[PERF_COUNT_HW_CACHE_MAX]
1088				[PERF_COUNT_HW_CACHE_OP_MAX]
1089				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1090[C(L1D)] = {
1091	/*
1092	 * Like some other architectures (e.g. ARM), the performance
1093	 * counters don't differentiate between read and write
1094	 * accesses/misses, so this isn't strictly correct, but it's the
1095	 * best we can do. Writes and reads get combined.
1096	 */
1097	[C(OP_READ)] = {
1098		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
1099		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
1100	},
1101	[C(OP_WRITE)] = {
1102		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
1103		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
1104	},
1105},
1106[C(L1I)] = {
1107	[C(OP_READ)] = {
1108		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1109		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1110	},
1111	[C(OP_WRITE)] = {
1112		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1113		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
1114	},
1115	[C(OP_PREFETCH)] = {
1116		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
1117		/*
1118		 * Note that MIPS has only "hit" events countable for
1119		 * the prefetch operation.
1120		 */
1121	},
1122},
1123[C(LL)] = {
1124	[C(OP_READ)] = {
1125		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
1126		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
1127	},
1128	[C(OP_WRITE)] = {
1129		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
1130		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
1131	},
1132},
1133/*
1134 * 74K core does not have specific DTLB events. proAptiv core has
1135 * "speculative" DTLB events which are numbered 0x63 (even/odd) and
1136 * not included here. One can use raw events if really needed.
1137 */
1138[C(ITLB)] = {
1139	[C(OP_READ)] = {
1140		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1141		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1142	},
1143	[C(OP_WRITE)] = {
1144		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1145		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1146	},
1147},
1148[C(BPU)] = {
1149	/* Using the same code for *HW_BRANCH* */
1150	[C(OP_READ)] = {
1151		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1152		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1153	},
1154	[C(OP_WRITE)] = {
1155		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1156		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1157	},
1158},
1159};
1160
1161static const struct mips_perf_event i6x00_cache_map
1162				[PERF_COUNT_HW_CACHE_MAX]
1163				[PERF_COUNT_HW_CACHE_OP_MAX]
1164				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1165[C(L1D)] = {
1166	[C(OP_READ)] = {
1167		[C(RESULT_ACCESS)]	= { 0x46, CNTR_EVEN | CNTR_ODD },
1168		[C(RESULT_MISS)]	= { 0x49, CNTR_EVEN | CNTR_ODD },
1169	},
1170	[C(OP_WRITE)] = {
1171		[C(RESULT_ACCESS)]	= { 0x47, CNTR_EVEN | CNTR_ODD },
1172		[C(RESULT_MISS)]	= { 0x4a, CNTR_EVEN | CNTR_ODD },
1173	},
1174},
1175[C(L1I)] = {
1176	[C(OP_READ)] = {
1177		[C(RESULT_ACCESS)]	= { 0x84, CNTR_EVEN | CNTR_ODD },
1178		[C(RESULT_MISS)]	= { 0x85, CNTR_EVEN | CNTR_ODD },
1179	},
1180},
1181[C(DTLB)] = {
1182	/* Can't distinguish read & write */
1183	[C(OP_READ)] = {
1184		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
1185		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
1186	},
1187	[C(OP_WRITE)] = {
1188		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
1189		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
1190	},
1191},
1192[C(BPU)] = {
1193	/* Conditional branches / mispredicted */
1194	[C(OP_READ)] = {
1195		[C(RESULT_ACCESS)]	= { 0x15, CNTR_EVEN | CNTR_ODD },
1196		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN | CNTR_ODD },
1197	},
1198},
1199};
1200
1201static const struct mips_perf_event loongson3_cache_map1
1202				[PERF_COUNT_HW_CACHE_MAX]
1203				[PERF_COUNT_HW_CACHE_OP_MAX]
1204				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1205[C(L1D)] = {
1206	/*
1207	 * Like some other architectures (e.g. ARM), the performance
1208	 * counters don't differentiate between read and write
1209	 * accesses/misses, so this isn't strictly correct, but it's the
1210	 * best we can do. Writes and reads get combined.
1211	 */
1212	[C(OP_READ)] = {
1213		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1214	},
1215	[C(OP_WRITE)] = {
1216		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1217	},
1218},
1219[C(L1I)] = {
1220	[C(OP_READ)] = {
1221		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1222	},
1223	[C(OP_WRITE)] = {
1224		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1225	},
1226},
1227[C(DTLB)] = {
1228	[C(OP_READ)] = {
1229		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1230	},
1231	[C(OP_WRITE)] = {
1232		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1233	},
1234},
1235[C(ITLB)] = {
1236	[C(OP_READ)] = {
1237		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1238	},
1239	[C(OP_WRITE)] = {
1240		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1241	},
1242},
1243[C(BPU)] = {
1244	/* Using the same code for *HW_BRANCH* */
1245	[C(OP_READ)] = {
1246		[C(RESULT_ACCESS)]      = { 0x01, CNTR_EVEN },
1247		[C(RESULT_MISS)]        = { 0x01, CNTR_ODD },
1248	},
1249	[C(OP_WRITE)] = {
1250		[C(RESULT_ACCESS)]      = { 0x01, CNTR_EVEN },
1251		[C(RESULT_MISS)]        = { 0x01, CNTR_ODD },
1252	},
1253},
1254};
1255
1256static const struct mips_perf_event loongson3_cache_map2
1257				[PERF_COUNT_HW_CACHE_MAX]
1258				[PERF_COUNT_HW_CACHE_OP_MAX]
1259				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1260[C(L1D)] = {
1261	/*
1262	 * Like some other architectures (e.g. ARM), the performance
1263	 * counters don't differentiate between read and write
1264	 * accesses/misses, so this isn't strictly correct, but it's the
1265	 * best we can do. Writes and reads get combined.
1266	 */
1267	[C(OP_READ)] = {
1268		[C(RESULT_ACCESS)]	= { 0x156, CNTR_ALL },
1269	},
1270	[C(OP_WRITE)] = {
1271		[C(RESULT_ACCESS)]	= { 0x155, CNTR_ALL },
1272		[C(RESULT_MISS)]        = { 0x153, CNTR_ALL },
1273	},
1274},
1275[C(L1I)] = {
1276	[C(OP_READ)] = {
1277		[C(RESULT_MISS)]	= { 0x18, CNTR_ALL },
1278	},
1279	[C(OP_WRITE)] = {
1280		[C(RESULT_MISS)]        = { 0x18, CNTR_ALL },
1281	},
1282},
1283[C(LL)] = {
1284	[C(OP_READ)] = {
1285		[C(RESULT_ACCESS)]	= { 0x1b6, CNTR_ALL },
1286	},
1287	[C(OP_WRITE)] = {
1288		[C(RESULT_ACCESS)]	= { 0x1b7, CNTR_ALL },
1289	},
1290	[C(OP_PREFETCH)] = {
1291		[C(RESULT_ACCESS)]	= { 0x1bf, CNTR_ALL },
1292	},
1293},
1294[C(DTLB)] = {
1295	[C(OP_READ)] = {
1296		[C(RESULT_MISS)]        = { 0x92, CNTR_ALL },
1297	},
1298	[C(OP_WRITE)] = {
1299		[C(RESULT_MISS)]        = { 0x92, CNTR_ALL },
1300	},
1301},
1302[C(ITLB)] = {
1303	[C(OP_READ)] = {
1304		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1305	},
1306	[C(OP_WRITE)] = {
1307		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1308	},
1309},
1310[C(BPU)] = {
1311	/* Using the same code for *HW_BRANCH* */
1312	[C(OP_READ)] = {
1313		[C(RESULT_ACCESS)]      = { 0x94, CNTR_ALL },
1314		[C(RESULT_MISS)]        = { 0x9c, CNTR_ALL },
1315	},
1316},
1317};
1318
1319static const struct mips_perf_event loongson3_cache_map3
1320				[PERF_COUNT_HW_CACHE_MAX]
1321				[PERF_COUNT_HW_CACHE_OP_MAX]
1322				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1323[C(L1D)] = {
1324	/*
1325	 * Like some other architectures (e.g. ARM), the performance
1326	 * counters don't differentiate between read and write
1327	 * accesses/misses, so this isn't strictly correct, but it's the
1328	 * best we can do. Writes and reads get combined.
1329	 */
1330	[C(OP_READ)] = {
1331		[C(RESULT_ACCESS)]      = { 0x1e, CNTR_ALL },
1332		[C(RESULT_MISS)]        = { 0x1f, CNTR_ALL },
1333	},
1334	[C(OP_PREFETCH)] = {
1335		[C(RESULT_ACCESS)]	= { 0xaa, CNTR_ALL },
1336		[C(RESULT_MISS)]	= { 0xa9, CNTR_ALL },
1337	},
1338},
1339[C(L1I)] = {
1340	[C(OP_READ)] = {
1341		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ALL },
1342		[C(RESULT_MISS)]	= { 0x1d, CNTR_ALL },
1343	},
1344},
1345[C(LL)] = {
1346	[C(OP_READ)] = {
1347		[C(RESULT_ACCESS)]	= { 0x2e, CNTR_ALL },
1348		[C(RESULT_MISS)]	= { 0x2f, CNTR_ALL },
1349	},
1350},
1351[C(DTLB)] = {
1352	[C(OP_READ)] = {
1353		[C(RESULT_ACCESS)]      = { 0x14, CNTR_ALL },
1354		[C(RESULT_MISS)]	= { 0x1b, CNTR_ALL },
1355	},
1356},
1357[C(ITLB)] = {
1358	[C(OP_READ)] = {
1359		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1360	},
1361},
1362[C(BPU)] = {
1363	/* Using the same code for *HW_BRANCH* */
1364	[C(OP_READ)] = {
1365		[C(RESULT_ACCESS)]      = { 0x02, CNTR_ALL },
1366		[C(RESULT_MISS)]        = { 0x08, CNTR_ALL },
1367	},
1368},
1369};
1370
1371/* BMIPS5000 */
1372static const struct mips_perf_event bmips5000_cache_map
1373				[PERF_COUNT_HW_CACHE_MAX]
1374				[PERF_COUNT_HW_CACHE_OP_MAX]
1375				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1376[C(L1D)] = {
1377	/*
1378	 * Like some other architectures (e.g. ARM), the performance
1379	 * counters don't differentiate between read and write
1380	 * accesses/misses, so this isn't strictly correct, but it's the
1381	 * best we can do. Writes and reads get combined.
1382	 */
1383	[C(OP_READ)] = {
1384		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1385		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1386	},
1387	[C(OP_WRITE)] = {
1388		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1389		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1390	},
1391},
1392[C(L1I)] = {
1393	[C(OP_READ)] = {
1394		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1395		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1396	},
1397	[C(OP_WRITE)] = {
1398		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1399		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1400	},
1401	[C(OP_PREFETCH)] = {
1402		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1403		/*
1404		 * Note that MIPS has only "hit" events countable for
1405		 * the prefetch operation.
1406		 */
1407	},
1408},
1409[C(LL)] = {
1410	[C(OP_READ)] = {
1411		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1412		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
1413	},
1414	[C(OP_WRITE)] = {
1415		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1416		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
1417	},
1418},
1419[C(BPU)] = {
1420	/* Using the same code for *HW_BRANCH* */
1421	[C(OP_READ)] = {
1422		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1423	},
1424	[C(OP_WRITE)] = {
1425		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1426	},
1427},
1428};
1429
1430static const struct mips_perf_event octeon_cache_map
1431				[PERF_COUNT_HW_CACHE_MAX]
1432				[PERF_COUNT_HW_CACHE_OP_MAX]
1433				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1434[C(L1D)] = {
1435	[C(OP_READ)] = {
1436		[C(RESULT_ACCESS)]	= { 0x2b, CNTR_ALL },
1437		[C(RESULT_MISS)]	= { 0x2e, CNTR_ALL },
1438	},
1439	[C(OP_WRITE)] = {
1440		[C(RESULT_ACCESS)]	= { 0x30, CNTR_ALL },
1441	},
1442},
1443[C(L1I)] = {
1444	[C(OP_READ)] = {
1445		[C(RESULT_ACCESS)]	= { 0x18, CNTR_ALL },
1446	},
1447	[C(OP_PREFETCH)] = {
1448		[C(RESULT_ACCESS)]	= { 0x19, CNTR_ALL },
1449	},
1450},
1451[C(DTLB)] = {
1452	/*
1453	 * Only general DTLB misses are counted use the same event for
1454	 * read and write.
1455	 */
1456	[C(OP_READ)] = {
1457		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
1458	},
1459	[C(OP_WRITE)] = {
1460		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
1461	},
1462},
1463[C(ITLB)] = {
1464	[C(OP_READ)] = {
1465		[C(RESULT_MISS)]	= { 0x37, CNTR_ALL },
1466	},
1467},
1468};
1469
1470static int __hw_perf_event_init(struct perf_event *event)
1471{
1472	struct perf_event_attr *attr = &event->attr;
1473	struct hw_perf_event *hwc = &event->hw;
1474	const struct mips_perf_event *pev;
1475	int err;
1476
1477	/* Returning MIPS event descriptor for generic perf event. */
1478	if (PERF_TYPE_HARDWARE == event->attr.type) {
1479		if (event->attr.config >= PERF_COUNT_HW_MAX)
1480			return -EINVAL;
1481		pev = mipspmu_map_general_event(event->attr.config);
1482	} else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1483		pev = mipspmu_map_cache_event(event->attr.config);
1484	} else if (PERF_TYPE_RAW == event->attr.type) {
1485		/* We are working on the global raw event. */
1486		mutex_lock(&raw_event_mutex);
1487		pev = mipspmu.map_raw_event(event->attr.config);
1488	} else {
1489		/* The event type is not (yet) supported. */
1490		return -EOPNOTSUPP;
1491	}
1492
1493	if (IS_ERR(pev)) {
1494		if (PERF_TYPE_RAW == event->attr.type)
1495			mutex_unlock(&raw_event_mutex);
1496		return PTR_ERR(pev);
1497	}
1498
1499	/*
1500	 * We allow max flexibility on how each individual counter shared
1501	 * by the single CPU operates (the mode exclusion and the range).
1502	 */
1503	hwc->config_base = MIPS_PERFCTRL_IE;
1504
1505	hwc->event_base = mipspmu_perf_event_encode(pev);
1506	if (PERF_TYPE_RAW == event->attr.type)
1507		mutex_unlock(&raw_event_mutex);
1508
1509	if (!attr->exclude_user)
1510		hwc->config_base |= MIPS_PERFCTRL_U;
1511	if (!attr->exclude_kernel) {
1512		hwc->config_base |= MIPS_PERFCTRL_K;
1513		/* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1514		hwc->config_base |= MIPS_PERFCTRL_EXL;
1515	}
1516	if (!attr->exclude_hv)
1517		hwc->config_base |= MIPS_PERFCTRL_S;
1518
1519	hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1520	/*
1521	 * The event can belong to another cpu. We do not assign a local
1522	 * counter for it for now.
1523	 */
1524	hwc->idx = -1;
1525	hwc->config = 0;
1526
1527	if (!hwc->sample_period) {
1528		hwc->sample_period  = mipspmu.max_period;
1529		hwc->last_period    = hwc->sample_period;
1530		local64_set(&hwc->period_left, hwc->sample_period);
1531	}
1532
1533	err = 0;
1534	if (event->group_leader != event)
1535		err = validate_group(event);
1536
1537	event->destroy = hw_perf_event_destroy;
1538
1539	if (err)
1540		event->destroy(event);
1541
1542	return err;
1543}
1544
1545static void pause_local_counters(void)
1546{
1547	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1548	int ctr = mipspmu.num_counters;
1549	unsigned long flags;
1550
1551	local_irq_save(flags);
1552	do {
1553		ctr--;
1554		cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1555		mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1556					 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1557	} while (ctr > 0);
1558	local_irq_restore(flags);
1559}
1560
1561static void resume_local_counters(void)
1562{
1563	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1564	int ctr = mipspmu.num_counters;
1565
1566	do {
1567		ctr--;
1568		mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1569	} while (ctr > 0);
1570}
1571
1572static int mipsxx_pmu_handle_shared_irq(void)
1573{
1574	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1575	struct perf_sample_data data;
1576	unsigned int counters = mipspmu.num_counters;
1577	u64 counter;
1578	int n, handled = IRQ_NONE;
1579	struct pt_regs *regs;
1580
1581	if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1582		return handled;
1583	/*
1584	 * First we pause the local counters, so that when we are locked
1585	 * here, the counters are all paused. When it gets locked due to
1586	 * perf_disable(), the timer interrupt handler will be delayed.
1587	 *
1588	 * See also mipsxx_pmu_start().
1589	 */
1590	pause_local_counters();
1591#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1592	read_lock(&pmuint_rwlock);
1593#endif
1594
1595	regs = get_irq_regs();
1596
1597	perf_sample_data_init(&data, 0, 0);
1598
1599	for (n = counters - 1; n >= 0; n--) {
1600		if (!test_bit(n, cpuc->used_mask))
1601			continue;
1602
1603		counter = mipspmu.read_counter(n);
1604		if (!(counter & mipspmu.overflow))
1605			continue;
1606
1607		handle_associated_event(cpuc, n, &data, regs);
1608		handled = IRQ_HANDLED;
1609	}
1610
1611#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1612	read_unlock(&pmuint_rwlock);
1613#endif
1614	resume_local_counters();
1615
1616	/*
1617	 * Do all the work for the pending perf events. We can do this
1618	 * in here because the performance counter interrupt is a regular
1619	 * interrupt, not NMI.
1620	 */
1621	if (handled == IRQ_HANDLED)
1622		irq_work_run();
1623
1624	return handled;
1625}
1626
1627static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1628{
1629	return mipsxx_pmu_handle_shared_irq();
1630}
1631
1632/* 24K */
1633#define IS_BOTH_COUNTERS_24K_EVENT(b)					\
1634	((b) == 0 || (b) == 1 || (b) == 11)
1635
1636/* 34K */
1637#define IS_BOTH_COUNTERS_34K_EVENT(b)					\
1638	((b) == 0 || (b) == 1 || (b) == 11)
1639#ifdef CONFIG_MIPS_MT_SMP
1640#define IS_RANGE_P_34K_EVENT(r, b)					\
1641	((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||		\
1642	 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||		\
1643	 (r) == 176 || ((b) >= 50 && (b) <= 55) ||			\
1644	 ((b) >= 64 && (b) <= 67))
1645#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1646#endif
1647
1648/* 74K */
1649#define IS_BOTH_COUNTERS_74K_EVENT(b)					\
1650	((b) == 0 || (b) == 1)
1651
1652/* proAptiv */
1653#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b)				\
1654	((b) == 0 || (b) == 1)
1655/* P5600 */
1656#define IS_BOTH_COUNTERS_P5600_EVENT(b)					\
1657	((b) == 0 || (b) == 1)
1658
1659/* 1004K */
1660#define IS_BOTH_COUNTERS_1004K_EVENT(b)					\
1661	((b) == 0 || (b) == 1 || (b) == 11)
1662#ifdef CONFIG_MIPS_MT_SMP
1663#define IS_RANGE_P_1004K_EVENT(r, b)					\
1664	((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||		\
1665	 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||		\
1666	 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||	\
1667	 (r) == 188 || (b) == 61 || (b) == 62 ||			\
1668	 ((b) >= 64 && (b) <= 67))
1669#define IS_RANGE_V_1004K_EVENT(r)	((r) == 47)
1670#endif
1671
1672/* interAptiv */
1673#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b)				\
1674	((b) == 0 || (b) == 1 || (b) == 11)
1675#ifdef CONFIG_MIPS_MT_SMP
1676/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1677#define IS_RANGE_P_INTERAPTIV_EVENT(r, b)				\
1678	((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||		\
1679	 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 ||		\
1680	 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 &&		\
1681	 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 ||		\
1682	 ((b) >= 64 && (b) <= 67))
1683#define IS_RANGE_V_INTERAPTIV_EVENT(r)	((r) == 47 || (r) == 175)
1684#endif
1685
1686/* BMIPS5000 */
1687#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b)				\
1688	((b) == 0 || (b) == 1)
1689
1690
1691/*
1692 * For most cores the user can use 0-255 raw events, where 0-127 for the events
1693 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1694 * indicate the even/odd bank selector. So, for example, when user wants to take
1695 * the Event Num of 15 for odd counters (by referring to the user manual), then
1696 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1697 * to be used.
1698 *
1699 * Some newer cores have even more events, in which case the user can use raw
1700 * events 0-511, where 0-255 are for the events of even counters, and 256-511
1701 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1702 */
1703static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1704{
1705	/* currently most cores have 7-bit event numbers */
1706	int pmu_type;
1707	unsigned int raw_id = config & 0xff;
1708	unsigned int base_id = raw_id & 0x7f;
1709
1710	switch (current_cpu_type()) {
1711	case CPU_24K:
1712		if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1713			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1714		else
1715			raw_event.cntr_mask =
1716				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1717#ifdef CONFIG_MIPS_MT_SMP
1718		/*
1719		 * This is actually doing nothing. Non-multithreading
1720		 * CPUs will not check and calculate the range.
1721		 */
1722		raw_event.range = P;
1723#endif
1724		break;
1725	case CPU_34K:
1726		if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1727			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1728		else
1729			raw_event.cntr_mask =
1730				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1731#ifdef CONFIG_MIPS_MT_SMP
1732		if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1733			raw_event.range = P;
1734		else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1735			raw_event.range = V;
1736		else
1737			raw_event.range = T;
1738#endif
1739		break;
1740	case CPU_74K:
1741	case CPU_1074K:
1742		if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1743			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1744		else
1745			raw_event.cntr_mask =
1746				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1747#ifdef CONFIG_MIPS_MT_SMP
1748		raw_event.range = P;
1749#endif
1750		break;
1751	case CPU_PROAPTIV:
1752		if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1753			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1754		else
1755			raw_event.cntr_mask =
1756				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1757#ifdef CONFIG_MIPS_MT_SMP
1758		raw_event.range = P;
1759#endif
1760		break;
1761	case CPU_P5600:
1762	case CPU_P6600:
1763		/* 8-bit event numbers */
1764		raw_id = config & 0x1ff;
1765		base_id = raw_id & 0xff;
1766		if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1767			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1768		else
1769			raw_event.cntr_mask =
1770				raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1771#ifdef CONFIG_MIPS_MT_SMP
1772		raw_event.range = P;
1773#endif
1774		break;
1775	case CPU_I6400:
1776	case CPU_I6500:
1777		/* 8-bit event numbers */
1778		base_id = config & 0xff;
1779		raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1780		break;
1781	case CPU_1004K:
1782		if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1783			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1784		else
1785			raw_event.cntr_mask =
1786				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1787#ifdef CONFIG_MIPS_MT_SMP
1788		if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1789			raw_event.range = P;
1790		else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1791			raw_event.range = V;
1792		else
1793			raw_event.range = T;
1794#endif
1795		break;
1796	case CPU_INTERAPTIV:
1797		if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1798			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1799		else
1800			raw_event.cntr_mask =
1801				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1802#ifdef CONFIG_MIPS_MT_SMP
1803		if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1804			raw_event.range = P;
1805		else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1806			raw_event.range = V;
1807		else
1808			raw_event.range = T;
1809#endif
1810		break;
1811	case CPU_BMIPS5000:
1812		if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1813			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1814		else
1815			raw_event.cntr_mask =
1816				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1817		break;
1818	case CPU_LOONGSON64:
1819		pmu_type = get_loongson3_pmu_type();
1820
1821		switch (pmu_type) {
1822		case LOONGSON_PMU_TYPE1:
1823			raw_event.cntr_mask =
1824				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1825			break;
1826		case LOONGSON_PMU_TYPE2:
1827			base_id = config & 0x3ff;
1828			raw_event.cntr_mask = CNTR_ALL;
1829
1830			if ((base_id >= 1 && base_id < 28) ||
1831				(base_id >= 64 && base_id < 90) ||
1832				(base_id >= 128 && base_id < 164) ||
1833				(base_id >= 192 && base_id < 200) ||
1834				(base_id >= 256 && base_id < 275) ||
1835				(base_id >= 320 && base_id < 361) ||
1836				(base_id >= 384 && base_id < 574))
1837				break;
1838
1839			return ERR_PTR(-EOPNOTSUPP);
1840		case LOONGSON_PMU_TYPE3:
1841			base_id = raw_id;
1842			raw_event.cntr_mask = CNTR_ALL;
1843			break;
1844		}
1845		break;
1846	}
1847
1848	raw_event.event_id = base_id;
1849
1850	return &raw_event;
1851}
1852
1853static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1854{
1855	unsigned int base_id = config & 0x7f;
1856	unsigned int event_max;
1857
1858
1859	raw_event.cntr_mask = CNTR_ALL;
1860	raw_event.event_id = base_id;
1861
1862	if (current_cpu_type() == CPU_CAVIUM_OCTEON3)
1863		event_max = 0x5f;
1864	else if (current_cpu_type() == CPU_CAVIUM_OCTEON2)
1865		event_max = 0x42;
1866	else
1867		event_max = 0x3a;
1868
1869	if (base_id > event_max) {
1870		return ERR_PTR(-EOPNOTSUPP);
1871	}
1872
1873	switch (base_id) {
1874	case 0x00:
1875	case 0x0f:
1876	case 0x1e:
1877	case 0x1f:
1878	case 0x2f:
1879	case 0x34:
1880	case 0x3e ... 0x3f:
1881		return ERR_PTR(-EOPNOTSUPP);
1882	default:
1883		break;
1884	}
1885
1886	return &raw_event;
1887}
1888
1889static int __init
1890init_hw_perf_events(void)
1891{
1892	int counters, irq, pmu_type;
1893
1894	pr_info("Performance counters: ");
1895
1896	counters = n_counters();
1897	if (counters == 0) {
1898		pr_cont("No available PMU.\n");
1899		return -ENODEV;
1900	}
1901
1902#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1903	if (!cpu_has_mipsmt_pertccounters)
1904		counters = counters_total_to_per_cpu(counters);
1905#endif
1906
1907	if (get_c0_perfcount_int)
1908		irq = get_c0_perfcount_int();
1909	else if (cp0_perfcount_irq >= 0)
1910		irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1911	else
1912		irq = -1;
1913
1914	mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1915
1916	switch (current_cpu_type()) {
1917	case CPU_24K:
1918		mipspmu.name = "mips/24K";
1919		mipspmu.general_event_map = &mipsxxcore_event_map;
1920		mipspmu.cache_event_map = &mipsxxcore_cache_map;
1921		break;
1922	case CPU_34K:
1923		mipspmu.name = "mips/34K";
1924		mipspmu.general_event_map = &mipsxxcore_event_map;
1925		mipspmu.cache_event_map = &mipsxxcore_cache_map;
1926		break;
1927	case CPU_74K:
1928		mipspmu.name = "mips/74K";
1929		mipspmu.general_event_map = &mipsxxcore_event_map2;
1930		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1931		break;
1932	case CPU_PROAPTIV:
1933		mipspmu.name = "mips/proAptiv";
1934		mipspmu.general_event_map = &mipsxxcore_event_map2;
1935		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1936		break;
1937	case CPU_P5600:
1938		mipspmu.name = "mips/P5600";
1939		mipspmu.general_event_map = &mipsxxcore_event_map2;
1940		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1941		break;
1942	case CPU_P6600:
1943		mipspmu.name = "mips/P6600";
1944		mipspmu.general_event_map = &mipsxxcore_event_map2;
1945		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1946		break;
1947	case CPU_I6400:
1948		mipspmu.name = "mips/I6400";
1949		mipspmu.general_event_map = &i6x00_event_map;
1950		mipspmu.cache_event_map = &i6x00_cache_map;
1951		break;
1952	case CPU_I6500:
1953		mipspmu.name = "mips/I6500";
1954		mipspmu.general_event_map = &i6x00_event_map;
1955		mipspmu.cache_event_map = &i6x00_cache_map;
1956		break;
1957	case CPU_1004K:
1958		mipspmu.name = "mips/1004K";
1959		mipspmu.general_event_map = &mipsxxcore_event_map;
1960		mipspmu.cache_event_map = &mipsxxcore_cache_map;
1961		break;
1962	case CPU_1074K:
1963		mipspmu.name = "mips/1074K";
1964		mipspmu.general_event_map = &mipsxxcore_event_map;
1965		mipspmu.cache_event_map = &mipsxxcore_cache_map;
1966		break;
1967	case CPU_INTERAPTIV:
1968		mipspmu.name = "mips/interAptiv";
1969		mipspmu.general_event_map = &mipsxxcore_event_map;
1970		mipspmu.cache_event_map = &mipsxxcore_cache_map;
1971		break;
1972	case CPU_LOONGSON32:
1973		mipspmu.name = "mips/loongson1";
1974		mipspmu.general_event_map = &mipsxxcore_event_map;
1975		mipspmu.cache_event_map = &mipsxxcore_cache_map;
1976		break;
1977	case CPU_LOONGSON64:
1978		mipspmu.name = "mips/loongson3";
1979		pmu_type = get_loongson3_pmu_type();
1980
1981		switch (pmu_type) {
1982		case LOONGSON_PMU_TYPE1:
1983			counters = 2;
1984			mipspmu.general_event_map = &loongson3_event_map1;
1985			mipspmu.cache_event_map = &loongson3_cache_map1;
1986			break;
1987		case LOONGSON_PMU_TYPE2:
1988			counters = 4;
1989			mipspmu.general_event_map = &loongson3_event_map2;
1990			mipspmu.cache_event_map = &loongson3_cache_map2;
1991			break;
1992		case LOONGSON_PMU_TYPE3:
1993			counters = 4;
1994			mipspmu.general_event_map = &loongson3_event_map3;
1995			mipspmu.cache_event_map = &loongson3_cache_map3;
1996			break;
1997		}
1998		break;
1999	case CPU_CAVIUM_OCTEON:
2000	case CPU_CAVIUM_OCTEON_PLUS:
2001	case CPU_CAVIUM_OCTEON2:
2002	case CPU_CAVIUM_OCTEON3:
2003		mipspmu.name = "octeon";
2004		mipspmu.general_event_map = &octeon_event_map;
2005		mipspmu.cache_event_map = &octeon_cache_map;
2006		mipspmu.map_raw_event = octeon_pmu_map_raw_event;
2007		break;
2008	case CPU_BMIPS5000:
2009		mipspmu.name = "BMIPS5000";
2010		mipspmu.general_event_map = &bmips5000_event_map;
2011		mipspmu.cache_event_map = &bmips5000_cache_map;
2012		break;
2013	default:
2014		pr_cont("Either hardware does not support performance "
2015			"counters, or not yet implemented.\n");
2016		return -ENODEV;
2017	}
2018
2019	mipspmu.num_counters = counters;
2020	mipspmu.irq = irq;
2021
2022	if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
2023		if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) {
2024			counter_bits = 48;
2025			mipspmu.max_period = (1ULL << 47) - 1;
2026			mipspmu.valid_count = (1ULL << 47) - 1;
2027			mipspmu.overflow = 1ULL << 47;
2028		} else {
2029			counter_bits = 64;
2030			mipspmu.max_period = (1ULL << 63) - 1;
2031			mipspmu.valid_count = (1ULL << 63) - 1;
2032			mipspmu.overflow = 1ULL << 63;
2033		}
2034		mipspmu.read_counter = mipsxx_pmu_read_counter_64;
2035		mipspmu.write_counter = mipsxx_pmu_write_counter_64;
2036	} else {
2037		counter_bits = 32;
2038		mipspmu.max_period = (1ULL << 31) - 1;
2039		mipspmu.valid_count = (1ULL << 31) - 1;
2040		mipspmu.overflow = 1ULL << 31;
2041		mipspmu.read_counter = mipsxx_pmu_read_counter;
2042		mipspmu.write_counter = mipsxx_pmu_write_counter;
2043	}
2044
2045	on_each_cpu(reset_counters, (void *)(long)counters, 1);
2046
2047	pr_cont("%s PMU enabled, %d %d-bit counters available to each "
2048		"CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
2049		irq < 0 ? " (share with timer interrupt)" : "");
2050
2051	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2052
2053	return 0;
2054}
2055early_initcall(init_hw_perf_events);