mips-cm.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2013 Imagination Technologies
  4 * Author: Paul Burton <paul.burton@mips.com>
  5 */
  6
  7#include <linux/errno.h>
  8#include <linux/of.h>
  9#include <linux/percpu.h>
 10#include <linux/spinlock.h>
 11
 12#include <asm/mips-cps.h>
 13#include <asm/smp-cps.h>
 14#include <asm/mipsregs.h>
 15
 16void __iomem *mips_gcr_base;
 17void __iomem *mips_cm_l2sync_base;
 18int mips_cm_is64;
 19bool mips_cm_is_l2_hci_broken;
 20
 21static char *cm2_tr[8] = {
 22	"mem",	"gcr",	"gic",	"mmio",
 23	"0x04", "cpc", "0x06", "0x07"
 24};
 25
 26/* CM3 Tag ECC transaction type */
 27static char *cm3_tr[16] = {
 28	[0x0] = "ReqNoData",
 29	[0x1] = "0x1",
 30	[0x2] = "ReqWData",
 31	[0x3] = "0x3",
 32	[0x4] = "IReqNoResp",
 33	[0x5] = "IReqWResp",
 34	[0x6] = "IReqNoRespDat",
 35	[0x7] = "IReqWRespDat",
 36	[0x8] = "RespNoData",
 37	[0x9] = "RespDataFol",
 38	[0xa] = "RespWData",
 39	[0xb] = "RespDataOnly",
 40	[0xc] = "IRespNoData",
 41	[0xd] = "IRespDataFol",
 42	[0xe] = "IRespWData",
 43	[0xf] = "IRespDataOnly"
 44};
 45
 46static char *cm2_cmd[32] = {
 47	[0x00] = "0x00",
 48	[0x01] = "Legacy Write",
 49	[0x02] = "Legacy Read",
 50	[0x03] = "0x03",
 51	[0x04] = "0x04",
 52	[0x05] = "0x05",
 53	[0x06] = "0x06",
 54	[0x07] = "0x07",
 55	[0x08] = "Coherent Read Own",
 56	[0x09] = "Coherent Read Share",
 57	[0x0a] = "Coherent Read Discard",
 58	[0x0b] = "Coherent Ready Share Always",
 59	[0x0c] = "Coherent Upgrade",
 60	[0x0d] = "Coherent Writeback",
 61	[0x0e] = "0x0e",
 62	[0x0f] = "0x0f",
 63	[0x10] = "Coherent Copyback",
 64	[0x11] = "Coherent Copyback Invalidate",
 65	[0x12] = "Coherent Invalidate",
 66	[0x13] = "Coherent Write Invalidate",
 67	[0x14] = "Coherent Completion Sync",
 68	[0x15] = "0x15",
 69	[0x16] = "0x16",
 70	[0x17] = "0x17",
 71	[0x18] = "0x18",
 72	[0x19] = "0x19",
 73	[0x1a] = "0x1a",
 74	[0x1b] = "0x1b",
 75	[0x1c] = "0x1c",
 76	[0x1d] = "0x1d",
 77	[0x1e] = "0x1e",
 78	[0x1f] = "0x1f"
 79};
 80
 81/* CM3 Tag ECC command type */
 82static char *cm3_cmd[16] = {
 83	[0x0] = "Legacy Read",
 84	[0x1] = "Legacy Write",
 85	[0x2] = "Coherent Read Own",
 86	[0x3] = "Coherent Read Share",
 87	[0x4] = "Coherent Read Discard",
 88	[0x5] = "Coherent Evicted",
 89	[0x6] = "Coherent Upgrade",
 90	[0x7] = "Coherent Upgrade for Store Conditional",
 91	[0x8] = "Coherent Writeback",
 92	[0x9] = "Coherent Write Invalidate",
 93	[0xa] = "0xa",
 94	[0xb] = "0xb",
 95	[0xc] = "0xc",
 96	[0xd] = "0xd",
 97	[0xe] = "0xe",
 98	[0xf] = "0xf"
 99};
100
101/* CM3 Tag ECC command group */
102static char *cm3_cmd_group[8] = {
103	[0x0] = "Normal",
104	[0x1] = "Registers",
105	[0x2] = "TLB",
106	[0x3] = "0x3",
107	[0x4] = "L1I",
108	[0x5] = "L1D",
109	[0x6] = "L3",
110	[0x7] = "L2"
111};
112
113static char *cm2_core[8] = {
114	"Invalid/OK",	"Invalid/Data",
115	"Shared/OK",	"Shared/Data",
116	"Modified/OK",	"Modified/Data",
117	"Exclusive/OK", "Exclusive/Data"
118};
119
120static char *cm2_l2_type[4] = {
121	[0x0] = "None",
122	[0x1] = "Tag RAM single/double ECC error",
123	[0x2] = "Data RAM single/double ECC error",
124	[0x3] = "WS RAM uncorrectable dirty parity"
125};
126
127static char *cm2_l2_instr[32] = {
128	[0x00] = "L2_NOP",
129	[0x01] = "L2_ERR_CORR",
130	[0x02] = "L2_TAG_INV",
131	[0x03] = "L2_WS_CLEAN",
132	[0x04] = "L2_RD_MDYFY_WR",
133	[0x05] = "L2_WS_MRU",
134	[0x06] = "L2_EVICT_LN2",
135	[0x07] = "0x07",
136	[0x08] = "L2_EVICT",
137	[0x09] = "L2_REFL",
138	[0x0a] = "L2_RD",
139	[0x0b] = "L2_WR",
140	[0x0c] = "L2_EVICT_MRU",
141	[0x0d] = "L2_SYNC",
142	[0x0e] = "L2_REFL_ERR",
143	[0x0f] = "0x0f",
144	[0x10] = "L2_INDX_WB_INV",
145	[0x11] = "L2_INDX_LD_TAG",
146	[0x12] = "L2_INDX_ST_TAG",
147	[0x13] = "L2_INDX_ST_DATA",
148	[0x14] = "L2_INDX_ST_ECC",
149	[0x15] = "0x15",
150	[0x16] = "0x16",
151	[0x17] = "0x17",
152	[0x18] = "L2_FTCH_AND_LCK",
153	[0x19] = "L2_HIT_INV",
154	[0x1a] = "L2_HIT_WB_INV",
155	[0x1b] = "L2_HIT_WB",
156	[0x1c] = "0x1c",
157	[0x1d] = "0x1d",
158	[0x1e] = "0x1e",
159	[0x1f] = "0x1f"
160};
161
162static char *cm2_causes[32] = {
163	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
164	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
165	"0x08", "0x09", "0x0a", "0x0b",
166	"0x0c", "0x0d", "0x0e", "0x0f",
167	"0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
168	"0x14", "0x15", "0x16", "0x17",
169	"L2_RD_UNCORR", "L2_WR_UNCORR", "L2_CORR", "0x1b",
170	"0x1c", "0x1d", "0x1e", "0x1f"
171};
172
173static char *cm3_causes[32] = {
174	"0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
175	"MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
176	"CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
177	"0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
178	"0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
179	"0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
180};
181
182static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
183static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
184
185phys_addr_t __weak mips_cm_phys_base(void)
186{
187	unsigned long cmgcr;
188
189	/* Check the CMGCRBase register is implemented */
190	if (!(read_c0_config() & MIPS_CONF_M))
191		return 0;
192
193	if (!(read_c0_config2() & MIPS_CONF_M))
194		return 0;
195
196	if (!(read_c0_config3() & MIPS_CONF3_CMGCR))
197		return 0;
198
199	/* Read the address from CMGCRBase */
200	cmgcr = read_c0_cmgcrbase();
201	return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
202}
203
204phys_addr_t __weak mips_cm_l2sync_phys_base(void)
205{
206	u32 base_reg;
207
208	/*
209	 * If the L2-only sync region is already enabled then leave it at it's
210	 * current location.
211	 */
212	base_reg = read_gcr_l2_only_sync_base();
213	if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
214		return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
215
216	/* Default to following the CM */
217	return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
218}
219
220static void mips_cm_probe_l2sync(void)
221{
222	unsigned major_rev;
223	phys_addr_t addr;
224
225	/* L2-only sync was introduced with CM major revision 6 */
226	major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev());
227	if (major_rev < 6)
228		return;
229
230	/* Find a location for the L2 sync region */
231	addr = mips_cm_l2sync_phys_base();
232	BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE) != addr);
233	if (!addr)
234		return;
235
236	/* Set the region base address & enable it */
237	write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
238
239	/* Map the region */
240	mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE);
241}
242
243void mips_cm_update_property(void)
244{
245	struct device_node *cm_node;
246
247	cm_node = of_find_compatible_node(of_root, NULL, "mobileye,eyeq6-cm");
248	if (!cm_node)
249		return;
250	pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken");
251	mips_cm_is_l2_hci_broken = true;
252
253	/* Disable MMID only if it was configured */
254	if (cpu_has_mmid)
255		cpu_disable_mmid();
256
257	of_node_put(cm_node);
258}
259
260int mips_cm_probe(void)
261{
262	phys_addr_t addr;
263	u32 base_reg;
264	unsigned cpu;
265
266	/*
267	 * No need to probe again if we have already been
268	 * here before.
269	 */
270	if (mips_gcr_base)
271		return 0;
272
273	addr = mips_cm_phys_base();
274	BUG_ON((addr & CM_GCR_BASE_GCRBASE) != addr);
275	if (!addr)
276		return -ENODEV;
277
278	mips_gcr_base = ioremap(addr, MIPS_CM_GCR_SIZE);
279	if (!mips_gcr_base)
280		return -ENXIO;
281
282	/* sanity check that we're looking at a CM */
283	base_reg = read_gcr_base();
284	if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
285		pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
286		       (unsigned long)addr);
287		iounmap(mips_gcr_base);
288		mips_gcr_base = NULL;
289		return -ENODEV;
290	}
291
292	/* set default target to memory */
293	change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
294
295	/* disable CM regions */
296	write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);
297	write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK);
298	write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR);
299	write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK);
300	write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR);
301	write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK);
302	write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR);
303	write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK);
304
305	/* probe for an L2-only sync region */
306	mips_cm_probe_l2sync();
307
308	/* determine register width for this CM */
309	mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
310
311	for_each_possible_cpu(cpu)
312		spin_lock_init(&per_cpu(cm_core_lock, cpu));
313
314	return 0;
315}
316
317void mips_cm_lock_other(unsigned int cluster, unsigned int core,
318			unsigned int vp, unsigned int block)
319{
320	unsigned int curr_core, cm_rev;
321	u32 val;
322
323	cm_rev = mips_cm_revision();
324	preempt_disable();
325
326	if (cm_rev >= CM_REV_CM3) {
327		val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) |
328		      FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
329
330		if (cm_rev >= CM_REV_CM3_5) {
331			if (cluster != cpu_cluster(&current_cpu_data))
332				val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
333			val |= CM_GCR_Cx_OTHER_GIC_EN;
334			val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
335			val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
336		} else {
337			WARN_ON(cluster != 0);
338			WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
339		}
340
341		/*
342		 * We need to disable interrupts in SMP systems in order to
343		 * ensure that we don't interrupt the caller with code which
344		 * may modify the redirect register. We do so here in a
345		 * slightly obscure way by using a spin lock, since this has
346		 * the neat property of also catching any nested uses of
347		 * mips_cm_lock_other() leading to a deadlock or a nice warning
348		 * with lockdep enabled.
349		 */
350		spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
351				  *this_cpu_ptr(&cm_core_lock_flags));
352	} else {
353		WARN_ON(cluster != 0);
354		WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
355
356		/*
357		 * We only have a GCR_CL_OTHER per core in systems with
358		 * CM 2.5 & older, so have to ensure other VP(E)s don't
359		 * race with us.
360		 */
361		curr_core = cpu_core(&current_cpu_data);
362		spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
363				  per_cpu(cm_core_lock_flags, curr_core));
364
365		val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
366	}
367
368	write_gcr_cl_other(val);
369
370	/*
371	 * Ensure the core-other region reflects the appropriate core &
372	 * VP before any accesses to it occur.
373	 */
374	mb();
375}
376
377void mips_cm_unlock_other(void)
378{
379	unsigned int curr_core;
380
381	if (mips_cm_revision() < CM_REV_CM3) {
382		curr_core = cpu_core(&current_cpu_data);
383		spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
384				       per_cpu(cm_core_lock_flags, curr_core));
385	} else {
386		spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
387				       *this_cpu_ptr(&cm_core_lock_flags));
388	}
389
390	preempt_enable();
391}
392
393void mips_cm_error_report(void)
394{
395	u64 cm_error, cm_addr, cm_other;
396	unsigned long revision;
397	int ocause, cause;
398	char buf[256];
399
400	if (!mips_cm_present())
401		return;
402
403	revision = mips_cm_revision();
404	cm_error = read_gcr_error_cause();
405	cm_addr = read_gcr_error_addr();
406	cm_other = read_gcr_error_mult();
407
408	if (revision < CM_REV_CM3) { /* CM2 */
409		cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
410		ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
411
412		if (!cause)
413			return;
414
415		if (cause < 16) {
416			unsigned long cca_bits = (cm_error >> 15) & 7;
417			unsigned long tr_bits = (cm_error >> 12) & 7;
418			unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
419			unsigned long stag_bits = (cm_error >> 3) & 15;
420			unsigned long sport_bits = (cm_error >> 0) & 7;
421
422			snprintf(buf, sizeof(buf),
423				 "CCA=%lu TR=%s MCmd=%s STag=%lu "
424				 "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
425				 cm2_cmd[cmd_bits], stag_bits, sport_bits);
426		} else if (cause < 24) {
427			/* glob state & sresp together */
428			unsigned long c3_bits = (cm_error >> 18) & 7;
429			unsigned long c2_bits = (cm_error >> 15) & 7;
430			unsigned long c1_bits = (cm_error >> 12) & 7;
431			unsigned long c0_bits = (cm_error >> 9) & 7;
432			unsigned long sc_bit = (cm_error >> 8) & 1;
433			unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
434			unsigned long sport_bits = (cm_error >> 0) & 7;
435
436			snprintf(buf, sizeof(buf),
437				 "C3=%s C2=%s C1=%s C0=%s SC=%s "
438				 "MCmd=%s SPort=%lu\n",
439				 cm2_core[c3_bits], cm2_core[c2_bits],
440				 cm2_core[c1_bits], cm2_core[c0_bits],
441				 sc_bit ? "True" : "False",
442				 cm2_cmd[cmd_bits], sport_bits);
443		} else {
444			unsigned long muc_bit = (cm_error >> 23) & 1;
445			unsigned long ins_bits = (cm_error >> 18) & 0x1f;
446			unsigned long arr_bits = (cm_error >> 16) & 3;
447			unsigned long dw_bits = (cm_error >> 12) & 15;
448			unsigned long way_bits = (cm_error >> 9) & 7;
449			unsigned long mway_bit = (cm_error >> 8) & 1;
450			unsigned long syn_bits = (cm_error >> 0) & 0xFF;
451
452			snprintf(buf, sizeof(buf),
453				 "Type=%s%s Instr=%s DW=%lu Way=%lu "
454				 "MWay=%s Syndrome=0x%02lx",
455				 muc_bit ? "Multi-UC " : "",
456				 cm2_l2_type[arr_bits],
457				 cm2_l2_instr[ins_bits], dw_bits, way_bits,
458				 mway_bit ? "True" : "False", syn_bits);
459		}
460		pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
461		       cm2_causes[cause], buf);
462		pr_err("CM_ADDR =%08llx\n", cm_addr);
463		pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
464	} else { /* CM3 */
465		ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
466		ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
467
468		cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
469		ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
470
471		if (!cause)
472			return;
473
474		/* Used by cause == {1,2,3} */
475		core_id_bits = (cm_error >> 22) & 0xf;
476		vp_id_bits = (cm_error >> 18) & 0xf;
477		cmd_bits = (cm_error >> 14) & 0xf;
478		cmd_group_bits = (cm_error >> 11) & 0xf;
479		cm3_cca_bits = (cm_error >> 8) & 7;
480		mcp_bits = (cm_error >> 5) & 0xf;
481		cm3_tr_bits = (cm_error >> 1) & 0xf;
482		sched_bit = cm_error & 0x1;
483
484		if (cause == 1 || cause == 3) { /* Tag ECC */
485			unsigned long tag_ecc = (cm_error >> 57) & 0x1;
486			unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
487			unsigned long dword_bits = (cm_error >> 49) & 0xff;
488			unsigned long data_way_bits = (cm_error >> 45) & 0xf;
489			unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
490			unsigned long bank_bit = (cm_error >> 28) & 0x1;
491			snprintf(buf, sizeof(buf),
492				 "%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
493				 "Bank=%lu CoreID=%lu VPID=%lu Command=%s"
494				 "Command Group=%s CCA=%lu MCP=%d"
495				 "Transaction type=%s Scheduler=%lu\n",
496				 tag_ecc ? "TAG" : "DATA",
497				 tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
498				 data_way_bits, bank_bit, dword_bits,
499				 data_sets_bits,
500				 core_id_bits, vp_id_bits,
501				 cm3_cmd[cmd_bits],
502				 cm3_cmd_group[cmd_group_bits],
503				 cm3_cca_bits, 1 << mcp_bits,
504				 cm3_tr[cm3_tr_bits], sched_bit);
505		} else if (cause == 2) {
506			unsigned long data_error_type = (cm_error >> 41) & 0xfff;
507			unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
508			unsigned long data_decode_group = (cm_error >> 34) & 0x7;
509			unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
510
511			snprintf(buf, sizeof(buf),
512				 "Decode Request Error: Type=%lu, Command=%lu"
513				 "Command Group=%lu Destination ID=%lu"
514				 "CoreID=%lu VPID=%lu Command=%s"
515				 "Command Group=%s CCA=%lu MCP=%d"
516				 "Transaction type=%s Scheduler=%lu\n",
517				 data_error_type, data_decode_cmd,
518				 data_decode_group, data_decode_destination_id,
519				 core_id_bits, vp_id_bits,
520				 cm3_cmd[cmd_bits],
521				 cm3_cmd_group[cmd_group_bits],
522				 cm3_cca_bits, 1 << mcp_bits,
523				 cm3_tr[cm3_tr_bits], sched_bit);
524		} else {
525			buf[0] = 0;
526		}
527
528		pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
529		       cm3_causes[cause], buf);
530		pr_err("CM_ADDR =%llx\n", cm_addr);
531		pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
532	}
533
534	/* reprime cause register */
535	write_gcr_error_cause(cm_error);
536}
537
538unsigned int mips_cps_first_online_in_cluster(int *first_cpu)
539{
540	unsigned int local_cl = cpu_cluster(&current_cpu_data);
541	struct cpumask *local_cl_mask;
542
543	/*
544	 * mips_cps_cluster_bootcfg is allocated in cps_prepare_cpus. If it is
545	 * not yet done, then we are so early that only one CPU is running, so
546	 * it is the first online CPU in the cluster.
547	 */
548	if  (IS_ENABLED(CONFIG_MIPS_CPS) && mips_cps_cluster_bootcfg)
549		local_cl_mask = &mips_cps_cluster_bootcfg[local_cl].cpumask;
550	else
551		return true;
552
553	*first_cpu = cpumask_any_and_but(local_cl_mask,
554					 cpu_online_mask,
555					 smp_processor_id());
556	return (*first_cpu >= nr_cpu_ids);
557}