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head.S

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linux-6.19.14/arch/mips/kernel/head.S S
  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 1994, 1995 Waldorf Electronics
  7 * Written by Ralf Baechle and Andreas Busse
  8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
  9 * Copyright (C) 1996 Paul M. Antoine
 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
 11 * Further modifications by David S. Miller and Harald Koerfgen
 12 * Copyright (C) 1999 Silicon Graphics, Inc.
 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 14 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 15 */
 16#include <linux/init.h>
 17#include <linux/threads.h>
 18
 19#include <asm/addrspace.h>
 20#include <asm/asm.h>
 21#include <asm/asmmacro.h>
 22#include <asm/irqflags.h>
 23#include <asm/regdef.h>
 24#include <asm/mipsregs.h>
 25#include <asm/stackframe.h>
 26
 27#include <kernel-entry-init.h>
 28
 29	/*
 30	 * For the moment disable interrupts, mark the kernel mode and
 31	 * set ST0_KX so that the CPU does not spit fire when using
 32	 * 64-bit addresses.  A full initialization of the CPU's status
 33	 * register is done later in per_cpu_trap_init().
 34	 */
 35	.macro	setup_c0_status set clr
 36	.set	push
 37	mfc0	t0, CP0_STATUS
 38	or	t0, ST0_KERNEL_CUMASK|\set|0x1f|\clr
 39	xor	t0, 0x1f|\clr
 40	mtc0	t0, CP0_STATUS
 41	.set	noreorder
 42	sll	zero,3				# ehb
 43	.set	pop
 44	.endm
 45
 46	.macro	setup_c0_status_pri
 47#ifdef CONFIG_64BIT
 48	setup_c0_status ST0_KX 0
 49#else
 50	setup_c0_status 0 0
 51#endif
 52	.endm
 53
 54	.macro	setup_c0_status_sec
 55#ifdef CONFIG_64BIT
 56	setup_c0_status ST0_KX ST0_BEV
 57#else
 58	setup_c0_status 0 ST0_BEV
 59#endif
 60	.endm
 61
 62	__HEAD
 63
 64#ifndef CONFIG_NO_EXCEPT_FILL
 65	/*
 66	 * Reserved space for exception handlers.
 67	 * Necessary for machines which link their kernels at KSEG0.
 68	 */
 69	.fill	0x400
 70#endif
 71
 72EXPORT(_stext)
 73
 74#ifdef CONFIG_BOOT_RAW
 75	/*
 76	 * Give us a fighting chance of running if execution beings at the
 77	 * kernel load address.	 This is needed because this platform does
 78	 * not have a ELF loader yet.
 79	 */
 80FEXPORT(__kernel_entry)
 81	j	kernel_entry
 82#endif /* CONFIG_BOOT_RAW */
 83
 84	__REF
 85
 86NESTED(kernel_entry, 16, sp)			# kernel entry point
 87
 88	kernel_entry_setup			# cpu specific setup
 89
 90	setup_c0_status_pri
 91
 92	/* We might not get launched at the address the kernel is linked to,
 93	   so we jump there.  */
 94	PTR_LA	t0, 0f
 95	jr	t0
 960:
 97
 98	PTR_LA		t0, __bss_start		# clear .bss
 99	LONG_S		zero, (t0)
100	PTR_LA		t1, __bss_stop - LONGSIZE
1011:
102	PTR_ADDIU	t0, LONGSIZE
103	LONG_S		zero, (t0)
104	bne		t0, t1, 1b
105
106	LONG_S		a0, fw_arg0		# firmware arguments
107	LONG_S		a1, fw_arg1
108	LONG_S		a2, fw_arg2
109	LONG_S		a3, fw_arg3
110
111	MTC0		zero, CP0_CONTEXT	# clear context register
112#ifdef CONFIG_64BIT
113	MTC0		zero, CP0_XCONTEXT
114#endif
115	PTR_LA		$28, init_thread_union
116	/* Set the SP after an empty pt_regs.  */
117	PTR_LI		sp, _THREAD_SIZE - 32 - PT_SIZE
118	PTR_ADDU	sp, $28
119	back_to_back_c0_hazard
120	set_saved_sp	sp, t0, t1
121	PTR_SUBU	sp, 4 * SZREG		# init stack pointer
122
123#ifdef CONFIG_RELOCATABLE
124	/* Copy kernel and apply the relocations */
125	jal		relocate_kernel
126
127	/* Repoint the sp into the new kernel image */
128	PTR_LI		sp, _THREAD_SIZE - 32 - PT_SIZE
129	PTR_ADDU	sp, $28
130	set_saved_sp	sp, t0, t1
131	PTR_SUBU	sp, 4 * SZREG		# init stack pointer
132
133	/*
134	 * relocate_kernel returns the entry point either
135	 * in the relocated kernel or the original if for
136	 * some reason relocation failed - jump there now
137	 * with instruction hazard barrier because of the
138	 * newly sync'd icache.
139	 */
140	jr.hb		v0
141#else  /* !CONFIG_RELOCATABLE */
142	j		start_kernel
143#endif /* !CONFIG_RELOCATABLE */
144	END(kernel_entry)
145
146#ifdef CONFIG_SMP
147/*
148 * SMP slave cpus entry point.	Board specific code for bootstrap calls this
149 * function after setting up the stack and gp registers.
150 */
151NESTED(smp_bootstrap, 16, sp)
152	smp_slave_setup
153	setup_c0_status_sec
154	j	start_secondary
155	END(smp_bootstrap)
156#endif /* CONFIG_SMP */
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