io.h

  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 1994, 1995 Waldorf GmbH
  7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
  8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  9 * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
 10 *	Author: Maciej W. Rozycki <macro@mips.com>
 11 */
 12#ifndef _ASM_IO_H
 13#define _ASM_IO_H
 14
 15#include <linux/compiler.h>
 16#include <linux/types.h>
 17#include <linux/irqflags.h>
 18
 19#include <asm/addrspace.h>
 20#include <asm/barrier.h>
 21#include <asm/bug.h>
 22#include <asm/byteorder.h>
 23#include <asm/cpu.h>
 24#include <asm/cpu-features.h>
 25#include <asm/page.h>
 26#include <asm/pgtable-bits.h>
 27#include <asm/string.h>
 28#include <mangle-port.h>
 29
 30/*
 31 * Raw operations are never swapped in software.  OTOH values that raw
 32 * operations are working on may or may not have been swapped by the bus
 33 * hardware.  An example use would be for flash memory that's used for
 34 * execute in place.
 35 */
 36# define __raw_ioswabb(a, x)	(x)
 37# define __raw_ioswabw(a, x)	(x)
 38# define __raw_ioswabl(a, x)	(x)
 39# define __raw_ioswabq(a, x)	(x)
 40# define ____raw_ioswabq(a, x)	(x)
 41
 42# define _ioswabb ioswabb
 43# define _ioswabw ioswabw
 44# define _ioswabl ioswabl
 45# define _ioswabq ioswabq
 46
 47# define __relaxed_ioswabb ioswabb
 48# define __relaxed_ioswabw ioswabw
 49# define __relaxed_ioswabl ioswabl
 50# define __relaxed_ioswabq ioswabq
 51
 52/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
 53
 54/*
 55 * On MIPS I/O ports are memory mapped, so we access them using normal
 56 * load/store instructions. mips_io_port_base is the virtual address to
 57 * which all ports are being mapped.  For sake of efficiency some code
 58 * assumes that this is an address that can be loaded with a single lui
 59 * instruction, so the lower 16 bits must be zero.  Should be true on
 60 * any sane architecture; generic code does not use this assumption.
 61 */
 62extern unsigned long mips_io_port_base;
 63
 64static inline void set_io_port_base(unsigned long base)
 65{
 66	mips_io_port_base = base;
 67}
 68
 69/*
 70 * Enforce in-order execution of data I/O.  In the MIPS architecture
 71 * these are equivalent to corresponding platform-specific memory
 72 * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
 73 * with sync additionally defined.
 74 */
 75#define iobarrier_rw() mb()
 76#define iobarrier_r() rmb()
 77#define iobarrier_w() wmb()
 78#define iobarrier_sync() iob()
 79
 80/*
 81 *     virt_to_phys    -       map virtual addresses to physical
 82 *     @address: address to remap
 83 *
 84 *     The returned physical address is the physical (CPU) mapping for
 85 *     the memory address given. It is only valid to use this function on
 86 *     addresses directly mapped or allocated via kmalloc.
 87 *
 88 *     This function does not give bus mappings for DMA transfers. In
 89 *     almost all conceivable cases a device driver should not be using
 90 *     this function
 91 */
 92static inline unsigned long __virt_to_phys_nodebug(volatile const void *address)
 93{
 94	return __pa(address);
 95}
 96
 97#ifdef CONFIG_DEBUG_VIRTUAL
 98extern phys_addr_t __virt_to_phys(volatile const void *x);
 99#else
100#define __virt_to_phys(x)	__virt_to_phys_nodebug(x)
101#endif
102
103#define virt_to_phys virt_to_phys
104static inline phys_addr_t virt_to_phys(const volatile void *x)
105{
106	return __virt_to_phys(x);
107}
108
109/*
110 * ISA I/O bus memory addresses are 1:1 with the physical address.
111 */
112static inline unsigned long isa_virt_to_bus(volatile void *address)
113{
114	return virt_to_phys(address);
115}
116
117void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
118			   pgprot_t prot);
119void iounmap(const volatile void __iomem *addr);
120
121/*
122 * ioremap     -   map bus memory into CPU space
123 * @offset:    bus address of the memory
124 * @size:      size of the resource to map
125 *
126 * ioremap performs a platform specific sequence of operations to
127 * make bus memory CPU accessible via the readb/readw/readl/writeb/
128 * writew/writel functions and the other mmio helpers. The returned
129 * address is not guaranteed to be usable directly as a virtual
130 * address.
131 */
132#define ioremap(offset, size)						\
133	ioremap_prot((offset), (size), __pgprot(_CACHE_UNCACHED))
134
135/*
136 * ioremap_cache -	map bus memory into CPU space
137 * @offset:	    bus address of the memory
138 * @size:	    size of the resource to map
139 *
140 * ioremap_cache performs a platform specific sequence of operations to
141 * make bus memory CPU accessible via the readb/readw/readl/writeb/
142 * writew/writel functions and the other mmio helpers. The returned
143 * address is not guaranteed to be usable directly as a virtual
144 * address.
145 *
146 * This version of ioremap ensures that the memory is marked cacheable by
147 * the CPU.  Also enables full write-combining.	 Useful for some
148 * memory-like regions on I/O busses.
149 */
150#define ioremap_cache(offset, size)					\
151	ioremap_prot((offset), (size), __pgprot(_page_cachable_default))
152
153/*
154 * ioremap_wc     -   map bus memory into CPU space
155 * @offset:    bus address of the memory
156 * @size:      size of the resource to map
157 *
158 * ioremap_wc performs a platform specific sequence of operations to
159 * make bus memory CPU accessible via the readb/readw/readl/writeb/
160 * writew/writel functions and the other mmio helpers. The returned
161 * address is not guaranteed to be usable directly as a virtual
162 * address.
163 *
164 * This version of ioremap ensures that the memory is marked uncacheable
165 * but accelerated by means of write-combining feature. It is specifically
166 * useful for PCIe prefetchable windows, which may vastly improve a
167 * communications performance. If it was determined on boot stage, what
168 * CPU CCA doesn't support UCA, the method shall fall-back to the
169 * _CACHE_UNCACHED option (see cpu_probe() method).
170 */
171#define ioremap_wc(offset, size)					\
172	ioremap_prot((offset), (size), __pgprot(boot_cpu_data.writecombine))
173
174#if defined(CONFIG_CPU_CAVIUM_OCTEON)
175#define war_io_reorder_wmb()		wmb()
176#else
177#define war_io_reorder_wmb()		barrier()
178#endif
179
180#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq)	\
181									\
182static inline void pfx##write##bwlq(type val,				\
183				    volatile void __iomem *mem)		\
184{									\
185	volatile type *__mem;						\
186	type __val;							\
187									\
188	if (barrier)							\
189		iobarrier_rw();						\
190	else								\
191		war_io_reorder_wmb();					\
192									\
193	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
194									\
195	__val = pfx##ioswab##bwlq(__mem, val);				\
196									\
197	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
198		*__mem = __val;						\
199	else if (cpu_has_64bits) {					\
200		unsigned long __flags;					\
201		type __tmp;						\
202									\
203		if (irq)						\
204			local_irq_save(__flags);			\
205		__asm__ __volatile__(					\
206			".set	push"		"\t\t# __writeq""\n\t"	\
207			".set	arch=r4000"			"\n\t"	\
208			"dsll32 %L0, %L0, 0"			"\n\t"	\
209			"dsrl32 %L0, %L0, 0"			"\n\t"	\
210			"dsll32 %M0, %M0, 0"			"\n\t"	\
211			"or	%L0, %L0, %M0"			"\n\t"	\
212			"sd	%L0, %2"			"\n\t"	\
213			".set	pop"				"\n"	\
214			: "=r" (__tmp)					\
215			: "0" (__val), "m" (*__mem));			\
216		if (irq)						\
217			local_irq_restore(__flags);			\
218	} else								\
219		BUG();							\
220}									\
221									\
222static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
223{									\
224	volatile type *__mem;						\
225	type __val;							\
226									\
227	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
228									\
229	if (barrier)							\
230		iobarrier_rw();						\
231									\
232	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
233		__val = *__mem;						\
234	else if (cpu_has_64bits) {					\
235		unsigned long __flags;					\
236									\
237		if (irq)						\
238			local_irq_save(__flags);			\
239		__asm__ __volatile__(					\
240			".set	push"		"\t\t# __readq" "\n\t"	\
241			".set	arch=r4000"			"\n\t"	\
242			"ld	%L0, %1"			"\n\t"	\
243			"dsra32 %M0, %L0, 0"			"\n\t"	\
244			"sll	%L0, %L0, 0"			"\n\t"	\
245			".set	pop"				"\n"	\
246			: "=r" (__val)					\
247			: "m" (*__mem));				\
248		if (irq)						\
249			local_irq_restore(__flags);			\
250	} else {							\
251		__val = 0;						\
252		BUG();							\
253	}								\
254									\
255	/* prevent prefetching of coherent DMA data prematurely */	\
256	if (!relax)							\
257		rmb();							\
258	return pfx##ioswab##bwlq(__mem, __val);				\
259}
260
261#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax)		\
262									\
263static inline void pfx##out##bwlq(type val, unsigned long port)		\
264{									\
265	volatile type *__addr;						\
266	type __val;							\
267									\
268	if (barrier)							\
269		iobarrier_rw();						\
270	else								\
271		war_io_reorder_wmb();					\
272									\
273	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
274									\
275	__val = pfx##ioswab##bwlq(__addr, val);				\
276									\
277	/* Really, we want this to be atomic */				\
278	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
279									\
280	*__addr = __val;						\
281}									\
282									\
283static inline type pfx##in##bwlq(unsigned long port)			\
284{									\
285	volatile type *__addr;						\
286	type __val;							\
287									\
288	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
289									\
290	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
291									\
292	if (barrier)							\
293		iobarrier_rw();						\
294									\
295	__val = *__addr;						\
296									\
297	/* prevent prefetching of coherent DMA data prematurely */	\
298	if (!relax)							\
299		rmb();							\
300	return pfx##ioswab##bwlq(__addr, __val);			\
301}
302
303#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax)			\
304									\
305__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
306
307#define BUILDIO_MEM(bwlq, type)						\
308									\
309__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0)				\
310__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1)				\
311__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0)				\
312__BUILD_MEMORY_PFX(, bwlq, type, 0)
313
314BUILDIO_MEM(b, u8)
315BUILDIO_MEM(w, u16)
316BUILDIO_MEM(l, u32)
317#ifdef CONFIG_64BIT
318BUILDIO_MEM(q, u64)
319#else
320__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
321__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
322#endif
323
324#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
325	__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0)
326
327#define BUILDIO_IOPORT(bwlq, type)					\
328	__BUILD_IOPORT_PFX(_, bwlq, type)				\
329	__BUILD_IOPORT_PFX(__mem_, bwlq, type)
330
331BUILDIO_IOPORT(b, u8)
332BUILDIO_IOPORT(w, u16)
333BUILDIO_IOPORT(l, u32)
334#ifdef CONFIG_64BIT
335BUILDIO_IOPORT(q, u64)
336#endif
337
338#define __BUILDIO(bwlq, type)						\
339									\
340__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
341
342__BUILDIO(q, u64)
343
344#define readb_relaxed			__relaxed_readb
345#define readw_relaxed			__relaxed_readw
346#define readl_relaxed			__relaxed_readl
347#ifdef CONFIG_64BIT
348#define readq_relaxed			__relaxed_readq
349#endif
350
351#define writeb_relaxed			__relaxed_writeb
352#define writew_relaxed			__relaxed_writew
353#define writel_relaxed			__relaxed_writel
354#ifdef CONFIG_64BIT
355#define writeq_relaxed			__relaxed_writeq
356#endif
357
358#define readb_be(addr)							\
359	__raw_readb((__force unsigned *)(addr))
360#define readw_be(addr)							\
361	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
362#define readl_be(addr)							\
363	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
364#define readq_be(addr)							\
365	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
366
367#define writeb_be(val, addr)						\
368	__raw_writeb((val), (__force unsigned *)(addr))
369#define writew_be(val, addr)						\
370	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
371#define writel_be(val, addr)						\
372	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
373#define writeq_be(val, addr)						\
374	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
375
376#define __BUILD_MEMORY_STRING(bwlq, type)				\
377									\
378static inline void writes##bwlq(volatile void __iomem *mem,		\
379				const void *addr, unsigned int count)	\
380{									\
381	const volatile type *__addr = addr;				\
382									\
383	while (count--) {						\
384		__mem_write##bwlq(*__addr, mem);			\
385		__addr++;						\
386	}								\
387}									\
388									\
389static inline void reads##bwlq(const volatile void __iomem *mem,	\
390			       void *addr, unsigned int count)		\
391{									\
392	volatile type *__addr = addr;					\
393									\
394	while (count--) {						\
395		*__addr = __mem_read##bwlq(mem);			\
396		__addr++;						\
397	}								\
398}
399
400#define __BUILD_IOPORT_STRING(bwlq, type)				\
401									\
402static inline void outs##bwlq(unsigned long port, const void *addr,	\
403			      unsigned int count)			\
404{									\
405	const volatile type *__addr = addr;				\
406									\
407	while (count--) {						\
408		__mem_out##bwlq(*__addr, port);				\
409		__addr++;						\
410	}								\
411}									\
412									\
413static inline void ins##bwlq(unsigned long port, void *addr,		\
414			     unsigned int count)			\
415{									\
416	volatile type *__addr = addr;					\
417									\
418	while (count--) {						\
419		*__addr = __mem_in##bwlq(port);				\
420		__addr++;						\
421	}								\
422}
423
424#define BUILDSTRING(bwlq, type)						\
425									\
426__BUILD_MEMORY_STRING(bwlq, type)					\
427__BUILD_IOPORT_STRING(bwlq, type)
428
429BUILDSTRING(b, u8)
430BUILDSTRING(w, u16)
431BUILDSTRING(l, u32)
432#ifdef CONFIG_64BIT
433BUILDSTRING(q, u64)
434#endif
435
436
437/*
438 * The caches on some architectures aren't dma-coherent and have need to
439 * handle this in software.  There are three types of operations that
440 * can be applied to dma buffers.
441 *
442 *  - dma_cache_wback_inv(start, size) makes caches and coherent by
443 *    writing the content of the caches back to memory, if necessary.
444 *    The function also invalidates the affected part of the caches as
445 *    necessary before DMA transfers from outside to memory.
446 *  - dma_cache_wback(start, size) makes caches and coherent by
447 *    writing the content of the caches back to memory, if necessary.
448 *    The function also invalidates the affected part of the caches as
449 *    necessary before DMA transfers from outside to memory.
450 *  - dma_cache_inv(start, size) invalidates the affected parts of the
451 *    caches.  Dirty lines of the caches may be written back or simply
452 *    be discarded.  This operation is necessary before dma operations
453 *    to the memory.
454 *
455 * This API used to be exported; it now is for arch code internal use only.
456 */
457#ifdef CONFIG_DMA_NONCOHERENT
458
459extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
460extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
461extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
462
463#define dma_cache_wback_inv(start, size)	_dma_cache_wback_inv(start, size)
464#define dma_cache_wback(start, size)		_dma_cache_wback(start, size)
465#define dma_cache_inv(start, size)		_dma_cache_inv(start, size)
466
467#else /* Sane hardware */
468
469#define dma_cache_wback_inv(start,size) \
470	do { (void) (start); (void) (size); } while (0)
471#define dma_cache_wback(start,size)	\
472	do { (void) (start); (void) (size); } while (0)
473#define dma_cache_inv(start,size)	\
474	do { (void) (start); (void) (size); } while (0)
475
476#endif /* CONFIG_DMA_NONCOHERENT */
477
478/*
479 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
480 * Avoid interrupt mucking, just adjust the address for 4-byte access.
481 * Assume the addresses are 8-byte aligned.
482 */
483#ifdef __MIPSEB__
484#define __CSR_32_ADJUST 4
485#else
486#define __CSR_32_ADJUST 0
487#endif
488
489#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
490#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
491
492#define __raw_readb __raw_readb
493#define __raw_readw __raw_readw
494#define __raw_readl __raw_readl
495#ifdef CONFIG_64BIT
496#define __raw_readq __raw_readq
497#endif
498#define __raw_writeb __raw_writeb
499#define __raw_writew __raw_writew
500#define __raw_writel __raw_writel
501#ifdef CONFIG_64BIT
502#define __raw_writeq __raw_writeq
503#endif
504
505#define readb readb
506#define readw readw
507#define readl readl
508#ifdef CONFIG_64BIT
509#define readq readq
510#endif
511#define writeb writeb
512#define writew writew
513#define writel writel
514#ifdef CONFIG_64BIT
515#define writeq writeq
516#endif
517
518#define readsb readsb
519#define readsw readsw
520#define readsl readsl
521#ifdef CONFIG_64BIT
522#define readsq readsq
523#endif
524#define writesb writesb
525#define writesw writesw
526#define writesl writesl
527#ifdef CONFIG_64BIT
528#define writesq writesq
529#endif
530
531#define _inb _inb
532#define _inw _inw
533#define _inl _inl
534#define insb insb
535#define insw insw
536#define insl insl
537
538#define _outb _outb
539#define _outw _outw
540#define _outl _outl
541#define outsb outsb
542#define outsw outsw
543#define outsl outsl
544
545void __ioread64_copy(void *to, const void __iomem *from, size_t count);
546
547#if defined(CONFIG_PCI) && defined(CONFIG_PCI_DRIVERS_LEGACY)
548struct pci_dev;
549void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
550#define pci_iounmap pci_iounmap
551#endif
552
553#ifndef PCI_IOBASE
554#define PCI_IOBASE ((void __iomem *)mips_io_port_base)
555#endif
556
557#include <asm-generic/io.h>
558
559static inline void *isa_bus_to_virt(unsigned long address)
560{
561	return phys_to_virt(address);
562}
563
564#endif /* _ASM_IO_H */