cpu-info.h

  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 1994 Waldorf GMBH
  7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
  8 * Copyright (C) 1996 Paul M. Antoine
  9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 10 * Copyright (C) 2004  Maciej W. Rozycki
 11 */
 12#ifndef __ASM_CPU_INFO_H
 13#define __ASM_CPU_INFO_H
 14
 15#include <linux/cache.h>
 16#include <linux/types.h>
 17
 18#include <asm/mipsregs.h>
 19
 20/*
 21 * Descriptor for a cache
 22 */
 23struct cache_desc {
 24	unsigned int waysize;	/* Bytes per way */
 25	unsigned short sets;	/* Number of lines per set */
 26	unsigned char ways;	/* Number of ways */
 27	unsigned char linesz;	/* Size of line in bytes */
 28	unsigned char waybit;	/* Bits to select in a cache set */
 29	unsigned char flags;	/* Flags describing cache properties */
 30};
 31
 32struct guest_info {
 33	unsigned long		ases;
 34	unsigned long		ases_dyn;
 35	unsigned long long	options;
 36	unsigned long long	options_dyn;
 37	int			tlbsize;
 38	u8			conf;
 39	u8			kscratch_mask;
 40};
 41
 42/*
 43 * Flag definitions
 44 */
 45#define MIPS_CACHE_NOT_PRESENT	0x00000001
 46#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
 47#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
 48#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
 49#define MIPS_IC_SNOOPS_REMOTE	0x00000010	/* Ic snoops remote stores */
 50#define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */
 51
 52struct cpuinfo_mips {
 53	u64			asid_cache;
 54#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
 55	unsigned long		asid_mask;
 56#endif
 57
 58	/*
 59	 * Capability and feature descriptor structure for MIPS CPU
 60	 */
 61	unsigned long		ases;
 62	unsigned long long	options;
 63	unsigned int		udelay_val;
 64	unsigned int		processor_id;
 65	unsigned int		fpu_id;
 66	unsigned int		fpu_csr31;
 67	unsigned int		fpu_msk31;
 68	unsigned int		msa_id;
 69	unsigned int		cputype;
 70	int			isa_level;
 71	int			tlbsize;
 72	int			tlbsizevtlb;
 73	int			tlbsizeftlbsets;
 74	int			tlbsizeftlbways;
 75	struct cache_desc	icache; /* Primary I-cache */
 76	struct cache_desc	dcache; /* Primary D or combined I/D cache */
 77	struct cache_desc	vcache; /* Victim cache, between pcache and scache */
 78	struct cache_desc	scache; /* Secondary cache */
 79	struct cache_desc	tcache; /* Tertiary/split secondary cache */
 80	int			srsets; /* Shadow register sets */
 81	int			package;/* physical package number */
 82	unsigned int		globalnumber;
 83	int			vmbits; /* Virtual memory size in bits */
 84	void			*data;	/* Additional data */
 85	unsigned int		watch_reg_count;   /* Number that exist */
 86	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */
 87#define NUM_WATCH_REGS 4
 88	u16			watch_reg_masks[NUM_WATCH_REGS];
 89	unsigned int		kscratch_mask; /* Usable KScratch mask. */
 90	/*
 91	 * Cache Coherency attribute for write-combine memory writes.
 92	 * (shifted by _CACHE_SHIFT)
 93	 */
 94	unsigned int		writecombine;
 95	/*
 96	 * Simple counter to prevent enabling HTW in nested
 97	 * htw_start/htw_stop calls
 98	 */
 99	unsigned int		htw_seq;
100
101	/* VZ & Guest features */
102	struct guest_info	guest;
103	unsigned int		gtoffset_mask;
104	unsigned int		guestid_mask;
105	unsigned int		guestid_cache;
106
107#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
108	/* CPUCFG data for this CPU, synthesized at probe time.
109	 *
110	 * CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
111	 * So the only stored values are for CPUCFG selects 1-3 inclusive.
112	 */
113	u32 loongson3_cpucfg_data[3];
114#endif
115} __attribute__((aligned(SMP_CACHE_BYTES)));
116
117extern struct cpuinfo_mips cpu_data[];
118#define current_cpu_data cpu_data[smp_processor_id()]
119#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
120#define boot_cpu_data cpu_data[0]
121
122extern void cpu_probe(void);
123extern void cpu_report(void);
124extern void cpu_disable_mmid(void);
125
126extern const char *__cpu_name[];
127#define cpu_name_string()	__cpu_name[raw_smp_processor_id()]
128
129struct seq_file;
130struct notifier_block;
131
132extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
133extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
134
135#define proc_cpuinfo_notifier(fn, pri)					\
136({									\
137	static struct notifier_block fn##_nb = {			\
138		.notifier_call = fn,					\
139		.priority = pri						\
140	};								\
141									\
142	register_proc_cpuinfo_notifier(&fn##_nb);			\
143})
144
145struct proc_cpuinfo_notifier_args {
146	struct seq_file *m;
147	unsigned long n;
148};
149
150static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
151{
152	/* Optimisation for systems where multiple clusters aren't used */
153	if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
154		return 0;
155
156	return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
157		MIPS_GLOBALNUMBER_CLUSTER_SHF;
158}
159
160static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
161{
162	return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
163		MIPS_GLOBALNUMBER_CORE_SHF;
164}
165
166static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
167{
168	/* Optimisation for systems where VP(E)s aren't used */
169	if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
170		return 0;
171
172	return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
173		MIPS_GLOBALNUMBER_VP_SHF;
174}
175
176extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
177extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
178extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
179
180static inline bool cpus_are_siblings(int cpua, int cpub)
181{
182	struct cpuinfo_mips *infoa = &cpu_data[cpua];
183	struct cpuinfo_mips *infob = &cpu_data[cpub];
184	unsigned int gnuma, gnumb;
185
186	if (infoa->package != infob->package)
187		return false;
188
189	gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
190	gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
191	if (gnuma != gnumb)
192		return false;
193
194	return true;
195}
196
197static inline unsigned long cpu_asid_inc(void)
198{
199	return 1 << CONFIG_MIPS_ASID_SHIFT;
200}
201
202static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
203{
204#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
205	return cpuinfo->asid_mask;
206#endif
207	return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
208}
209
210static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
211				     unsigned long asid_mask)
212{
213#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
214	cpuinfo->asid_mask = asid_mask;
215#endif
216}
217
218#endif /* __ASM_CPU_INFO_H */