cvmx-helper-xaui.c

  1/***********************license start***************
  2 * Author: Cavium Networks
  3 *
  4 * Contact: support@caviumnetworks.com
  5 * This file is part of the OCTEON SDK
  6 *
  7 * Copyright (C) 2003-2018 Cavium, Inc.
  8 *
  9 * This file is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License, Version 2, as
 11 * published by the Free Software Foundation.
 12 *
 13 * This file is distributed in the hope that it will be useful, but
 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16 * NONINFRINGEMENT.  See the GNU General Public License for more
 17 * details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this file; if not, write to the Free Software
 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 22 * or visit http://www.gnu.org/licenses/.
 23 *
 24 * This file may also be available under a different license from Cavium.
 25 * Contact Cavium Networks for more information
 26 ***********************license end**************************************/
 27
 28/*
 29 * Functions for XAUI initialization, configuration,
 30 * and monitoring.
 31 *
 32 */
 33
 34#include <asm/octeon/octeon.h>
 35
 36#include <asm/octeon/cvmx-config.h>
 37
 38#include <asm/octeon/cvmx-helper.h>
 39
 40#include <asm/octeon/cvmx-pko-defs.h>
 41#include <asm/octeon/cvmx-gmxx-defs.h>
 42#include <asm/octeon/cvmx-pcsx-defs.h>
 43#include <asm/octeon/cvmx-pcsxx-defs.h>
 44
 45int __cvmx_helper_xaui_enumerate(int interface)
 46{
 47	union cvmx_gmxx_hg2_control gmx_hg2_control;
 48
 49	/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
 50	gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
 51	if (gmx_hg2_control.s.hg2tx_en)
 52		return 16;
 53	else
 54		return 1;
 55}
 56
 57/*
 58 * Probe a XAUI interface and determine the number of ports
 59 * connected to it. The XAUI interface should still be down
 60 * after this call.
 61 *
 62 * @interface: Interface to probe
 63 *
 64 * Returns Number of ports on the interface. Zero to disable.
 65 */
 66int __cvmx_helper_xaui_probe(int interface)
 67{
 68	int i;
 69	union cvmx_gmxx_inf_mode mode;
 70
 71	/*
 72	 * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
 73	 * interface needs to be enabled before IPD otherwise per port
 74	 * backpressure may not work properly.
 75	 */
 76	mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 77	mode.s.en = 1;
 78	cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
 79
 80	__cvmx_helper_setup_gmx(interface, 1);
 81
 82	/*
 83	 * Setup PKO to support 16 ports for HiGig2 virtual
 84	 * ports. We're pointing all of the PKO packet ports for this
 85	 * interface to the XAUI. This allows us to use HiGig2
 86	 * backpressure per port.
 87	 */
 88	for (i = 0; i < 16; i++) {
 89		union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
 90		pko_mem_port_ptrs.u64 = 0;
 91		/*
 92		 * We set each PKO port to have equal priority in a
 93		 * round robin fashion.
 94		 */
 95		pko_mem_port_ptrs.s.static_p = 0;
 96		pko_mem_port_ptrs.s.qos_mask = 0xff;
 97		/* All PKO ports map to the same XAUI hardware port */
 98		pko_mem_port_ptrs.s.eid = interface * 4;
 99		pko_mem_port_ptrs.s.pid = interface * 16 + i;
100		cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
101	}
102	return __cvmx_helper_xaui_enumerate(interface);
103}
104
105/*
106 * Bringup and enable a XAUI interface. After this call packet
107 * I/O should be fully functional. This is called with IPD
108 * enabled but PKO disabled.
109 *
110 * @interface: Interface to bring up
111 *
112 * Returns Zero on success, negative on failure
113 */
114int __cvmx_helper_xaui_enable(int interface)
115{
116	union cvmx_gmxx_prtx_cfg gmx_cfg;
117	union cvmx_pcsxx_control1_reg xauiCtl;
118	union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
119	union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
120	union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
121	union cvmx_gmxx_tx_int_en gmx_tx_int_en;
122	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
123
124	/* Setup PKND */
125	if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
126		gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
127		gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
128		cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
129	}
130
131	/* (1) Interface has already been enabled. */
132
133	/* (2) Disable GMX. */
134	xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
135	xauiMiscCtl.s.gmxeno = 1;
136	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
137
138	/* (3) Disable GMX and PCSX interrupts. */
139	gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
140	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
141	gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
142	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
143	pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
144	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
145
146	/* (4) Bring up the PCSX and GMX reconciliation layer. */
147	/* (4)a Set polarity and lane swapping. */
148	/* (4)b */
149	gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
150	/* Enable better IFG packing and improves performance */
151	gmxXauiTxCtl.s.dic_en = 1;
152	gmxXauiTxCtl.s.uni_en = 0;
153	cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
154
155	/* (4)c Aply reset sequence */
156	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
157	xauiCtl.s.lo_pwr = 0;
158
159	/* Issuing a reset here seems to hang some CN66XX/CN68XX chips. */
160	if (!OCTEON_IS_MODEL(OCTEON_CN66XX) &&
161	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
162	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
163		xauiCtl.s.reset = 1;
164
165	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
166
167	/* Wait for PCS to come out of reset */
168	if (CVMX_WAIT_FOR_FIELD64
169	    (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
170	     reset, ==, 0, 10000))
171		return -1;
172	/* Wait for PCS to be aligned */
173	if (CVMX_WAIT_FOR_FIELD64
174	    (CVMX_PCSXX_10GBX_STATUS_REG(interface),
175	     union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
176		return -1;
177	/* Wait for RX to be ready */
178	if (CVMX_WAIT_FOR_FIELD64
179	    (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
180		    status, ==, 0, 10000))
181		return -1;
182
183	/* (6) Configure GMX */
184	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
185	gmx_cfg.s.en = 0;
186	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
187
188	/* Wait for GMX RX to be idle */
189	if (CVMX_WAIT_FOR_FIELD64
190	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
191		    rx_idle, ==, 1, 10000))
192		return -1;
193	/* Wait for GMX TX to be idle */
194	if (CVMX_WAIT_FOR_FIELD64
195	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
196		    tx_idle, ==, 1, 10000))
197		return -1;
198
199	/* GMX configure */
200	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
201	gmx_cfg.s.speed = 1;
202	gmx_cfg.s.speed_msb = 0;
203	gmx_cfg.s.slottime = 1;
204	cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
205	cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
206	cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
207	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
208
209	/* (7) Clear out any error state */
210	cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
211		       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
212	cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
213		       cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
214	cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
215		       cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
216
217	/* Wait for receive link */
218	if (CVMX_WAIT_FOR_FIELD64
219	    (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
220	     rcv_lnk, ==, 1, 10000))
221		return -1;
222	if (CVMX_WAIT_FOR_FIELD64
223	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
224	     xmtflt, ==, 0, 10000))
225		return -1;
226	if (CVMX_WAIT_FOR_FIELD64
227	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
228	     rcvflt, ==, 0, 10000))
229		return -1;
230
231	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
232	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
233	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
234
235	/* (8) Enable packet reception */
236	xauiMiscCtl.s.gmxeno = 0;
237	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
238
239	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
240	gmx_cfg.s.en = 1;
241	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
242
243	__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
244	__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
245	__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
246	__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
247	__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
248	__cvmx_interrupt_gmxx_enable(interface);
249
250	return 0;
251}
252
253/*
254 * Return the link state of an IPD/PKO port as returned by
255 * auto negotiation. The result of this function may not match
256 * Octeon's link config if auto negotiation has changed since
257 * the last call to cvmx_helper_link_set().
258 *
259 * @ipd_port: IPD/PKO port to query
260 *
261 * Returns Link state
262 */
263union cvmx_helper_link_info __cvmx_helper_xaui_link_get(int ipd_port)
264{
265	int interface = cvmx_helper_get_interface_num(ipd_port);
266	union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
267	union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
268	union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
269	union cvmx_helper_link_info result;
270
271	gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
272	gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
273	pcsxx_status1_reg.u64 =
274	    cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
275	result.u64 = 0;
276
277	/* Only return a link if both RX and TX are happy */
278	if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
279	    (pcsxx_status1_reg.s.rcv_lnk == 1)) {
280		result.s.link_up = 1;
281		result.s.full_duplex = 1;
282		result.s.speed = 10000;
283	} else {
284		/* Disable GMX and PCSX interrupts. */
285		cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
286		cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
287		cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
288	}
289	return result;
290}
291
292/*
293 * Configure an IPD/PKO port for the specified link state. This
294 * function does not influence auto negotiation at the PHY level.
295 * The passed link state must always match the link state returned
296 * by cvmx_helper_link_get().
297 *
298 * @ipd_port:  IPD/PKO port to configure
299 * @link_info: The new link state
300 *
301 * Returns Zero on success, negative on failure
302 */
303int __cvmx_helper_xaui_link_set(int ipd_port, union cvmx_helper_link_info link_info)
304{
305	int interface = cvmx_helper_get_interface_num(ipd_port);
306	union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
307	union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
308
309	gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
310	gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
311
312	/* If the link shouldn't be up, then just return */
313	if (!link_info.s.link_up)
314		return 0;
315
316	/* Do nothing if both RX and TX are happy */
317	if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
318		return 0;
319
320	/* Bring the link up */
321	return __cvmx_helper_xaui_enable(interface);
322}