rtl838x.dtsi

  1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
  2
  3/ {
  4	#address-cells = <1>;
  5	#size-cells = <1>;
  6
  7	aliases {
  8		serial0 = &uart0;
  9		serial1 = &uart1;
 10	};
 11
 12	cpus {
 13		#address-cells = <1>;
 14		#size-cells = <0>;
 15
 16		cpu@0 {
 17			device_type = "cpu";
 18			compatible = "mips,mips4KEc";
 19			reg = <0>;
 20			clocks = <&baseclk>;
 21		};
 22	};
 23
 24	baseclk: baseclk {
 25		compatible = "fixed-clock";
 26		#clock-cells = <0>;
 27		clock-frequency = <500000000>;
 28	};
 29
 30	cpuintc: cpuintc {
 31		compatible = "mti,cpu-interrupt-controller";
 32		#address-cells = <0>;
 33		#interrupt-cells = <1>;
 34		interrupt-controller;
 35	};
 36
 37	lx_clk: clock-lexra {
 38		compatible = "fixed-clock";
 39		#clock-cells = <0>;
 40		clock-frequency = <200000000>;
 41	};
 42
 43	soc@18000000 {
 44		compatible = "simple-bus";
 45		#address-cells = <1>;
 46		#size-cells = <1>;
 47		ranges = <0x0 0x18000000 0x10000>;
 48
 49		spi0: spi@1200 {
 50			compatible = "realtek,rtl8380-spi";
 51			reg = <0x1200 0x100>;
 52
 53			#address-cells = <1>;
 54			#size-cells = <0>;
 55		};
 56
 57		uart0: serial@2000 {
 58			compatible = "ns16550a";
 59			reg = <0x2000 0x100>;
 60
 61			clocks = <&lx_clk>;
 62
 63			interrupt-parent = <&intc>;
 64			interrupts = <31>;
 65
 66			reg-io-width = <1>;
 67			reg-shift = <2>;
 68			fifo-size = <1>;
 69			no-loopback-test;
 70
 71			status = "disabled";
 72		};
 73
 74		uart1: serial@2100 {
 75			compatible = "ns16550a";
 76			reg = <0x2100 0x100>;
 77
 78			clocks = <&lx_clk>;
 79
 80			interrupt-parent = <&intc>;
 81			interrupts = <30>;
 82
 83			reg-io-width = <1>;
 84			reg-shift = <2>;
 85			fifo-size = <1>;
 86			no-loopback-test;
 87
 88			status = "disabled";
 89		};
 90
 91		intc: interrupt-controller@3000 {
 92			compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
 93			reg = <0x3000 0x20>;
 94			interrupt-controller;
 95			#interrupt-cells = <1>;
 96
 97			interrupt-parent = <&cpuintc>;
 98			interrupts = <2>, <3>, <4>, <5>, <6>;
 99		};
100
101		watchdog: watchdog@3150 {
102			compatible = "realtek,rtl8380-wdt";
103			reg = <0x3150 0xc>;
104
105			realtek,reset-mode = "soc";
106
107			clocks = <&lx_clk>;
108			timeout-sec = <20>;
109
110			interrupt-parent = <&intc>;
111			interrupt-names = "phase1", "phase2";
112			interrupts = <19>, <18>;
113		};
114
115		gpio0: gpio@3500 {
116			compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
117			reg = <0x3500 0x1c>;
118
119			gpio-controller;
120			#gpio-cells = <2>;
121			ngpios = <24>;
122
123			interrupt-controller;
124			#interrupt-cells = <2>;
125			interrupt-parent = <&intc>;
126			interrupts = <23>;
127		};
128	};
129};