eyeq6h.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2/*
  3 * Copyright 2024 Mobileye Vision Technologies Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/mips-gic.h>
  7
  8#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
  9
 10/ {
 11	#address-cells = <2>;
 12	#size-cells = <2>;
 13	cpus {
 14		#address-cells = <1>;
 15		#size-cells = <0>;
 16		cpu@0 {
 17			device_type = "cpu";
 18			compatible = "img,i6500";
 19			reg = <0>;
 20			clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
 21		};
 22	};
 23
 24	aliases {
 25		serial0 = &uart0;
 26	};
 27
 28	cpu_intc: interrupt-controller {
 29		compatible = "mti,cpu-interrupt-controller";
 30		interrupt-controller;
 31		#address-cells = <0>;
 32		#interrupt-cells = <1>;
 33	};
 34
 35	coherency-manager {
 36		compatible = "mobileye,eyeq6-cm";
 37	};
 38
 39	xtal: clock-30000000 {
 40		compatible = "fixed-clock";
 41		#clock-cells = <0>;
 42		clock-frequency = <30000000>;
 43	};
 44
 45	soc: soc {
 46		compatible = "simple-bus";
 47		#address-cells = <2>;
 48		#size-cells = <2>;
 49		ranges;
 50
 51		olb_acc: system-controller@d2003000 {
 52			compatible = "mobileye,eyeq6h-acc-olb", "syscon";
 53			reg = <0x0 0xd2003000 0x0 0x1000>;
 54			#reset-cells = <1>;
 55			#clock-cells = <1>;
 56			clocks = <&xtal>;
 57			clock-names = "ref";
 58		};
 59
 60		olb_central: system-controller@d3100000 {
 61			compatible = "mobileye,eyeq6h-central-olb", "syscon";
 62			reg = <0x0 0xd3100000 0x0 0x1000>;
 63			#clock-cells = <1>;
 64			clocks = <&xtal>;
 65			clock-names = "ref";
 66		};
 67
 68		uart0: serial@d3331000 {
 69			compatible = "arm,pl011", "arm,primecell";
 70			reg = <0 0xd3331000 0x0 0x1000>;
 71			reg-io-width = <4>;
 72			interrupt-parent = <&gic>;
 73			interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
 74			clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
 75			clock-names = "uartclk", "apb_pclk";
 76		};
 77
 78		pinctrl_west: pinctrl@d3337000 {
 79			compatible = "pinctrl-single";
 80			reg = <0x0 0xd3337000 0x0 0xb0>;
 81			#pinctrl-cells = <1>;
 82			pinctrl-single,register-width = <32>;
 83			pinctrl-single,function-mask = <0xffff>;
 84		};
 85
 86		olb_west: system-controller@d3338000 {
 87			compatible = "mobileye,eyeq6h-west-olb", "syscon";
 88			reg = <0x0 0xd3338000 0x0 0x1000>;
 89			#reset-cells = <1>;
 90			#clock-cells = <1>;
 91			clocks = <&xtal>;
 92			clock-names = "ref";
 93		};
 94
 95		pinctrl_east: pinctrl@d3357000 {
 96			compatible = "pinctrl-single";
 97			reg = <0x0 0xd3357000 0x0 0xb0>;
 98			#pinctrl-cells = <1>;
 99			pinctrl-single,register-width = <32>;
100			pinctrl-single,function-mask = <0xffff>;
101		};
102
103		olb_east: system-controller@d3358000 {
104			compatible = "mobileye,eyeq6h-east-olb", "syscon";
105			reg = <0x0 0xd3358000 0x0 0x1000>;
106			#reset-cells = <1>;
107			#clock-cells = <1>;
108			clocks = <&xtal>;
109			clock-names = "ref";
110		};
111
112		emmc: mmc@d8010000 {
113			compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
114			reg = <0 0xd8010000 0x0 0x1000>;
115			interrupt-parent = <&gic>;
116			interrupts = <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>;
117			clocks = <&olb_south EQ6HC_SOUTH_DIV_EMMC>;
118			bus-width = <8>;
119			max-frequency = <200000000>;
120			mmc-ddr-1_8v;
121			sd-uhs-ddr50;
122			mmc-hs200-1_8v;
123			mmc-hs400-1_8v;
124			mmc-hs400-enhanced-strobe;
125
126			cdns,phy-input-delay-legacy = <4>;
127			cdns,phy-input-delay-mmc-highspeed = <2>;
128			cdns,phy-input-delay-mmc-ddr = <3>;
129			cdns,phy-dll-delay-sdclk = <32>;
130			cdns,phy-dll-delay-sdclk-hsmmc = <32>;
131			cdns,phy-dll-delay-strobe = <32>;
132		};
133
134		olb_south: system-controller@d8013000 {
135			compatible = "mobileye,eyeq6h-south-olb", "syscon";
136			reg = <0x0 0xd8013000 0x0 0x1000>;
137			#clock-cells = <1>;
138			clocks = <&xtal>;
139			clock-names = "ref";
140		};
141
142		pinctrl_south: pinctrl@d8014000 {
143			compatible = "pinctrl-single";
144			reg = <0x0 0xd8014000 0x0 0xf8>;
145			#pinctrl-cells = <1>;
146			pinctrl-single,register-width = <32>;
147			pinctrl-single,function-mask = <0xffff>;
148		};
149
150		olb_ddr0: system-controller@e4080000 {
151			compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
152			reg = <0x0 0xe4080000 0x0 0x1000>;
153			#clock-cells = <1>;
154			clocks = <&xtal>;
155			clock-names = "ref";
156		};
157
158		olb_ddr1: system-controller@e4081000 {
159			compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
160			reg = <0x0 0xe4081000 0x0 0x1000>;
161			#clock-cells = <1>;
162			clocks = <&xtal>;
163			clock-names = "ref";
164		};
165
166		gic: interrupt-controller@f0920000 {
167			compatible = "mti,gic";
168			reg = <0x0 0xf0920000 0x0 0x20000>;
169			interrupt-controller;
170			#interrupt-cells = <3>;
171
172			/*
173			 * Declare the interrupt-parent even though the mti,gic
174			 * binding doesn't require it, such that the kernel can
175			 * figure out that cpu_intc is the root interrupt
176			 * controller & should be probed first.
177			 */
178			interrupt-parent = <&cpu_intc>;
179
180			timer {
181				compatible = "mti,gic-timer";
182				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
183				clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
184			};
185		};
186	};
187};
188
189#include "eyeq6h-pins.dtsi"