danube.dtsi

  1// SPDX-License-Identifier: GPL-2.0
  2/ {
  3	#address-cells = <1>;
  4	#size-cells = <1>;
  5	compatible = "lantiq,xway", "lantiq,danube";
  6
  7	cpus {
  8		#address-cells = <1>;
  9		#size-cells = <0>;
 10
 11		cpu@0 {
 12			compatible = "mips,mips24Kc";
 13			reg = <0>;
 14		};
 15	};
 16
 17	biu@1f800000 {
 18		#address-cells = <1>;
 19		#size-cells = <1>;
 20		compatible = "lantiq,biu", "simple-bus";
 21		reg = <0x1f800000 0x800000>;
 22		ranges = <0x0 0x1f800000 0x7fffff>;
 23
 24		icu0: icu@80200 {
 25			#interrupt-cells = <1>;
 26			interrupt-controller;
 27			compatible = "lantiq,icu";
 28			reg = <0x80200 0x120>;
 29		};
 30
 31		watchdog@803f0 {
 32			compatible = "lantiq,wdt";
 33			reg = <0x803f0 0x10>;
 34		};
 35	};
 36
 37	sram@1f000000 {
 38		#address-cells = <1>;
 39		#size-cells = <1>;
 40		compatible = "lantiq,sram";
 41		reg = <0x1f000000 0x800000>;
 42		ranges = <0x0 0x1f000000 0x7fffff>;
 43
 44		eiu0: eiu@101000 {
 45			#interrupt-cells = <1>;
 46			interrupt-controller;
 47			compatible = "lantiq,eiu-xway";
 48			reg = <0x101000 0x1000>;
 49		};
 50
 51		pmu0: pmu@102000 {
 52			compatible = "lantiq,pmu-xway";
 53			reg = <0x102000 0x1000>;
 54		};
 55
 56		cgu0: cgu@103000 {
 57			compatible = "lantiq,cgu-xway";
 58			reg = <0x103000 0x1000>;
 59			#clock-cells = <1>;
 60		};
 61
 62		rcu0: rcu@203000 {
 63			compatible = "lantiq,rcu-xway";
 64			reg = <0x203000 0x1000>;
 65		};
 66	};
 67
 68	fpi@10000000 {
 69		#address-cells = <1>;
 70		#size-cells = <1>;
 71		compatible = "lantiq,fpi", "simple-bus";
 72		ranges = <0x0 0x10000000 0xeefffff>;
 73		reg = <0x10000000 0xef00000>;
 74
 75		gptu@e100a00 {
 76			compatible = "lantiq,gptu-xway";
 77			reg = <0xe100a00 0x100>;
 78		};
 79
 80		serial@e100c00 {
 81			compatible = "lantiq,asc";
 82			reg = <0xe100c00 0x400>;
 83			interrupt-parent = <&icu0>;
 84			interrupts = <112 113 114>;
 85		};
 86
 87		dma0: dma@e104100 {
 88			compatible = "lantiq,dma-xway";
 89			reg = <0xe104100 0x800>;
 90		};
 91
 92		ebu0: ebu@e105300 {
 93			compatible = "lantiq,ebu-xway";
 94			reg = <0xe105300 0x100>;
 95		};
 96
 97		pci0: pci@e105400 {
 98			#address-cells = <3>;
 99			#size-cells = <2>;
100			#interrupt-cells = <1>;
101			compatible = "lantiq,pci-xway";
102			bus-range = <0x0 0x0>;
103			ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000	/* pci memory */
104				  0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
105			reg = <0x7000000 0x8000		/* config space */
106				0xe105400 0x400>;	/* pci bridge */
107
108			device_type = "pci";
109		};
110	};
111};