mmu.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
  4 * Copyright (C) 2008-2009 PetaLogix
  5 * Copyright (C) 2006 Atmark Techno, Inc.
  6 */
  7
  8#ifndef _ASM_MICROBLAZE_MMU_H
  9#define _ASM_MICROBLAZE_MMU_H
 10
 11#  ifdef __KERNEL__
 12#   ifndef __ASSEMBLER__
 13
 14/* Default "unsigned long" context */
 15typedef unsigned long mm_context_t;
 16
 17/* Hardware Page Table Entry */
 18typedef struct _PTE {
 19	unsigned long    v:1;	/* Entry is valid */
 20	unsigned long vsid:24;	/* Virtual segment identifier */
 21	unsigned long    h:1;	/* Hash algorithm indicator */
 22	unsigned long  api:6;	/* Abbreviated page index */
 23	unsigned long  rpn:20;	/* Real (physical) page number */
 24	unsigned long     :3;	/* Unused */
 25	unsigned long    r:1;	/* Referenced */
 26	unsigned long    c:1;	/* Changed */
 27	unsigned long    w:1;	/* Write-thru cache mode */
 28	unsigned long    i:1;	/* Cache inhibited */
 29	unsigned long    m:1;	/* Memory coherence */
 30	unsigned long    g:1;	/* Guarded */
 31	unsigned long     :1;	/* Unused */
 32	unsigned long   pp:2;	/* Page protection */
 33} PTE;
 34
 35/* Values for PP (assumes Ks=0, Kp=1) */
 36#  define PP_RWXX	0 /* Supervisor read/write, User none */
 37#  define PP_RWRX	1 /* Supervisor read/write, User read */
 38#  define PP_RWRW	2 /* Supervisor read/write, User read/write */
 39#  define PP_RXRX	3 /* Supervisor read,       User read */
 40
 41/* Segment Register */
 42typedef struct _SEGREG {
 43	unsigned long    t:1;	/* Normal or I/O  type */
 44	unsigned long   ks:1;	/* Supervisor 'key' (normally 0) */
 45	unsigned long   kp:1;	/* User 'key' (normally 1) */
 46	unsigned long    n:1;	/* No-execute */
 47	unsigned long     :4;	/* Unused */
 48	unsigned long vsid:24;	/* Virtual Segment Identifier */
 49} SEGREG;
 50
 51extern void _tlbie(unsigned long va);	/* invalidate a TLB entry */
 52extern void _tlbia(void);		/* invalidate all TLB entries */
 53
 54/*
 55 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
 56 * mapping has to increase tlb_skip size.
 57 */
 58extern u32 tlb_skip;
 59#   endif /* __ASSEMBLER__ */
 60
 61/*
 62 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
 63 * instruction and data sides share a unified, 64-entry, semi-associative
 64 * TLB which is maintained totally under software control. In addition, the
 65 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
 66 * TLB which serves as a first level to the shared TLB. These two TLBs are
 67 * known as the UTLB and ITLB, respectively.
 68 */
 69
 70#  define MICROBLAZE_TLB_SIZE 64
 71
 72/* For cases when you want to skip some TLB entries */
 73#  define MICROBLAZE_TLB_SKIP 0
 74
 75/* Use the last TLB for temporary access to LMB */
 76#  define MICROBLAZE_LMB_TLB_ID 63
 77
 78/*
 79 * TLB entries are defined by a "high" tag portion and a "low" data
 80 * portion. The data portion is 32-bits.
 81 *
 82 * TLB entries are managed entirely under software control by reading,
 83 * writing, and searching using the MTS and MFS instructions.
 84 */
 85
 86#  define TLB_LO		1
 87#  define TLB_HI		0
 88#  define TLB_DATA		TLB_LO
 89#  define TLB_TAG		TLB_HI
 90
 91/* Tag portion */
 92#  define TLB_EPN_MASK		0xFFFFFC00 /* Effective Page Number */
 93#  define TLB_PAGESZ_MASK	0x00000380
 94#  define TLB_PAGESZ(x)		(((x) & 0x7) << 7)
 95#  define PAGESZ_1K		0
 96#  define PAGESZ_4K		1
 97#  define PAGESZ_16K		2
 98#  define PAGESZ_64K		3
 99#  define PAGESZ_256K		4
100#  define PAGESZ_1M		5
101#  define PAGESZ_4M		6
102#  define PAGESZ_16M		7
103#  define TLB_VALID		0x00000040 /* Entry is valid */
104
105/* Data portion */
106#  define TLB_RPN_MASK		0xFFFFFC00 /* Real Page Number */
107#  define TLB_PERM_MASK		0x00000300
108#  define TLB_EX		0x00000200 /* Instruction execution allowed */
109#  define TLB_WR		0x00000100 /* Writes permitted */
110#  define TLB_ZSEL_MASK		0x000000F0
111#  define TLB_ZSEL(x)		(((x) & 0xF) << 4)
112#  define TLB_ATTR_MASK		0x0000000F
113#  define TLB_W			0x00000008 /* Caching is write-through */
114#  define TLB_I			0x00000004 /* Caching is inhibited */
115#  define TLB_M			0x00000002 /* Memory is coherent */
116#  define TLB_G			0x00000001 /* Memory is guarded from prefetch */
117
118#  endif /* __KERNEL__ */
119#endif /* _ASM_MICROBLAZE_MMU_H */