m53xxacr.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/****************************************************************************/
  3
  4/*
  5 * m53xxacr.h -- ColdFire version 3 core cache support
  6 *
  7 * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
  8 */
  9
 10/****************************************************************************/
 11#ifndef m53xxacr_h
 12#define m53xxacr_h
 13/****************************************************************************/
 14
 15/*
 16 * All varients of the ColdFire using version 3 cores have a similar
 17 * cache setup. They have a unified instruction and data cache, with
 18 * configurable write-through or copy-back operation.
 19 */
 20
 21/*
 22 * Define the Cache Control register flags.
 23 */
 24#define CACR_EC		0x80000000	/* Enable cache */
 25#define CACR_ESB	0x20000000	/* Enable store buffer */
 26#define CACR_DPI	0x10000000	/* Disable invalidation by CPUSHL */
 27#define CACR_HLCK	0x08000000	/* Half cache lock mode */
 28#define CACR_CINVA	0x01000000	/* Invalidate cache */
 29#define CACR_DNFB	0x00000400	/* Inhibited fill buffer */
 30#define CACR_DCM_WT	0x00000000	/* Cacheable write-through */
 31#define CACR_DCM_CB	0x00000100	/* Cacheable copy-back */
 32#define CACR_DCM_PRE	0x00000200	/* Cache inhibited, precise */
 33#define CACR_DCM_IMPRE	0x00000300	/* Cache inhibited, imprecise */
 34#define CACR_WPROTECT	0x00000020	/* Write protect*/
 35#define CACR_EUSP	0x00000010	/* Eanble separate user a7 */
 36
 37/*
 38 * Define the Access Control register flags.
 39 */
 40#define ACR_BASE_POS	24		/* Address Base (upper 8 bits) */
 41#define ACR_MASK_POS	16		/* Address Mask (next 8 bits) */
 42#define ACR_ENABLE	0x00008000	/* Enable this ACR */
 43#define ACR_USER	0x00000000	/* Allow only user accesses */
 44#define ACR_SUPER	0x00002000	/* Allow supervisor access only */
 45#define ACR_ANY		0x00004000	/* Allow any access type */
 46#define ACR_CM_WT	0x00000000	/* Cacheable, write-through */
 47#define ACR_CM_CB	0x00000020	/* Cacheable, copy-back */
 48#define ACR_CM_PRE	0x00000040	/* Cache inhibited, precise */
 49#define ACR_CM_IMPRE	0x00000060	/* Cache inhibited, imprecise */
 50#define ACR_WPROTECT	0x00000004	/* Write protect region */
 51
 52/*
 53 * Define the cache type and arrangement (needed for pushes).
 54 */
 55#if defined(CONFIG_M5307)
 56#define	CACHE_SIZE	0x2000		/* 8k of unified cache */
 57#define	ICACHE_SIZE	CACHE_SIZE
 58#define	DCACHE_SIZE	CACHE_SIZE
 59#elif defined(CONFIG_M53xx)
 60#define	CACHE_SIZE	0x4000		/* 16k of unified cache */
 61#define	ICACHE_SIZE	CACHE_SIZE
 62#define	DCACHE_SIZE	CACHE_SIZE
 63#endif
 64
 65#define	CACHE_LINE_SIZE	16		/* 16 byte line size */
 66#define	CACHE_WAYS	4		/* 4 ways - set associative */
 67
 68/*
 69 * Set the cache controller settings we will use. This default in the
 70 * CACR is cache inhibited, we use the ACR register to set cacheing
 71 * enabled on the regions we want (eg RAM).
 72 */
 73#if defined(CONFIG_CACHE_COPYBACK)
 74#define CACHE_TYPE	ACR_CM_CB
 75#define CACHE_PUSH
 76#else
 77#define CACHE_TYPE	ACR_CM_WT
 78#endif
 79
 80#ifdef CONFIG_COLDFIRE_SW_A7
 81#define CACHE_MODE	(CACR_EC + CACR_ESB + CACR_DCM_PRE)
 82#else
 83#define CACHE_MODE	(CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
 84#endif
 85
 86/*
 87 * Unified cache means we will never need to flush for coherency of
 88 * instruction fetch. We will need to flush to maintain memory/DMA
 89 * coherency though in all cases. And for copyback caches we will need
 90 * to push cached data as well.
 91 */
 92#define CACHE_INIT        (CACHE_MODE + CACR_CINVA - CACR_EC)
 93#define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINVA)
 94#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA)
 95
 96#define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
 97			 (0x000f0000) + \
 98			 (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
 99#define ACR1_MODE	0
100
101/****************************************************************************/
102#endif  /* m53xxsim_h */