CHANGES

  1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  2MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
  3M68000 Hi-Performance Microprocessor Division
  4M68060 Software Package
  5Production Release P1.00 -- October 10, 1994
  6
  7M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
  8
  9THE SOFTWARE is provided on an "AS IS" basis and without warranty.
 10To the maximum extent permitted by applicable law,
 11MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
 12INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 13and any warranty against infringement with regard to the SOFTWARE
 14(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
 15
 16To the maximum extent permitted by applicable law,
 17IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
 18(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
 19BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
 20ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
 21Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
 22
 23You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
 24so long as this entire notice is retained without alteration in any modified and/or
 25redistributed versions, and that such modified versions are clearly identified as such.
 26No licenses are granted by implication, estoppel or otherwise under any patents
 27or trademarks of Motorola, Inc.
 28~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 29
 30CHANGES SINCE LAST RELEASE:
 31---------------------------
 32
 331) "movep" emulation where data was being read from memory
 34was reading the intermediate bytes. Emulation now only
 35reads the required bytes.
 36
 372) "flogn", "flog2", and "flog10" of "1" was setting the
 38Inexact FPSR bit. Emulation now does not set Inexact for
 39this case.
 40
 413) For an opclass three FP instruction where the effective addressing
 42mode was pre-decrement or post-increment and the address register
 43was A0 or A1, the address register was not being updated as a result
 44of the operation. This has been corrected.
 45
 464) Beta B.2 version had the following erratum:
 47
 48	Scenario:
 49	---------
 50	If {i,d}mem_{read,write}_{byte,word,long}() returns
 51	a failing value to the 68060SP, the package ignores
 52	this return value and continues with program execution
 53	as if it never received a failing value.
 54
 55	Effect:
 56	-------
 57	For example, if a user executed "fsin.x ADDR,fp0" where
 58	ADDR should cause a "segmentation violation", the memory read
 59	requested by the package should return a failing value
 60	to the package. Since the package currently ignores this
 61	return value, the user program will continue to the
 62	next instruction, and the result created in fp0 will be
 63	undefined.
 64
 65	Fix:
 66	----
 67	This has been fixed in the current release.
 68
 69	Notes:
 70	------
 71	Upon receiving a non-zero (failing) return value from
 72	a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
 73	the package creates a 16-byte access error stack frame
 74	from the current exception stack frame and exits
 75	through the "call-out" _real_access(). This is the process
 76	as described in the MC68060 User's Manual.
 77
 78	For instruction read access errors, the info stacked is:
 79		SR	= SR at time of exception
 80		PC	= PC of instruction being emulated
 81		VOFF	= $4008 (stack frame format type)
 82		ADDRESS	= PC of instruction being emulated
 83		FSLW	= FAULT STATUS LONGWORD
 84
 85	The valid FSLW bits are:
 86		bit 27		= 1	(misaligned bit)
 87		bit 24		= 1	(read)
 88		bit 23		= 0	(write)
 89		bit 22:21	= 10	(SIZE = word)
 90		bit 20:19	= 00	(TT)
 91		bit 18:16	= x10	(TM; x = 1 for supervisor mode)
 92		bit 15		= 1	(IO)
 93		bit 0		= 1	(Software Emulation Error)
 94
 95	all other bits are EQUAL TO ZERO and can be set by the _real_access()
 96	"call-out" stub by the user as appropriate. The MC68060 User's Manual
 97	stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
 98	other bits.
 99
100	For data read/write access errors, the info stacked is:
101		SR	= SR at time of exception
102		PC	= PC of instruction being emulated
103		VOFF	= $4008 (stack frame format type)
104		ADDRESS	= Address of source or destination operand
105		FSLW	= FAULT STATUS LONGWORD
106
107	The valid FSLW bits are:
108		bit 27		= 0	(misaligned bit)
109		bit 24		= x	(read; 1 if read, 0 if write)
110		bit 23		= x	(write; 1 if write, 0 if read)
111		bit 22:21	= xx	(SIZE; see MC68060 User's Manual)
112		bit 20:19	= 00	(TT)
113		bit 18:16	= x01	(TM; x = 1 for supervisor mode)
114		bit 15		= 0	(IO)
115		bit 0		= 1	(Software Emulation Error)
116
117	all other bits are EQUAL TO ZERO and can be set by the _real_access()
118	"call-out" stub by the user as appropriate. The MC68060 User's Manual
119	stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
120	other bits.