traps.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Author: Huacai Chen <chenhuacai@loongson.cn>
   4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   5 */
   6#include <linux/bitfield.h>
   7#include <linux/bitops.h>
   8#include <linux/bug.h>
   9#include <linux/compiler.h>
  10#include <linux/context_tracking.h>
  11#include <linux/entry-common.h>
  12#include <linux/init.h>
  13#include <linux/kernel.h>
  14#include <linux/kexec.h>
  15#include <linux/module.h>
  16#include <linux/export.h>
  17#include <linux/extable.h>
  18#include <linux/mm.h>
  19#include <linux/sched/mm.h>
  20#include <linux/sched/debug.h>
  21#include <linux/smp.h>
  22#include <linux/spinlock.h>
  23#include <linux/kallsyms.h>
  24#include <linux/memblock.h>
  25#include <linux/interrupt.h>
  26#include <linux/ptrace.h>
  27#include <linux/kgdb.h>
  28#include <linux/kdebug.h>
  29#include <linux/notifier.h>
  30#include <linux/irq.h>
  31#include <linux/perf_event.h>
  32
  33#include <asm/addrspace.h>
  34#include <asm/bootinfo.h>
  35#include <asm/branch.h>
  36#include <asm/break.h>
  37#include <asm/cpu.h>
  38#include <asm/exception.h>
  39#include <asm/fpu.h>
  40#include <asm/lbt.h>
  41#include <asm/inst.h>
  42#include <asm/kgdb.h>
  43#include <asm/loongarch.h>
  44#include <asm/mmu_context.h>
  45#include <asm/pgtable.h>
  46#include <asm/ptrace.h>
  47#include <asm/sections.h>
  48#include <asm/siginfo.h>
  49#include <asm/stacktrace.h>
  50#include <asm/tlb.h>
  51#include <asm/types.h>
  52#include <asm/unwind.h>
  53#include <asm/uprobes.h>
  54
  55#include "access-helper.h"
  56
  57void *exception_table[EXCCODE_INT_START] = {
  58	[0 ... EXCCODE_INT_START - 1] = handle_reserved,
  59
  60	[EXCCODE_TLBI]		= handle_tlb_load,
  61	[EXCCODE_TLBL]		= handle_tlb_load,
  62	[EXCCODE_TLBS]		= handle_tlb_store,
  63	[EXCCODE_TLBM]		= handle_tlb_modify,
  64	[EXCCODE_TLBNR]		= handle_tlb_protect,
  65	[EXCCODE_TLBNX]		= handle_tlb_protect,
  66	[EXCCODE_TLBPE]		= handle_tlb_protect,
  67	[EXCCODE_ADE]		= handle_ade,
  68	[EXCCODE_ALE]		= handle_ale,
  69	[EXCCODE_BCE]		= handle_bce,
  70	[EXCCODE_SYS]		= handle_sys,
  71	[EXCCODE_BP]		= handle_bp,
  72	[EXCCODE_INE]		= handle_ri,
  73	[EXCCODE_IPE]		= handle_ri,
  74	[EXCCODE_FPDIS]		= handle_fpu,
  75	[EXCCODE_LSXDIS]	= handle_lsx,
  76	[EXCCODE_LASXDIS]	= handle_lasx,
  77	[EXCCODE_FPE]		= handle_fpe,
  78	[EXCCODE_WATCH]		= handle_watch,
  79	[EXCCODE_BTDIS]		= handle_lbt,
  80};
  81EXPORT_SYMBOL_GPL(exception_table);
  82
  83static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
  84			   const char *loglvl, bool user)
  85{
  86	unsigned long addr;
  87	struct unwind_state state;
  88	struct pt_regs *pregs = (struct pt_regs *)regs;
  89
  90	if (!task)
  91		task = current;
  92
  93	printk("%sCall Trace:", loglvl);
  94	for (unwind_start(&state, task, pregs);
  95	      !unwind_done(&state); unwind_next_frame(&state)) {
  96		addr = unwind_get_return_address(&state);
  97		print_ip_sym(loglvl, addr);
  98	}
  99	printk("%s\n", loglvl);
 100}
 101
 102static void show_stacktrace(struct task_struct *task,
 103	const struct pt_regs *regs, const char *loglvl, bool user)
 104{
 105	int i;
 106	const int field = 2 * sizeof(unsigned long);
 107	unsigned long stackdata;
 108	unsigned long *sp = (unsigned long *)regs->regs[3];
 109
 110	printk("%sStack :", loglvl);
 111	i = 0;
 112	while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 113		if (i && ((i % (64 / field)) == 0)) {
 114			pr_cont("\n");
 115			printk("%s       ", loglvl);
 116		}
 117		if (i > 39) {
 118			pr_cont(" ...");
 119			break;
 120		}
 121
 122		if (__get_addr(&stackdata, sp++, user)) {
 123			pr_cont(" (Bad stack address)");
 124			break;
 125		}
 126
 127		pr_cont(" %0*lx", field, stackdata);
 128		i++;
 129	}
 130	pr_cont("\n");
 131	show_backtrace(task, regs, loglvl, user);
 132}
 133
 134void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
 135{
 136	struct pt_regs regs;
 137
 138	regs.csr_crmd = 0;
 139	if (sp) {
 140		regs.csr_era = 0;
 141		regs.regs[1] = 0;
 142		regs.regs[3] = (unsigned long)sp;
 143	} else {
 144		if (!task || task == current)
 145			prepare_frametrace(&regs);
 146		else {
 147			regs.csr_era = task->thread.reg01;
 148			regs.regs[1] = 0;
 149			regs.regs[3] = task->thread.reg03;
 150			regs.regs[22] = task->thread.reg22;
 151		}
 152	}
 153
 154	show_stacktrace(task, &regs, loglvl, false);
 155}
 156
 157static void show_code(unsigned int *pc, bool user)
 158{
 159	long i;
 160	unsigned int insn;
 161
 162	printk("Code:");
 163
 164	for(i = -3 ; i < 6 ; i++) {
 165		if (__get_inst(&insn, pc + i, user)) {
 166			pr_cont(" (Bad address in era)\n");
 167			break;
 168		}
 169		pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 170	}
 171	pr_cont("\n");
 172}
 173
 174static void print_bool_fragment(const char *key, unsigned long val, bool first)
 175{
 176	/* e.g. "+PG", "-DA" */
 177	pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key);
 178}
 179
 180static void print_plv_fragment(const char *key, int val)
 181{
 182	/* e.g. "PLV0", "PPLV3" */
 183	pr_cont("%s%d", key, val);
 184}
 185
 186static void print_memory_type_fragment(const char *key, unsigned long val)
 187{
 188	const char *humanized_type;
 189
 190	switch (val) {
 191	case 0:
 192		humanized_type = "SUC";
 193		break;
 194	case 1:
 195		humanized_type = "CC";
 196		break;
 197	case 2:
 198		humanized_type = "WUC";
 199		break;
 200	default:
 201		pr_cont(" %s=Reserved(%lu)", key, val);
 202		return;
 203	}
 204
 205	/* e.g. " DATM=WUC" */
 206	pr_cont(" %s=%s", key, humanized_type);
 207}
 208
 209static void print_intr_fragment(const char *key, unsigned long val)
 210{
 211	/* e.g. "LIE=0-1,3,5-7" */
 212	pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val);
 213}
 214
 215static void print_crmd(unsigned long x)
 216{
 217	printk(" CRMD: %08lx (", x);
 218	print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x));
 219	print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false);
 220	print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false);
 221	print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false);
 222	print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x));
 223	print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x));
 224	print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false);
 225	pr_cont(")\n");
 226}
 227
 228static void print_prmd(unsigned long x)
 229{
 230	printk(" PRMD: %08lx (", x);
 231	print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x));
 232	print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false);
 233	print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false);
 234	pr_cont(")\n");
 235}
 236
 237static void print_euen(unsigned long x)
 238{
 239	printk(" EUEN: %08lx (", x);
 240	print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true);
 241	print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false);
 242	print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false);
 243	print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false);
 244	pr_cont(")\n");
 245}
 246
 247static void print_ecfg(unsigned long x)
 248{
 249	printk(" ECFG: %08lx (", x);
 250	print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x));
 251	pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x));
 252}
 253
 254static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode)
 255{
 256	/*
 257	 * LoongArch users and developers are probably more familiar with
 258	 * those names found in the ISA manual, so we are going to print out
 259	 * the latter. This will require some mapping.
 260	 */
 261	switch (ecode) {
 262	case EXCCODE_RSV: return "INT";
 263	case EXCCODE_TLBL: return "PIL";
 264	case EXCCODE_TLBS: return "PIS";
 265	case EXCCODE_TLBI: return "PIF";
 266	case EXCCODE_TLBM: return "PME";
 267	case EXCCODE_TLBNR: return "PNR";
 268	case EXCCODE_TLBNX: return "PNX";
 269	case EXCCODE_TLBPE: return "PPI";
 270	case EXCCODE_ADE:
 271		switch (esubcode) {
 272		case EXSUBCODE_ADEF: return "ADEF";
 273		case EXSUBCODE_ADEM: return "ADEM";
 274		}
 275		break;
 276	case EXCCODE_ALE: return "ALE";
 277	case EXCCODE_BCE: return "BCE";
 278	case EXCCODE_SYS: return "SYS";
 279	case EXCCODE_BP: return "BRK";
 280	case EXCCODE_INE: return "INE";
 281	case EXCCODE_IPE: return "IPE";
 282	case EXCCODE_FPDIS: return "FPD";
 283	case EXCCODE_LSXDIS: return "SXD";
 284	case EXCCODE_LASXDIS: return "ASXD";
 285	case EXCCODE_FPE:
 286		switch (esubcode) {
 287		case EXCSUBCODE_FPE: return "FPE";
 288		case EXCSUBCODE_VFPE: return "VFPE";
 289		}
 290		break;
 291	case EXCCODE_WATCH:
 292		switch (esubcode) {
 293		case EXCSUBCODE_WPEF: return "WPEF";
 294		case EXCSUBCODE_WPEM: return "WPEM";
 295		}
 296		break;
 297	case EXCCODE_BTDIS: return "BTD";
 298	case EXCCODE_BTE: return "BTE";
 299	case EXCCODE_GSPR: return "GSPR";
 300	case EXCCODE_HVC: return "HVC";
 301	case EXCCODE_GCM:
 302		switch (esubcode) {
 303		case EXCSUBCODE_GCSC: return "GCSC";
 304		case EXCSUBCODE_GCHC: return "GCHC";
 305		}
 306		break;
 307	/*
 308	 * The manual did not mention the EXCCODE_SE case, but print out it
 309	 * nevertheless.
 310	 */
 311	case EXCCODE_SE: return "SE";
 312	}
 313
 314	return "???";
 315}
 316
 317static void print_estat(unsigned long x)
 318{
 319	unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x);
 320	unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x);
 321
 322	printk("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode));
 323	print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x));
 324	pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode);
 325}
 326
 327static void __show_regs(const struct pt_regs *regs)
 328{
 329	const int field = 2 * sizeof(unsigned long);
 330	unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat);
 331
 332	show_regs_print_info(KERN_DEFAULT);
 333
 334	/* Print saved GPRs except $zero (substituting with PC/ERA) */
 335#define GPR_FIELD(x) field, regs->regs[x]
 336	printk("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n",
 337	       field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3));
 338	printk("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n",
 339	       GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7));
 340	printk("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n",
 341	       GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11));
 342	printk("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n",
 343	       GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15));
 344	printk("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n",
 345	       GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19));
 346	printk("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n",
 347	       GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23));
 348	printk("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n",
 349	       GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27));
 350	printk("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n",
 351	       GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31));
 352
 353	/* The slot for $zero is reused as the syscall restart flag */
 354	if (regs->regs[0])
 355		printk("syscall restart flag: %0*lx\n", GPR_FIELD(0));
 356
 357	if (user_mode(regs)) {
 358		printk("   ra: %0*lx\n", GPR_FIELD(1));
 359		printk("  ERA: %0*lx\n", field, regs->csr_era);
 360	} else {
 361		printk("   ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]);
 362		printk("  ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era);
 363	}
 364#undef GPR_FIELD
 365
 366	/* Print saved important CSRs */
 367	print_crmd(regs->csr_crmd);
 368	print_prmd(regs->csr_prmd);
 369	print_euen(regs->csr_euen);
 370	print_ecfg(regs->csr_ecfg);
 371	print_estat(regs->csr_estat);
 372
 373	if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
 374		printk(" BADV: %0*lx\n", field, regs->csr_badvaddr);
 375
 376	printk(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
 377	       cpu_family_string(), cpu_full_name_string());
 378}
 379
 380void show_regs(struct pt_regs *regs)
 381{
 382	__show_regs((struct pt_regs *)regs);
 383	dump_stack();
 384}
 385
 386void show_registers(struct pt_regs *regs)
 387{
 388	__show_regs(regs);
 389	print_modules();
 390	printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 391	       current->comm, current->pid, current_thread_info(), current);
 392
 393	show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
 394	show_code((void *)regs->csr_era, user_mode(regs));
 395	printk("\n");
 396}
 397
 398static DEFINE_RAW_SPINLOCK(die_lock);
 399
 400void die(const char *str, struct pt_regs *regs)
 401{
 402	int ret;
 403	static int die_counter;
 404
 405	oops_enter();
 406
 407	ret = notify_die(DIE_OOPS, str, regs, 0,
 408			 current->thread.trap_nr, SIGSEGV);
 409
 410	console_verbose();
 411	raw_spin_lock_irq(&die_lock);
 412	bust_spinlocks(1);
 413
 414	printk("%s[#%d]:\n", str, ++die_counter);
 415	show_registers(regs);
 416	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 417	raw_spin_unlock_irq(&die_lock);
 418
 419	oops_exit();
 420
 421	if (ret == NOTIFY_STOP)
 422		return;
 423
 424	if (regs && kexec_should_crash(current))
 425		crash_kexec(regs);
 426
 427	if (in_interrupt())
 428		panic("Fatal exception in interrupt");
 429
 430	if (panic_on_oops)
 431		panic("Fatal exception");
 432
 433	make_task_dead(SIGSEGV);
 434}
 435
 436static inline void setup_vint_size(unsigned int size)
 437{
 438	unsigned int vs;
 439
 440	vs = ilog2(size/4);
 441
 442	if (vs == 0 || vs > 7)
 443		panic("vint_size %d Not support yet", vs);
 444
 445	csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG);
 446}
 447
 448/*
 449 * Send SIGFPE according to FCSR Cause bits, which must have already
 450 * been masked against Enable bits.  This is impotant as Inexact can
 451 * happen together with Overflow or Underflow, and `ptrace' can set
 452 * any bits.
 453 */
 454static void force_fcsr_sig(unsigned long fcsr,
 455			void __user *fault_addr, struct task_struct *tsk)
 456{
 457	int si_code = FPE_FLTUNK;
 458
 459	if (fcsr & FPU_CSR_INV_X)
 460		si_code = FPE_FLTINV;
 461	else if (fcsr & FPU_CSR_DIV_X)
 462		si_code = FPE_FLTDIV;
 463	else if (fcsr & FPU_CSR_OVF_X)
 464		si_code = FPE_FLTOVF;
 465	else if (fcsr & FPU_CSR_UDF_X)
 466		si_code = FPE_FLTUND;
 467	else if (fcsr & FPU_CSR_INE_X)
 468		si_code = FPE_FLTRES;
 469
 470	force_sig_fault(SIGFPE, si_code, fault_addr);
 471}
 472
 473static int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr)
 474{
 475	int si_code;
 476
 477	switch (sig) {
 478	case 0:
 479		return 0;
 480
 481	case SIGFPE:
 482		force_fcsr_sig(fcsr, fault_addr, current);
 483		return 1;
 484
 485	case SIGBUS:
 486		force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
 487		return 1;
 488
 489	case SIGSEGV:
 490		mmap_read_lock(current->mm);
 491		if (vma_lookup(current->mm, (unsigned long)fault_addr))
 492			si_code = SEGV_ACCERR;
 493		else
 494			si_code = SEGV_MAPERR;
 495		mmap_read_unlock(current->mm);
 496		force_sig_fault(SIGSEGV, si_code, fault_addr);
 497		return 1;
 498
 499	default:
 500		force_sig(sig);
 501		return 1;
 502	}
 503}
 504
 505/*
 506 * Delayed fp exceptions when doing a lazy ctx switch
 507 */
 508asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr)
 509{
 510	int sig;
 511	void __user *fault_addr;
 512	irqentry_state_t state = irqentry_enter(regs);
 513
 514	if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
 515		       SIGFPE) == NOTIFY_STOP)
 516		goto out;
 517
 518	/* Clear FCSR.Cause before enabling interrupts */
 519	write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr));
 520	local_irq_enable();
 521
 522	die_if_kernel("FP exception in kernel code", regs);
 523
 524	sig = SIGFPE;
 525	fault_addr = (void __user *) regs->csr_era;
 526
 527	/* Send a signal if required.  */
 528	process_fpemu_return(sig, fault_addr, fcsr);
 529
 530out:
 531	local_irq_disable();
 532	irqentry_exit(regs, state);
 533}
 534
 535asmlinkage void noinstr do_ade(struct pt_regs *regs)
 536{
 537	irqentry_state_t state = irqentry_enter(regs);
 538	unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, regs->csr_estat);
 539
 540	if ((esubcode == EXSUBCODE_ADEM) && fixup_exception(regs))
 541		goto out;
 542
 543	die_if_kernel("Kernel ade access", regs);
 544	force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);
 545
 546out:
 547	irqentry_exit(regs, state);
 548}
 549
 550/* sysctl hooks */
 551int unaligned_enabled __read_mostly = 1;	/* Enabled by default */
 552int no_unaligned_warning __read_mostly = 1;	/* Only 1 warning by default */
 553
 554asmlinkage void noinstr do_ale(struct pt_regs *regs)
 555{
 556	irqentry_state_t state = irqentry_enter(regs);
 557
 558#ifndef CONFIG_ARCH_STRICT_ALIGN
 559	die_if_kernel("Kernel ale access", regs);
 560	force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
 561#else
 562	bool pie = regs_irqs_disabled(regs);
 563	unsigned int *pc;
 564
 565	if (!pie)
 566		local_irq_enable();
 567
 568	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr);
 569
 570	/*
 571	 * Did we catch a fault trying to load an instruction?
 572	 */
 573	if (regs->csr_badvaddr == regs->csr_era)
 574		goto sigbus;
 575	if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
 576		goto sigbus;
 577	if (!unaligned_enabled)
 578		goto sigbus;
 579	if (!no_unaligned_warning)
 580		show_registers(regs);
 581
 582	pc = (unsigned int *)exception_era(regs);
 583
 584	emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc);
 585
 586	goto out;
 587
 588sigbus:
 589	die_if_kernel("Kernel ale access", regs);
 590	force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
 591out:
 592	if (!pie)
 593		local_irq_disable();
 594#endif
 595	irqentry_exit(regs, state);
 596}
 597
 598#ifdef CONFIG_GENERIC_BUG
 599int is_valid_bugaddr(unsigned long addr)
 600{
 601	return 1;
 602}
 603#endif /* CONFIG_GENERIC_BUG */
 604
 605static void bug_handler(struct pt_regs *regs)
 606{
 607	if (user_mode(regs)) {
 608		force_sig(SIGTRAP);
 609		return;
 610	}
 611
 612	switch (report_bug(regs->csr_era, regs)) {
 613	case BUG_TRAP_TYPE_BUG:
 614		die("Oops - BUG", regs);
 615		break;
 616
 617	case BUG_TRAP_TYPE_WARN:
 618		/* Skip the BUG instruction and continue */
 619		regs->csr_era += LOONGARCH_INSN_SIZE;
 620		break;
 621
 622	default:
 623		if (!fixup_exception(regs))
 624			die("Oops - BUG", regs);
 625	}
 626}
 627
 628asmlinkage void noinstr do_bce(struct pt_regs *regs)
 629{
 630	bool user = user_mode(regs);
 631	bool pie = regs_irqs_disabled(regs);
 632	unsigned long era = exception_era(regs);
 633	unsigned long badv = 0, lower = 0, upper = ULONG_MAX;
 634	union loongarch_instruction insn;
 635	irqentry_state_t state = irqentry_enter(regs);
 636
 637	if (!pie)
 638		local_irq_enable();
 639
 640	current->thread.trap_nr = read_csr_excode();
 641
 642	die_if_kernel("Bounds check error in kernel code", regs);
 643
 644	/*
 645	 * Pull out the address that failed bounds checking, and the lower /
 646	 * upper bound, by minimally looking at the faulting instruction word
 647	 * and reading from the correct register.
 648	 */
 649	if (__get_inst(&insn.word, (u32 *)era, user))
 650		goto bad_era;
 651
 652	switch (insn.reg3_format.opcode) {
 653	case asrtle_op:
 654		if (insn.reg3_format.rd != 0)
 655			break;	/* not asrtle */
 656		badv = regs->regs[insn.reg3_format.rj];
 657		upper = regs->regs[insn.reg3_format.rk];
 658		break;
 659
 660	case asrtgt_op:
 661		if (insn.reg3_format.rd != 0)
 662			break;	/* not asrtgt */
 663		badv = regs->regs[insn.reg3_format.rj];
 664		lower = regs->regs[insn.reg3_format.rk];
 665		break;
 666
 667	case ldleb_op:
 668	case ldleh_op:
 669	case ldlew_op:
 670	case ldled_op:
 671	case stleb_op:
 672	case stleh_op:
 673	case stlew_op:
 674	case stled_op:
 675	case fldles_op:
 676	case fldled_op:
 677	case fstles_op:
 678	case fstled_op:
 679		badv = regs->regs[insn.reg3_format.rj];
 680		upper = regs->regs[insn.reg3_format.rk];
 681		break;
 682
 683	case ldgtb_op:
 684	case ldgth_op:
 685	case ldgtw_op:
 686	case ldgtd_op:
 687	case stgtb_op:
 688	case stgth_op:
 689	case stgtw_op:
 690	case stgtd_op:
 691	case fldgts_op:
 692	case fldgtd_op:
 693	case fstgts_op:
 694	case fstgtd_op:
 695		badv = regs->regs[insn.reg3_format.rj];
 696		lower = regs->regs[insn.reg3_format.rk];
 697		break;
 698	}
 699
 700	force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper);
 701
 702out:
 703	if (!pie)
 704		local_irq_disable();
 705
 706	irqentry_exit(regs, state);
 707	return;
 708
 709bad_era:
 710	/*
 711	 * Cannot pull out the instruction word, hence cannot provide more
 712	 * info than a regular SIGSEGV in this case.
 713	 */
 714	force_sig(SIGSEGV);
 715	goto out;
 716}
 717
 718asmlinkage void noinstr do_bp(struct pt_regs *regs)
 719{
 720	bool user = user_mode(regs);
 721	bool pie = regs_irqs_disabled(regs);
 722	unsigned int opcode, bcode;
 723	unsigned long era = exception_era(regs);
 724	irqentry_state_t state = irqentry_enter(regs);
 725
 726	if (!pie)
 727		local_irq_enable();
 728
 729	if (__get_inst(&opcode, (u32 *)era, user))
 730		goto out_sigsegv;
 731
 732	bcode = (opcode & 0x7fff);
 733
 734	/*
 735	 * notify the kprobe handlers, if instruction is likely to
 736	 * pertain to them.
 737	 */
 738	switch (bcode) {
 739	case BRK_KDB:
 740		if (kgdb_breakpoint_handler(regs))
 741			goto out;
 742		else
 743			break;
 744	case BRK_KPROBE_BP:
 745		if (kprobe_breakpoint_handler(regs))
 746			goto out;
 747		else
 748			break;
 749	case BRK_KPROBE_SSTEPBP:
 750		if (kprobe_singlestep_handler(regs))
 751			goto out;
 752		else
 753			break;
 754	case BRK_UPROBE_BP:
 755		if (uprobe_breakpoint_handler(regs))
 756			goto out;
 757		else
 758			break;
 759	case BRK_UPROBE_XOLBP:
 760		if (uprobe_singlestep_handler(regs))
 761			goto out;
 762		else
 763			break;
 764	default:
 765		current->thread.trap_nr = read_csr_excode();
 766		if (notify_die(DIE_TRAP, "Break", regs, bcode,
 767			       current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
 768			goto out;
 769		else
 770			break;
 771	}
 772
 773	switch (bcode) {
 774	case BRK_BUG:
 775		bug_handler(regs);
 776		break;
 777	case BRK_DIVZERO:
 778		die_if_kernel("Break instruction in kernel code", regs);
 779		force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era);
 780		break;
 781	case BRK_OVERFLOW:
 782		die_if_kernel("Break instruction in kernel code", regs);
 783		force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era);
 784		break;
 785	default:
 786		die_if_kernel("Break instruction in kernel code", regs);
 787		force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era);
 788		break;
 789	}
 790
 791out:
 792	if (!pie)
 793		local_irq_disable();
 794
 795	irqentry_exit(regs, state);
 796	return;
 797
 798out_sigsegv:
 799	force_sig(SIGSEGV);
 800	goto out;
 801}
 802
 803asmlinkage void noinstr do_watch(struct pt_regs *regs)
 804{
 805	irqentry_state_t state = irqentry_enter(regs);
 806
 807#ifndef CONFIG_HAVE_HW_BREAKPOINT
 808	pr_warn("Hardware watch point handler not implemented!\n");
 809#else
 810	if (kgdb_breakpoint_handler(regs))
 811		goto out;
 812
 813	if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) {
 814		int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1);
 815		unsigned long pc = instruction_pointer(regs);
 816		union loongarch_instruction *ip = (union loongarch_instruction *)pc;
 817
 818		if (llbit) {
 819			/*
 820			 * When the ll-sc combo is encountered, it is regarded as an single
 821			 * instruction. So don't clear llbit and reset CSR.FWPS.Skip until
 822			 * the llsc execution is completed.
 823			 */
 824			csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
 825			csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL);
 826			goto out;
 827		}
 828
 829		if (pc == current->thread.single_step) {
 830			/*
 831			 * Certain insns are occasionally not skipped when CSR.FWPS.Skip is
 832			 * set, such as fld.d/fst.d. So singlestep needs to compare whether
 833			 * the csr_era is equal to the value of singlestep which last time set.
 834			 */
 835			if (!is_self_loop_ins(ip, regs)) {
 836				/*
 837				 * Check if the given instruction the target pc is equal to the
 838				 * current pc, If yes, then we should not set the CSR.FWPS.SKIP
 839				 * bit to break the original instruction stream.
 840				 */
 841				csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
 842				goto out;
 843			}
 844		}
 845	} else {
 846		breakpoint_handler(regs);
 847		watchpoint_handler(regs);
 848	}
 849
 850	force_sig(SIGTRAP);
 851out:
 852#endif
 853	irqentry_exit(regs, state);
 854}
 855
 856asmlinkage void noinstr do_ri(struct pt_regs *regs)
 857{
 858	int status = SIGILL;
 859	unsigned int __maybe_unused opcode;
 860	unsigned int __user *era = (unsigned int __user *)exception_era(regs);
 861	irqentry_state_t state = irqentry_enter(regs);
 862
 863	local_irq_enable();
 864	current->thread.trap_nr = read_csr_excode();
 865
 866	if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
 867		       SIGILL) == NOTIFY_STOP)
 868		goto out;
 869
 870	die_if_kernel("Reserved instruction in kernel code", regs);
 871
 872	if (unlikely(get_user(opcode, era) < 0)) {
 873		status = SIGSEGV;
 874		current->thread.error_code = 1;
 875	}
 876
 877	force_sig(status);
 878
 879out:
 880	local_irq_disable();
 881	irqentry_exit(regs, state);
 882}
 883
 884static void init_restore_fp(void)
 885{
 886	if (!used_math()) {
 887		/* First time FP context user. */
 888		init_fpu();
 889	} else {
 890		/* This task has formerly used the FP context */
 891		if (!is_fpu_owner())
 892			own_fpu_inatomic(1);
 893	}
 894
 895	BUG_ON(!is_fp_enabled());
 896}
 897
 898static void init_restore_lsx(void)
 899{
 900	enable_lsx();
 901
 902	if (!thread_lsx_context_live()) {
 903		/* First time LSX context user */
 904		init_restore_fp();
 905		init_lsx_upper();
 906		set_thread_flag(TIF_LSX_CTX_LIVE);
 907	} else {
 908		if (!is_simd_owner()) {
 909			if (is_fpu_owner()) {
 910				restore_lsx_upper(current);
 911			} else {
 912				__own_fpu();
 913				restore_lsx(current);
 914			}
 915		}
 916	}
 917
 918	set_thread_flag(TIF_USEDSIMD);
 919
 920	BUG_ON(!is_fp_enabled());
 921	BUG_ON(!is_lsx_enabled());
 922}
 923
 924static void init_restore_lasx(void)
 925{
 926	enable_lasx();
 927
 928	if (!thread_lasx_context_live()) {
 929		/* First time LASX context user */
 930		init_restore_lsx();
 931		init_lasx_upper();
 932		set_thread_flag(TIF_LASX_CTX_LIVE);
 933	} else {
 934		if (is_fpu_owner() || is_simd_owner()) {
 935			init_restore_lsx();
 936			restore_lasx_upper(current);
 937		} else {
 938			__own_fpu();
 939			enable_lsx();
 940			restore_lasx(current);
 941		}
 942	}
 943
 944	set_thread_flag(TIF_USEDSIMD);
 945
 946	BUG_ON(!is_fp_enabled());
 947	BUG_ON(!is_lsx_enabled());
 948	BUG_ON(!is_lasx_enabled());
 949}
 950
 951asmlinkage void noinstr do_fpu(struct pt_regs *regs)
 952{
 953	irqentry_state_t state = irqentry_enter(regs);
 954
 955	local_irq_enable();
 956	die_if_kernel("do_fpu invoked from kernel context!", regs);
 957	BUG_ON(is_lsx_enabled());
 958	BUG_ON(is_lasx_enabled());
 959
 960	preempt_disable();
 961	init_restore_fp();
 962	preempt_enable();
 963
 964	local_irq_disable();
 965	irqentry_exit(regs, state);
 966}
 967
 968asmlinkage void noinstr do_lsx(struct pt_regs *regs)
 969{
 970	irqentry_state_t state = irqentry_enter(regs);
 971
 972	local_irq_enable();
 973	if (!cpu_has_lsx) {
 974		force_sig(SIGILL);
 975		goto out;
 976	}
 977
 978	die_if_kernel("do_lsx invoked from kernel context!", regs);
 979	BUG_ON(is_lasx_enabled());
 980
 981	preempt_disable();
 982	init_restore_lsx();
 983	preempt_enable();
 984
 985out:
 986	local_irq_disable();
 987	irqentry_exit(regs, state);
 988}
 989
 990asmlinkage void noinstr do_lasx(struct pt_regs *regs)
 991{
 992	irqentry_state_t state = irqentry_enter(regs);
 993
 994	local_irq_enable();
 995	if (!cpu_has_lasx) {
 996		force_sig(SIGILL);
 997		goto out;
 998	}
 999
1000	die_if_kernel("do_lasx invoked from kernel context!", regs);
1001
1002	preempt_disable();
1003	init_restore_lasx();
1004	preempt_enable();
1005
1006out:
1007	local_irq_disable();
1008	irqentry_exit(regs, state);
1009}
1010
1011static void init_restore_lbt(void)
1012{
1013	if (!thread_lbt_context_live()) {
1014		/* First time LBT context user */
1015		init_lbt();
1016		set_thread_flag(TIF_LBT_CTX_LIVE);
1017	} else {
1018		if (!is_lbt_owner())
1019			own_lbt_inatomic(1);
1020	}
1021
1022	BUG_ON(!is_lbt_enabled());
1023}
1024
1025asmlinkage void noinstr do_lbt(struct pt_regs *regs)
1026{
1027	bool pie = regs_irqs_disabled(regs);
1028	irqentry_state_t state = irqentry_enter(regs);
1029
1030	/*
1031	 * BTD (Binary Translation Disable exception) can be triggered
1032	 * during FP save/restore if TM (Top Mode) is on, which may
1033	 * cause irq_enable during 'switch_to'. To avoid this situation
1034	 * (including the user using 'MOVGR2GCSR' to turn on TM, which
1035	 * will not trigger the BTE), we need to check PRMD first.
1036	 */
1037	if (!pie)
1038		local_irq_enable();
1039
1040	if (!cpu_has_lbt) {
1041		force_sig(SIGILL);
1042		goto out;
1043	}
1044	BUG_ON(is_lbt_enabled());
1045
1046	preempt_disable();
1047	init_restore_lbt();
1048	preempt_enable();
1049
1050out:
1051	if (!pie)
1052		local_irq_disable();
1053
1054	irqentry_exit(regs, state);
1055}
1056
1057asmlinkage void noinstr do_reserved(struct pt_regs *regs)
1058{
1059	irqentry_state_t state = irqentry_enter(regs);
1060
1061	local_irq_enable();
1062	/*
1063	 * Game over - no way to handle this if it ever occurs.	Most probably
1064	 * caused by a fatal error after another hardware/software error.
1065	 */
1066	pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
1067		read_csr_excode(), current->pid, current->comm);
1068	die_if_kernel("do_reserved exception", regs);
1069	force_sig(SIGUNUSED);
1070
1071	local_irq_disable();
1072
1073	irqentry_exit(regs, state);
1074}
1075
1076asmlinkage void cache_parity_error(void)
1077{
1078	u32 merrctl = csr_read32(LOONGARCH_CSR_MERRCTL);
1079	unsigned long merrera = csr_read(LOONGARCH_CSR_MERRERA);
1080
1081	/* For the moment, report the problem and hang. */
1082	pr_err("Cache error exception:\n");
1083	pr_err("csr_merrctl == %08x\n", merrctl);
1084	pr_err("csr_merrera == %016lx\n", merrera);
1085	panic("Can't handle the cache error!");
1086}
1087
1088asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs)
1089{
1090	struct pt_regs *old_regs;
1091
1092	irq_enter_rcu();
1093	old_regs = set_irq_regs(regs);
1094	handle_arch_irq(regs);
1095	set_irq_regs(old_regs);
1096	irq_exit_rcu();
1097}
1098
1099asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp)
1100{
1101	register int cpu;
1102	register unsigned long stack;
1103	irqentry_state_t state = irqentry_enter(regs);
1104
1105	cpu = smp_processor_id();
1106
1107	if (on_irq_stack(cpu, sp))
1108		handle_loongarch_irq(regs);
1109	else {
1110		stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START;
1111
1112		/* Save task's sp on IRQ stack for unwinding */
1113		*(unsigned long *)stack = sp;
1114
1115		__asm__ __volatile__(
1116		"move	$s0, $sp		\n" /* Preserve sp */
1117		"move	$sp, %[stk]		\n" /* Switch stack */
1118		"move	$a0, %[regs]		\n"
1119		"bl	handle_loongarch_irq	\n"
1120		"move	$sp, $s0		\n" /* Restore sp */
1121		: /* No outputs */
1122		: [stk] "r" (stack), [regs] "r" (regs)
1123		: "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0",
1124		  "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8",
1125		  "memory");
1126	}
1127
1128	irqentry_exit(regs, state);
1129}
1130
1131unsigned long eentry;
1132unsigned long tlbrentry;
1133
1134long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
1135
1136static void configure_exception_vector(void)
1137{
1138	eentry    = (unsigned long)exception_handlers;
1139	tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE;
1140
1141	csr_write(eentry, LOONGARCH_CSR_EENTRY);
1142	csr_write(__pa(eentry), LOONGARCH_CSR_MERRENTRY);
1143	csr_write(__pa(tlbrentry), LOONGARCH_CSR_TLBRENTRY);
1144}
1145
1146void per_cpu_trap_init(int cpu)
1147{
1148	unsigned int i;
1149
1150	setup_vint_size(VECSIZE);
1151
1152	configure_exception_vector();
1153
1154	if (!cpu_data[cpu].asid_cache)
1155		cpu_data[cpu].asid_cache = asid_first_version(cpu);
1156
1157	mmgrab(&init_mm);
1158	current->active_mm = &init_mm;
1159	BUG_ON(current->mm);
1160	enter_lazy_tlb(&init_mm, current);
1161
1162	/* Initialise exception handlers */
1163	if (cpu == 0)
1164		for (i = 0; i < 64; i++)
1165			set_handler(i * VECSIZE, handle_reserved, VECSIZE);
1166
1167	tlb_init(cpu);
1168	cpu_cache_init();
1169}
1170
1171/* Install CPU exception handler */
1172void set_handler(unsigned long offset, void *addr, unsigned long size)
1173{
1174	memcpy((void *)(eentry + offset), addr, size);
1175	local_flush_icache_range(eentry + offset, eentry + offset + size);
1176}
1177
1178static const char panic_null_cerr[] =
1179	"Trying to set NULL cache error exception handler\n";
1180
1181/*
1182 * Install uncached CPU exception handler.
1183 * This is suitable only for the cache error exception which is the only
1184 * exception handler that is being run uncached.
1185 */
1186void set_merr_handler(unsigned long offset, void *addr, unsigned long size)
1187{
1188	unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry));
1189
1190	if (!addr)
1191		panic(panic_null_cerr);
1192
1193	memcpy((void *)(uncached_eentry + offset), addr, size);
1194}
1195
1196void __init trap_init(void)
1197{
1198	long i;
1199
1200	/* Set interrupt vector handler */
1201	for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++)
1202		set_handler(i * VECSIZE, handle_vint, VECSIZE);
1203
1204	/* Set exception vector handler */
1205	for (i = EXCCODE_ADE; i <= EXCCODE_BTDIS; i++)
1206		set_handler(i * VECSIZE, exception_table[i], VECSIZE);
1207
1208	cache_error_setup();
1209
1210	local_flush_icache_range(eentry, eentry + 0x400);
1211}