loongson.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Author: Huacai Chen <chenhuacai@loongson.cn>
  4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  5 */
  6
  7#ifndef __ASM_LOONGSON_H
  8#define __ASM_LOONGSON_H
  9
 10#include <linux/init.h>
 11#include <linux/io.h>
 12#include <linux/irq.h>
 13#include <linux/pci.h>
 14#include <asm/addrspace.h>
 15#include <asm/bootinfo.h>
 16
 17#define LOONGSON_REG(x) \
 18	(*(volatile u32 *)((char *)TO_UNCACHE(LOONGSON_REG_BASE) + (x)))
 19
 20#define LOONGSON_LIO_BASE	0x18000000
 21#define LOONGSON_LIO_SIZE	0x00100000	/* 1M */
 22#define LOONGSON_LIO_TOP	(LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1)
 23
 24#define LOONGSON_BOOT_BASE	0x1c000000
 25#define LOONGSON_BOOT_SIZE	0x02000000	/* 32M */
 26#define LOONGSON_BOOT_TOP	(LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
 27
 28#define LOONGSON_REG_BASE	0x1fe00000
 29#define LOONGSON_REG_SIZE	0x00100000	/* 1M */
 30#define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
 31
 32/* GPIO Regs - r/w */
 33
 34#define LOONGSON_GPIODATA		LOONGSON_REG(0x11c)
 35#define LOONGSON_GPIOIE			LOONGSON_REG(0x120)
 36#define LOONGSON_REG_GPIO_BASE          (LOONGSON_REG_BASE + 0x11c)
 37
 38#define MAX_PACKAGES 16
 39
 40#define xconf_readl(addr) readl(addr)
 41#define xconf_readq(addr) readq(addr)
 42
 43static inline void xconf_writel(u32 val, volatile void __iomem *addr)
 44{
 45	asm volatile (
 46	"	st.w	%[v], %[hw], 0	\n"
 47	"	ld.b	$zero, %[hw], 0	\n"
 48	:
 49	: [hw] "r" (addr), [v] "r" (val)
 50	);
 51}
 52
 53static inline void xconf_writeq(u64 val64, volatile void __iomem *addr)
 54{
 55	asm volatile (
 56	"	st.d	%[v], %[hw], 0	\n"
 57	"	ld.b	$zero, %[hw], 0	\n"
 58	:
 59	: [hw] "r" (addr),  [v] "r" (val64)
 60	);
 61}
 62
 63/* ============== LS7A registers =============== */
 64#define LS7A_PCH_REG_BASE		0x10000000UL
 65/* LPC regs */
 66#define LS7A_LPC_REG_BASE		(LS7A_PCH_REG_BASE + 0x00002000)
 67/* CHIPCFG regs */
 68#define LS7A_CHIPCFG_REG_BASE		(LS7A_PCH_REG_BASE + 0x00010000)
 69/* MISC reg base */
 70#define LS7A_MISC_REG_BASE		(LS7A_PCH_REG_BASE + 0x00080000)
 71/* ACPI regs */
 72#define LS7A_ACPI_REG_BASE		(LS7A_MISC_REG_BASE + 0x00050000)
 73/* RTC regs */
 74#define LS7A_RTC_REG_BASE		(LS7A_MISC_REG_BASE + 0x00050100)
 75
 76#define LS7A_DMA_CFG			(volatile void *)TO_UNCACHE(LS7A_CHIPCFG_REG_BASE + 0x041c)
 77#define LS7A_DMA_NODE_SHF		8
 78#define LS7A_DMA_NODE_MASK		0x1F00
 79
 80#define LS7A_INT_MASK_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x020)
 81#define LS7A_INT_EDGE_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x060)
 82#define LS7A_INT_CLEAR_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x080)
 83#define LS7A_INT_HTMSI_EN_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x040)
 84#define LS7A_INT_ROUTE_ENTRY_REG	(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x100)
 85#define LS7A_INT_HTMSI_VEC_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200)
 86#define LS7A_INT_STATUS_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3a0)
 87#define LS7A_INT_POL_REG		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3e0)
 88#define LS7A_LPC_INT_CTL		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2000)
 89#define LS7A_LPC_INT_ENA		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2004)
 90#define LS7A_LPC_INT_STS		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2008)
 91#define LS7A_LPC_INT_CLR		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200c)
 92#define LS7A_LPC_INT_POL		(volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2010)
 93
 94#define LS7A_PMCON_SOC_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x000)
 95#define LS7A_PMCON_RESUME_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x004)
 96#define LS7A_PMCON_RTC_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x008)
 97#define LS7A_PM1_EVT_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x00c)
 98#define LS7A_PM1_ENA_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x010)
 99#define LS7A_PM1_CNT_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x014)
100#define LS7A_PM1_TMR_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x018)
101#define LS7A_P_CNT_REG			(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x01c)
102#define LS7A_GPE0_STS_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x028)
103#define LS7A_GPE0_ENA_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x02c)
104#define LS7A_RST_CNT_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x030)
105#define LS7A_WD_SET_REG			(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x034)
106#define LS7A_WD_TIMER_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x038)
107#define LS7A_THSENS_CNT_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x04c)
108#define LS7A_GEN_RTC_1_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x050)
109#define LS7A_GEN_RTC_2_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x054)
110#define LS7A_DPM_CFG_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x400)
111#define LS7A_DPM_STS_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x404)
112#define LS7A_DPM_CNT_REG		(volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x408)
113
114typedef enum {
115	ACPI_PCI_HOTPLUG_STATUS	= 1 << 1,
116	ACPI_CPU_HOTPLUG_STATUS	= 1 << 2,
117	ACPI_MEM_HOTPLUG_STATUS	= 1 << 3,
118	ACPI_POWERBUTTON_STATUS	= 1 << 8,
119	ACPI_RTC_WAKE_STATUS	= 1 << 10,
120	ACPI_PCI_WAKE_STATUS	= 1 << 14,
121	ACPI_ANY_WAKE_STATUS	= 1 << 15,
122} AcpiEventStatusBits;
123
124#define HT1LO_OFFSET		0xe0000000000UL
125
126/* PCI Configuration Space Base */
127#define MCFG_EXT_PCICFG_BASE		0xefe00000000UL
128
129/* REG ACCESS*/
130#define ls7a_readb(addr)	(*(volatile unsigned char  *)TO_UNCACHE(addr))
131#define ls7a_readw(addr)	(*(volatile unsigned short *)TO_UNCACHE(addr))
132#define ls7a_readl(addr)	(*(volatile unsigned int   *)TO_UNCACHE(addr))
133#define ls7a_readq(addr)	(*(volatile unsigned long  *)TO_UNCACHE(addr))
134#define ls7a_writeb(val, addr)	*(volatile unsigned char  *)TO_UNCACHE(addr) = (val)
135#define ls7a_writew(val, addr)	*(volatile unsigned short *)TO_UNCACHE(addr) = (val)
136#define ls7a_writel(val, addr)	*(volatile unsigned int   *)TO_UNCACHE(addr) = (val)
137#define ls7a_writeq(val, addr)	*(volatile unsigned long  *)TO_UNCACHE(addr) = (val)
138
139void enable_gpe_wakeup(void);
140void enable_pci_wakeup(void);
141
142#endif /* __ASM_LOONGSON_H */