kvm_pch_pic.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (C) 2024 Loongson Technology Corporation Limited
 4 */
 5
 6#ifndef __ASM_KVM_PCH_PIC_H
 7#define __ASM_KVM_PCH_PIC_H
 8
 9#include <kvm/iodev.h>
10
11#define PCH_PIC_SIZE			0x3e8
12
13#define PCH_PIC_INT_ID_START		0x0
14#define PCH_PIC_INT_ID_END		0x7
15#define PCH_PIC_MASK_START		0x20
16#define PCH_PIC_MASK_END		0x27
17#define PCH_PIC_HTMSI_EN_START		0x40
18#define PCH_PIC_HTMSI_EN_END		0x47
19#define PCH_PIC_EDGE_START		0x60
20#define PCH_PIC_EDGE_END		0x67
21#define PCH_PIC_CLEAR_START		0x80
22#define PCH_PIC_CLEAR_END		0x87
23#define PCH_PIC_AUTO_CTRL0_START	0xc0
24#define PCH_PIC_AUTO_CTRL0_END		0xc7
25#define PCH_PIC_AUTO_CTRL1_START	0xe0
26#define PCH_PIC_AUTO_CTRL1_END		0xe7
27#define PCH_PIC_ROUTE_ENTRY_START	0x100
28#define PCH_PIC_ROUTE_ENTRY_END		0x13f
29#define PCH_PIC_HTMSI_VEC_START		0x200
30#define PCH_PIC_HTMSI_VEC_END		0x23f
31#define PCH_PIC_INT_IRR_START		0x380
32#define PCH_PIC_INT_IRR_END		0x38f
33#define PCH_PIC_INT_ISR_START		0x3a0
34#define PCH_PIC_INT_ISR_END		0x3af
35#define PCH_PIC_POLARITY_START		0x3e0
36#define PCH_PIC_POLARITY_END		0x3e7
37#define PCH_PIC_INT_ID_VAL		0x7UL
38#define PCH_PIC_INT_ID_VER		0x1UL
39
40union pch_pic_id {
41	struct {
42		uint8_t reserved_0[3];
43		uint8_t id;
44		uint8_t version;
45		uint8_t reserved_1;
46		uint8_t irq_num;
47		uint8_t reserved_2;
48	} desc;
49	uint64_t data;
50};
51
52struct loongarch_pch_pic {
53	spinlock_t lock;
54	struct kvm *kvm;
55	struct kvm_io_device device;
56	union pch_pic_id id;
57	uint64_t mask; /* 1:disable irq, 0:enable irq */
58	uint64_t htmsi_en; /* 1:msi */
59	uint64_t edge; /* 1:edge triggered, 0:level triggered */
60	uint64_t auto_ctrl0; /* only use default value 00b */
61	uint64_t auto_ctrl1; /* only use default value 00b */
62	uint64_t last_intirr; /* edge detection */
63	uint64_t irr; /* interrupt request register */
64	uint64_t isr; /* interrupt service register */
65	uint64_t polarity; /* 0: high level trigger, 1: low level trigger */
66	uint8_t  route_entry[64]; /* default value 0, route to int0: eiointc */
67	uint8_t  htmsi_vector[64]; /* irq route table for routing to eiointc */
68	uint64_t pch_pic_base;
69};
70
71int kvm_loongarch_register_pch_pic_device(void);
72void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level);
73void pch_msi_set_irq(struct kvm *kvm, int irq, int level);
74
75#endif /* __ASM_KVM_PCH_PIC_H */