cpu.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * cpu.h: Values of the PRID register used to match up
  4 *	  various LoongArch CPU types.
  5 *
  6 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  7 */
  8#ifndef _ASM_CPU_H
  9#define _ASM_CPU_H
 10
 11/*
 12 * As described in LoongArch specs from Loongson Technology, the PRID register
 13 * (CPUCFG.00) has the following layout:
 14 *
 15 * +---------------+----------------+------------+--------------------+
 16 * | Reserved      | Company ID     | Series ID  |  Product ID        |
 17 * +---------------+----------------+------------+--------------------+
 18 *  31		 24 23		  16 15	       12 11		     0
 19 */
 20
 21/*
 22 * Assigned Company values for bits 23:16 of the PRID register.
 23 */
 24
 25#define PRID_COMP_MASK		0xff0000
 26
 27#define PRID_COMP_LOONGSON	0x140000
 28
 29/*
 30 * Assigned Series ID values for bits 15:12 of the PRID register. In order
 31 * to detect a certain CPU type exactly eventually additional registers may
 32 * need to be examined.
 33 */
 34
 35#define PRID_SERIES_MASK	0xf000
 36
 37#define PRID_SERIES_LA132	0x8000  /* Loongson 32bit */
 38#define PRID_SERIES_LA264	0xa000  /* Loongson 64bit, 2-issue */
 39#define PRID_SERIES_LA364	0xb000  /* Loongson 64bit, 3-issue */
 40#define PRID_SERIES_LA464	0xc000  /* Loongson 64bit, 4-issue */
 41#define PRID_SERIES_LA664	0xd000  /* Loongson 64bit, 6-issue */
 42
 43/*
 44 * Particular Product ID values for bits 11:0 of the PRID register.
 45 */
 46
 47#define PRID_PRODUCT_MASK	0x0fff
 48
 49#if !defined(__ASSEMBLER__)
 50
 51enum cpu_type_enum {
 52	CPU_UNKNOWN,
 53	CPU_LOONGSON32,
 54	CPU_LOONGSON64,
 55	CPU_LAST
 56};
 57
 58static inline char *id_to_core_name(unsigned int id)
 59{
 60	if ((id & PRID_COMP_MASK) != PRID_COMP_LOONGSON)
 61		return "Unknown";
 62
 63	switch (id & PRID_SERIES_MASK) {
 64	case PRID_SERIES_LA132:
 65		return "LA132";
 66	case PRID_SERIES_LA264:
 67		return "LA264";
 68	case PRID_SERIES_LA364:
 69		return "LA364";
 70	case PRID_SERIES_LA464:
 71		return "LA464";
 72	case PRID_SERIES_LA664:
 73		return "LA664";
 74	default:
 75		return "Unknown";
 76	}
 77}
 78
 79#endif /* !__ASSEMBLER__ */
 80
 81/*
 82 * ISA Level encodings
 83 *
 84 */
 85
 86#define LOONGARCH_CPU_ISA_LA32R 0x00000001
 87#define LOONGARCH_CPU_ISA_LA32S 0x00000002
 88#define LOONGARCH_CPU_ISA_LA64  0x00000004
 89
 90#define LOONGARCH_CPU_ISA_32BIT (LOONGARCH_CPU_ISA_LA32R | LOONGARCH_CPU_ISA_LA32S)
 91#define LOONGARCH_CPU_ISA_64BIT LOONGARCH_CPU_ISA_LA64
 92
 93/*
 94 * CPU Option encodings
 95 */
 96#define CPU_FEATURE_CPUCFG		0	/* CPU has CPUCFG */
 97#define CPU_FEATURE_LAM			1	/* CPU has Atomic instructions */
 98#define CPU_FEATURE_UAL			2	/* CPU supports unaligned access */
 99#define CPU_FEATURE_FPU			3	/* CPU has FPU */
100#define CPU_FEATURE_LSX			4	/* CPU has LSX (128-bit SIMD) */
101#define CPU_FEATURE_LASX		5	/* CPU has LASX (256-bit SIMD) */
102#define CPU_FEATURE_CRC32		6	/* CPU has CRC32 instructions */
103#define CPU_FEATURE_COMPLEX		7	/* CPU has Complex instructions */
104#define CPU_FEATURE_CRYPTO		8	/* CPU has Crypto instructions */
105#define CPU_FEATURE_LVZ			9	/* CPU has Virtualization extension */
106#define CPU_FEATURE_LBT_X86		10	/* CPU has X86 Binary Translation */
107#define CPU_FEATURE_LBT_ARM		11	/* CPU has ARM Binary Translation */
108#define CPU_FEATURE_LBT_MIPS		12	/* CPU has MIPS Binary Translation */
109#define CPU_FEATURE_TLB			13	/* CPU has TLB */
110#define CPU_FEATURE_CSR			14	/* CPU has CSR */
111#define CPU_FEATURE_IOCSR		15	/* CPU has IOCSR */
112#define CPU_FEATURE_WATCH		16	/* CPU has watchpoint registers */
113#define CPU_FEATURE_VINT		17	/* CPU has vectored interrupts */
114#define CPU_FEATURE_CSRIPI		18	/* CPU has CSR-IPI */
115#define CPU_FEATURE_EXTIOI		19	/* CPU has EXT-IOI */
116#define CPU_FEATURE_PREFETCH		20	/* CPU has prefetch instructions */
117#define CPU_FEATURE_PMP			21	/* CPU has perfermance counter */
118#define CPU_FEATURE_SCALEFREQ		22	/* CPU supports cpufreq scaling */
119#define CPU_FEATURE_FLATMODE		23	/* CPU has flat mode */
120#define CPU_FEATURE_EIODECODE		24	/* CPU has EXTIOI interrupt pin decode mode */
121#define CPU_FEATURE_GUESTID		25	/* CPU has GuestID feature */
122#define CPU_FEATURE_HYPERVISOR		26	/* CPU has hypervisor (running in VM) */
123#define CPU_FEATURE_PTW			27	/* CPU has hardware page table walker */
124#define CPU_FEATURE_LSPW		28	/* CPU has LSPW (lddir/ldpte instructions) */
125#define CPU_FEATURE_MSGINT		29	/* CPU has MSG interrupt */
126#define CPU_FEATURE_AVECINT		30	/* CPU has AVEC interrupt */
127#define CPU_FEATURE_REDIRECTINT		31	/* CPU has interrupt remapping */
128
129#define LOONGARCH_CPU_CPUCFG		BIT_ULL(CPU_FEATURE_CPUCFG)
130#define LOONGARCH_CPU_LAM		BIT_ULL(CPU_FEATURE_LAM)
131#define LOONGARCH_CPU_UAL		BIT_ULL(CPU_FEATURE_UAL)
132#define LOONGARCH_CPU_FPU		BIT_ULL(CPU_FEATURE_FPU)
133#define LOONGARCH_CPU_LSX		BIT_ULL(CPU_FEATURE_LSX)
134#define LOONGARCH_CPU_LASX		BIT_ULL(CPU_FEATURE_LASX)
135#define LOONGARCH_CPU_CRC32		BIT_ULL(CPU_FEATURE_CRC32)
136#define LOONGARCH_CPU_COMPLEX		BIT_ULL(CPU_FEATURE_COMPLEX)
137#define LOONGARCH_CPU_CRYPTO		BIT_ULL(CPU_FEATURE_CRYPTO)
138#define LOONGARCH_CPU_LVZ		BIT_ULL(CPU_FEATURE_LVZ)
139#define LOONGARCH_CPU_LBT_X86		BIT_ULL(CPU_FEATURE_LBT_X86)
140#define LOONGARCH_CPU_LBT_ARM		BIT_ULL(CPU_FEATURE_LBT_ARM)
141#define LOONGARCH_CPU_LBT_MIPS		BIT_ULL(CPU_FEATURE_LBT_MIPS)
142#define LOONGARCH_CPU_TLB		BIT_ULL(CPU_FEATURE_TLB)
143#define LOONGARCH_CPU_IOCSR		BIT_ULL(CPU_FEATURE_IOCSR)
144#define LOONGARCH_CPU_CSR		BIT_ULL(CPU_FEATURE_CSR)
145#define LOONGARCH_CPU_WATCH		BIT_ULL(CPU_FEATURE_WATCH)
146#define LOONGARCH_CPU_VINT		BIT_ULL(CPU_FEATURE_VINT)
147#define LOONGARCH_CPU_CSRIPI		BIT_ULL(CPU_FEATURE_CSRIPI)
148#define LOONGARCH_CPU_EXTIOI		BIT_ULL(CPU_FEATURE_EXTIOI)
149#define LOONGARCH_CPU_PREFETCH		BIT_ULL(CPU_FEATURE_PREFETCH)
150#define LOONGARCH_CPU_PMP		BIT_ULL(CPU_FEATURE_PMP)
151#define LOONGARCH_CPU_SCALEFREQ		BIT_ULL(CPU_FEATURE_SCALEFREQ)
152#define LOONGARCH_CPU_FLATMODE		BIT_ULL(CPU_FEATURE_FLATMODE)
153#define LOONGARCH_CPU_EIODECODE		BIT_ULL(CPU_FEATURE_EIODECODE)
154#define LOONGARCH_CPU_GUESTID		BIT_ULL(CPU_FEATURE_GUESTID)
155#define LOONGARCH_CPU_HYPERVISOR	BIT_ULL(CPU_FEATURE_HYPERVISOR)
156#define LOONGARCH_CPU_PTW		BIT_ULL(CPU_FEATURE_PTW)
157#define LOONGARCH_CPU_LSPW		BIT_ULL(CPU_FEATURE_LSPW)
158#define LOONGARCH_CPU_MSGINT		BIT_ULL(CPU_FEATURE_MSGINT)
159#define LOONGARCH_CPU_AVECINT		BIT_ULL(CPU_FEATURE_AVECINT)
160#define LOONGARCH_CPU_REDIRECTINT	BIT_ULL(CPU_FEATURE_REDIRECTINT)
161
162#endif /* _ASM_CPU_H */