addrspace.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4 *
  5 * Derived from MIPS:
  6 * Copyright (C) 1996, 99 Ralf Baechle
  7 * Copyright (C) 2000, 2002  Maciej W. Rozycki
  8 * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
  9 */
 10#ifndef _ASM_ADDRSPACE_H
 11#define _ASM_ADDRSPACE_H
 12
 13#include <linux/const.h>
 14#include <linux/sizes.h>
 15
 16#include <asm/loongarch.h>
 17
 18/*
 19 * This gives the physical RAM offset.
 20 */
 21#ifndef __ASSEMBLER__
 22#ifndef PHYS_OFFSET
 23#define PHYS_OFFSET	_UL(0)
 24#endif
 25extern unsigned long vm_map_base;
 26#endif /* __ASSEMBLER__ */
 27
 28#ifndef IO_BASE
 29#define IO_BASE			CSR_DMW0_BASE
 30#endif
 31
 32#ifndef CACHE_BASE
 33#define CACHE_BASE		CSR_DMW1_BASE
 34#endif
 35
 36#ifndef UNCACHE_BASE
 37#define UNCACHE_BASE		CSR_DMW0_BASE
 38#endif
 39
 40#ifndef WRITECOMBINE_BASE
 41#ifdef CONFIG_32BIT
 42#define WRITECOMBINE_BASE	CSR_DMW0_BASE
 43#else
 44#define WRITECOMBINE_BASE	CSR_DMW2_BASE
 45#endif
 46#endif
 47
 48#ifdef CONFIG_32BIT
 49#define DMW_PABITS	29
 50#define TO_PHYS_MASK	((_UL(1) << _UL(DMW_PABITS)) - 1)
 51#else
 52#define DMW_PABITS	48
 53#define TO_PHYS_MASK	((_ULL(1) << _ULL(DMW_PABITS)) - 1)
 54#endif
 55
 56/*
 57 * Memory above this physical address will be considered highmem.
 58 */
 59#ifndef HIGHMEM_START
 60#define HIGHMEM_START		(_UL(1) << _UL(DMW_PABITS))
 61#endif
 62
 63#define TO_PHYS(x)		(		((x) & TO_PHYS_MASK))
 64#define TO_CACHE(x)		(CACHE_BASE   |	((x) & TO_PHYS_MASK))
 65#define TO_UNCACHE(x)		(UNCACHE_BASE |	((x) & TO_PHYS_MASK))
 66
 67/*
 68 * This handles the memory map.
 69 */
 70#ifndef PAGE_OFFSET
 71#define PAGE_OFFSET		(CACHE_BASE + PHYS_OFFSET)
 72#endif
 73
 74#ifndef FIXADDR_TOP
 75#define FIXADDR_TOP		((unsigned long)(long)(int)0xfffe0000)
 76#endif
 77
 78#ifdef __ASSEMBLER__
 79#define _ATYPE_
 80#define _ATYPE32_
 81#define _ATYPE64_
 82#else
 83#define _ATYPE_		__PTRDIFF_TYPE__
 84#define _ATYPE32_	int
 85#define _ATYPE64_	__s64
 86#endif
 87
 88#ifdef CONFIG_64BIT
 89#define _CONST64_(x)	_UL(x)
 90#else
 91#define _CONST64_(x)	_ULL(x)
 92#endif
 93
 94/*
 95 *  32/64-bit LoongArch address spaces
 96 */
 97#ifdef __ASSEMBLER__
 98#define _ACAST32_
 99#define _ACAST64_
100#else
101#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
102#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
103#endif
104
105#ifdef CONFIG_32BIT
106
107#define UVRANGE			0x00000000
108#define KPRANGE0		0x80000000
109#define KPRANGE1		0xa0000000
110#define KVRANGE			0xc0000000
111
112#else
113
114#define XUVRANGE		_CONST64_(0x0000000000000000)
115#define XSPRANGE		_CONST64_(0x4000000000000000)
116#define XKPRANGE		_CONST64_(0x8000000000000000)
117#define XKVRANGE		_CONST64_(0xc000000000000000)
118
119#endif
120
121/*
122 * Returns the physical address of a KPRANGEx / XKPRANGE address
123 */
124#ifdef CONFIG_32BIT
125#define PHYSADDR(a)		((_ACAST32_(a)) & TO_PHYS_MASK)
126#else
127#define PHYSADDR(a)		((_ACAST64_(a)) & TO_PHYS_MASK)
128#endif
129
130/*
131 * On LoongArch, I/O ports mappring is following:
132 *
133 *              |         ....          |
134 *              |-----------------------|
135 *              | pci io ports(16K~32M) |
136 *              |-----------------------|
137 *              | isa io ports(0  ~16K) |
138 * PCI_IOBASE ->|-----------------------|
139 *              |         ....          |
140 */
141#define PCI_IOBASE	((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
142#define PCI_IOSIZE	SZ_32M
143#define ISA_IOSIZE	SZ_16K
144#define IO_SPACE_LIMIT	(PCI_IOSIZE - 1)
145
146#define PHYS_LINK_KADDR	PHYSADDR(VMLINUX_LOAD_ADDRESS)
147
148#endif /* _ASM_ADDRSPACE_H */