io.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2
 3#ifndef __ASM_CSKY_IO_H
 4#define __ASM_CSKY_IO_H
 5
 6#include <linux/pgtable.h>
 7#include <linux/types.h>
 8
 9/*
10 * I/O memory access primitives. Reads are ordered relative to any
11 * following Normal memory access. Writes are ordered relative to any prior
12 * Normal memory access.
13 *
14 * For CACHEV1 (807, 810), store instruction could fast retire, so we need
15 * another mb() to prevent st fast retire.
16 *
17 * For CACHEV2 (860), store instruction with PAGE_ATTR_NO_BUFFERABLE won't
18 * fast retire.
19 */
20#define readb(c)		({ u8  __v = readb_relaxed(c); rmb(); __v; })
21#define readw(c)		({ u16 __v = readw_relaxed(c); rmb(); __v; })
22#define readl(c)		({ u32 __v = readl_relaxed(c); rmb(); __v; })
23
24#ifdef CONFIG_CPU_HAS_CACHEV2
25#define writeb(v,c)		({ wmb(); writeb_relaxed((v),(c)); })
26#define writew(v,c)		({ wmb(); writew_relaxed((v),(c)); })
27#define writel(v,c)		({ wmb(); writel_relaxed((v),(c)); })
28#else
29#define writeb(v,c)		({ wmb(); writeb_relaxed((v),(c)); mb(); })
30#define writew(v,c)		({ wmb(); writew_relaxed((v),(c)); mb(); })
31#define writel(v,c)		({ wmb(); writel_relaxed((v),(c)); mb(); })
32#endif
33
34/*
35 * I/O memory mapping functions.
36 */
37#define ioremap_wc(addr, size) \
38	ioremap_prot((addr), (size), \
39		__pgprot((_PAGE_IOREMAP & ~_CACHE_MASK) | _CACHE_UNCACHED))
40
41#include <asm-generic/io.h>
42
43#endif /* __ASM_CSKY_IO_H */