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cpufeature.c
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linux-6.19.14/arch/arm64/kernel/cpufeature.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63#define pr_fmt(fmt) "CPU features: " fmt 64 65#include <linux/bsearch.h> 66#include <linux/cpumask.h> 67#include <linux/crash_dump.h> 68#include <linux/kstrtox.h> 69#include <linux/sort.h> 70#include <linux/stop_machine.h> 71#include <linux/sysfs.h> 72#include <linux/types.h> 73#include <linux/minmax.h> 74#include <linux/mm.h> 75#include <linux/cpu.h> 76#include <linux/kasan.h> 77#include <linux/percpu.h> 78#include <linux/sched/isolation.h> 79 80#include <asm/cpu.h> 81#include <asm/cpufeature.h> 82#include <asm/cpu_ops.h> 83#include <asm/fpsimd.h> 84#include <asm/hwcap.h> 85#include <asm/insn.h> 86#include <asm/kvm_host.h> 87#include <asm/mmu.h> 88#include <asm/mmu_context.h> 89#include <asm/mte.h> 90#include <asm/hypervisor.h> 91#include <asm/processor.h> 92#include <asm/smp.h> 93#include <asm/sysreg.h> 94#include <asm/traps.h> 95#include <asm/vectors.h> 96#include <asm/virt.h> 97 98#include <asm/spectre.h> 99/* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 100static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 101 102#ifdef CONFIG_COMPAT 103#define COMPAT_ELF_HWCAP_DEFAULT \ 104 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 105 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 106 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 107 COMPAT_HWCAP_LPAE) 108unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 109unsigned int compat_elf_hwcap2 __read_mostly; 110unsigned int compat_elf_hwcap3 __read_mostly; 111#endif 112 113DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 114EXPORT_SYMBOL(system_cpucaps); 115static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 116 117DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 118 119/* 120 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 121 * ends up in the .bss section where it is initialized in early_map_kernel() 122 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 123 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 124 * may end up generating an incorrect idmap page table attributes. 125 */ 126bool arm64_use_ng_mappings __read_mostly = false; 127EXPORT_SYMBOL(arm64_use_ng_mappings); 128 129DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 130 131/* 132 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 133 * support it? 134 */ 135static bool __read_mostly allow_mismatched_32bit_el0; 136 137/* 138 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 139 * seen at least one CPU capable of 32-bit EL0. 140 */ 141DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 142 143/* 144 * Mask of CPUs supporting 32-bit EL0. 145 * Only valid if arm64_mismatched_32bit_el0 is enabled. 146 */ 147static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 148 149void dump_cpu_features(void) 150{ 151 /* file-wide pr_fmt adds "CPU features: " prefix */ 152 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 153} 154 155#define __ARM64_MAX_POSITIVE(reg, field) \ 156 ((reg##_##field##_SIGNED ? \ 157 BIT(reg##_##field##_WIDTH - 1) : \ 158 BIT(reg##_##field##_WIDTH)) - 1) 159 160#define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 161 162#define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 163 .sys_reg = SYS_##reg, \ 164 .field_pos = reg##_##field##_SHIFT, \ 165 .field_width = reg##_##field##_WIDTH, \ 166 .sign = reg##_##field##_SIGNED, \ 167 .min_field_value = min_value, \ 168 .max_field_value = max_value, 169 170/* 171 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 172 * an implicit maximum that depends on the sign-ess of the field. 173 * 174 * An unsigned field will be capped at all ones, while a signed field 175 * will be limited to the positive half only. 176 */ 177#define ARM64_CPUID_FIELDS(reg, field, min_value) \ 178 __ARM64_CPUID_FIELDS(reg, field, \ 179 SYS_FIELD_VALUE(reg, field, min_value), \ 180 __ARM64_MAX_POSITIVE(reg, field)) 181 182/* 183 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 184 * implicit minimal value to max_value. This should be used when 185 * matching a non-implemented property. 186 */ 187#define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 188 __ARM64_CPUID_FIELDS(reg, field, \ 189 __ARM64_MIN_NEGATIVE(reg, field), \ 190 SYS_FIELD_VALUE(reg, field, max_value)) 191 192#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 193 { \ 194 .sign = SIGNED, \ 195 .visible = VISIBLE, \ 196 .strict = STRICT, \ 197 .type = TYPE, \ 198 .shift = SHIFT, \ 199 .width = WIDTH, \ 200 .safe_val = SAFE_VAL, \ 201 } 202 203/* Define a feature with unsigned values */ 204#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 205 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 206 207/* Define a feature with a signed value */ 208#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 209 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 210 211#define ARM64_FTR_END \ 212 { \ 213 .width = 0, \ 214 } 215 216static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 217 218static bool __system_matches_cap(unsigned int n); 219 220/* 221 * NOTE: Any changes to the visibility of features should be kept in 222 * sync with the documentation of the CPU feature register ABI. 223 */ 224static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 239 ARM64_FTR_END, 240}; 241 242static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 260 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 262 ARM64_FTR_END, 263}; 264 265static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 273 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 278 ARM64_FTR_END, 279}; 280 281static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 282 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 285 ARM64_FTR_END, 286}; 287 288static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 296 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 299 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 300 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 305 ARM64_FTR_END, 306}; 307 308static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 311 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 312 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 319 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 322 ARM64_FTR_END, 323}; 324 325static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 328 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 329 ARM64_FTR_END, 330}; 331 332static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 333 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 334 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 336 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 338 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 354 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 356 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 357 ARM64_FTR_END, 358}; 359 360static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 362 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 364 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 366 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 404 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 406 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 407 ARM64_FTR_END, 408}; 409 410static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 419 ARM64_FTR_END, 420}; 421 422static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 426 /* 427 * Page size not being supported at Stage-2 is not fatal. You 428 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 429 * your favourite nesting hypervisor. 430 * 431 * There is a small corner case where the hypervisor explicitly 432 * advertises a given granule size at Stage-2 (value 2) on some 433 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 434 * vCPUs. Although this is not forbidden by the architecture, it 435 * indicates that the hypervisor is being silly (or buggy). 436 * 437 * We make no effort to cope with this and pretend that if these 438 * fields are inconsistent across vCPUs, then it isn't worth 439 * trying to bring KVM up. 440 */ 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 444 /* 445 * We already refuse to boot CPUs that don't support our configured 446 * page size, so we can only detect mismatches for a page size other 447 * than the one we're currently using. Unfortunately, SoCs like this 448 * exist in the wild so, even though we don't like it, we'll have to go 449 * along with it and treat them as non-strict. 450 */ 451 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 452 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 454 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 456 /* Linux shouldn't care about secure memory */ 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 460 /* 461 * Differing PARange is fine as long as all peripherals and memory are mapped 462 * within the minimum PARange of all CPUs 463 */ 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 465 ARM64_FTR_END, 466}; 467 468static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 483 ARM64_FTR_END, 484}; 485 486static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 502 ARM64_FTR_END, 503}; 504 505static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 506 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 507 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 511 ARM64_FTR_END, 512}; 513 514static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 515 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 517 ARM64_FTR_END, 518}; 519 520static const struct arm64_ftr_bits ftr_ctr[] = { 521 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 522 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 523 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 524 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 527 /* 528 * Linux can handle differing I-cache policies. Userspace JITs will 529 * make use of *minLine. 530 * If we have differing I-cache policies, report it as the weakest - VIPT. 531 */ 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 534 ARM64_FTR_END, 535}; 536 537static struct arm64_ftr_override __ro_after_init no_override = { }; 538 539struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 540 .name = "SYS_CTR_EL0", 541 .ftr_bits = ftr_ctr, 542 .override = &no_override, 543}; 544 545static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 546 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 551 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 554 ARM64_FTR_END, 555}; 556 557static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 558 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 563 /* 564 * We can instantiate multiple PMU instances with different levels 565 * of support. 566 */ 567 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 569 ARM64_FTR_END, 570}; 571 572static const struct arm64_ftr_bits ftr_mvfr0[] = { 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 581 ARM64_FTR_END, 582}; 583 584static const struct arm64_ftr_bits ftr_mvfr1[] = { 585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 590 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 593 ARM64_FTR_END, 594}; 595 596static const struct arm64_ftr_bits ftr_mvfr2[] = { 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 599 ARM64_FTR_END, 600}; 601 602static const struct arm64_ftr_bits ftr_dczid[] = { 603 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 604 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 605 ARM64_FTR_END, 606}; 607 608static const struct arm64_ftr_bits ftr_gmid[] = { 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 610 ARM64_FTR_END, 611}; 612 613static const struct arm64_ftr_bits ftr_id_isar0[] = { 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 621 ARM64_FTR_END, 622}; 623 624static const struct arm64_ftr_bits ftr_id_isar5[] = { 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 631 ARM64_FTR_END, 632}; 633 634static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 642 643 /* 644 * SpecSEI = 1 indicates that the PE might generate an SError on an 645 * external abort on speculative read. It is safe to assume that an 646 * SError might be generated than it will not be. Hence it has been 647 * classified as FTR_HIGHER_SAFE. 648 */ 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 650 ARM64_FTR_END, 651}; 652 653static const struct arm64_ftr_bits ftr_id_isar4[] = { 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 662 ARM64_FTR_END, 663}; 664 665static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 667 ARM64_FTR_END, 668}; 669 670static const struct arm64_ftr_bits ftr_id_isar6[] = { 671 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 673 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 674 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 675 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 678 ARM64_FTR_END, 679}; 680 681static const struct arm64_ftr_bits ftr_id_pfr0[] = { 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 688 ARM64_FTR_END, 689}; 690 691static const struct arm64_ftr_bits ftr_id_pfr1[] = { 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 700 ARM64_FTR_END, 701}; 702 703static const struct arm64_ftr_bits ftr_id_pfr2[] = { 704 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 706 ARM64_FTR_END, 707}; 708 709static const struct arm64_ftr_bits ftr_id_dfr0[] = { 710 /* [31:28] TraceFilt */ 711 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 715 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 716 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 717 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 718 ARM64_FTR_END, 719}; 720 721static const struct arm64_ftr_bits ftr_id_dfr1[] = { 722 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 723 ARM64_FTR_END, 724}; 725 726static const struct arm64_ftr_bits ftr_mpamidr[] = { 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 730 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 731 ARM64_FTR_END, 732}; 733 734/* 735 * Common ftr bits for a 32bit register with all hidden, strict 736 * attributes, with 4bit feature fields and a default safe value of 737 * 0. Covers the following 32bit registers: 738 * id_isar[1-3], id_mmfr[1-3] 739 */ 740static const struct arm64_ftr_bits ftr_generic_32bits[] = { 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 743 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 744 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 745 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 746 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 747 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 748 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 749 ARM64_FTR_END, 750}; 751 752/* Table for a single 32bit feature value */ 753static const struct arm64_ftr_bits ftr_single32[] = { 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 755 ARM64_FTR_END, 756}; 757 758static const struct arm64_ftr_bits ftr_raz[] = { 759 ARM64_FTR_END, 760}; 761 762#define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 763 .sys_id = id, \ 764 .reg = &(struct arm64_ftr_reg){ \ 765 .name = id_str, \ 766 .override = (ovr), \ 767 .ftr_bits = &((table)[0]), \ 768 }} 769 770#define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 771 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 772 773#define ARM64_FTR_REG(id, table) \ 774 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 775 776struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 777struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 778struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 779struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 780struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 781struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 782struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 783struct arm64_ftr_override __read_mostly id_aa64isar1_override; 784struct arm64_ftr_override __read_mostly id_aa64isar2_override; 785 786struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 787 788static const struct __ftr_reg_entry { 789 u32 sys_id; 790 struct arm64_ftr_reg *reg; 791} arm64_ftr_regs[] = { 792 793 /* Op1 = 0, CRn = 0, CRm = 1 */ 794 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 795 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 796 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 797 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 798 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 799 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 800 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 801 802 /* Op1 = 0, CRn = 0, CRm = 2 */ 803 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 804 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 805 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 806 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 807 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 808 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 809 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 810 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 811 812 /* Op1 = 0, CRn = 0, CRm = 3 */ 813 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 814 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 815 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 816 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 817 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 818 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 819 820 /* Op1 = 0, CRn = 0, CRm = 4 */ 821 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 822 &id_aa64pfr0_override), 823 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 824 &id_aa64pfr1_override), 825 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 826 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 827 &id_aa64zfr0_override), 828 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 829 &id_aa64smfr0_override), 830 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 831 832 /* Op1 = 0, CRn = 0, CRm = 5 */ 833 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 834 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 835 836 /* Op1 = 0, CRn = 0, CRm = 6 */ 837 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 838 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 839 &id_aa64isar1_override), 840 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 841 &id_aa64isar2_override), 842 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 843 844 /* Op1 = 0, CRn = 0, CRm = 7 */ 845 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 846 &id_aa64mmfr0_override), 847 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 848 &id_aa64mmfr1_override), 849 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 850 &id_aa64mmfr2_override), 851 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 852 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 853 854 /* Op1 = 0, CRn = 10, CRm = 4 */ 855 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 856 857 /* Op1 = 1, CRn = 0, CRm = 0 */ 858 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 859 860 /* Op1 = 3, CRn = 0, CRm = 0 */ 861 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 862 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 863 864 /* Op1 = 3, CRn = 14, CRm = 0 */ 865 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 866}; 867 868static int search_cmp_ftr_reg(const void *id, const void *regp) 869{ 870 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 871} 872 873/* 874 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 875 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 876 * ascending order of sys_id, we use binary search to find a matching 877 * entry. 878 * 879 * returns - Upon success, matching ftr_reg entry for id. 880 * - NULL on failure. It is upto the caller to decide 881 * the impact of a failure. 882 */ 883static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 884{ 885 const struct __ftr_reg_entry *ret; 886 887 ret = bsearch((const void *)(unsigned long)sys_id, 888 arm64_ftr_regs, 889 ARRAY_SIZE(arm64_ftr_regs), 890 sizeof(arm64_ftr_regs[0]), 891 search_cmp_ftr_reg); 892 if (ret) 893 return ret->reg; 894 return NULL; 895} 896 897/* 898 * get_arm64_ftr_reg - Looks up a feature register entry using 899 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 900 * 901 * returns - Upon success, matching ftr_reg entry for id. 902 * - NULL on failure but with an WARN_ON(). 903 */ 904struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 905{ 906 struct arm64_ftr_reg *reg; 907 908 reg = get_arm64_ftr_reg_nowarn(sys_id); 909 910 /* 911 * Requesting a non-existent register search is an error. Warn 912 * and let the caller handle it. 913 */ 914 WARN_ON(!reg); 915 return reg; 916} 917 918static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 919 s64 ftr_val) 920{ 921 u64 mask = arm64_ftr_mask(ftrp); 922 923 reg &= ~mask; 924 reg |= (ftr_val << ftrp->shift) & mask; 925 return reg; 926} 927 928s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 929 s64 cur) 930{ 931 s64 ret = 0; 932 933 switch (ftrp->type) { 934 case FTR_EXACT: 935 ret = ftrp->safe_val; 936 break; 937 case FTR_LOWER_SAFE: 938 ret = min(new, cur); 939 break; 940 case FTR_HIGHER_OR_ZERO_SAFE: 941 if (!cur || !new) 942 break; 943 fallthrough; 944 case FTR_HIGHER_SAFE: 945 ret = max(new, cur); 946 break; 947 default: 948 BUG(); 949 } 950 951 return ret; 952} 953 954static void __init sort_ftr_regs(void) 955{ 956 unsigned int i; 957 958 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 959 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 960 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 961 unsigned int j = 0; 962 963 /* 964 * Features here must be sorted in descending order with respect 965 * to their shift values and should not overlap with each other. 966 */ 967 for (; ftr_bits->width != 0; ftr_bits++, j++) { 968 unsigned int width = ftr_reg->ftr_bits[j].width; 969 unsigned int shift = ftr_reg->ftr_bits[j].shift; 970 unsigned int prev_shift; 971 972 WARN((shift + width) > 64, 973 "%s has invalid feature at shift %d\n", 974 ftr_reg->name, shift); 975 976 /* 977 * Skip the first feature. There is nothing to 978 * compare against for now. 979 */ 980 if (j == 0) 981 continue; 982 983 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 984 WARN((shift + width) > prev_shift, 985 "%s has feature overlap at shift %d\n", 986 ftr_reg->name, shift); 987 } 988 989 /* 990 * Skip the first register. There is nothing to 991 * compare against for now. 992 */ 993 if (i == 0) 994 continue; 995 /* 996 * Registers here must be sorted in ascending order with respect 997 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 998 * to work correctly. 999 */ 1000 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1001 } 1002} 1003 1004/* 1005 * Initialise the CPU feature register from Boot CPU values. 1006 * Also initialises the strict_mask for the register. 1007 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1008 * RES0 for the system-wide value, and must strictly match. 1009 */ 1010static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1011{ 1012 u64 val = 0; 1013 u64 strict_mask = ~0x0ULL; 1014 u64 user_mask = 0; 1015 u64 valid_mask = 0; 1016 1017 const struct arm64_ftr_bits *ftrp; 1018 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1019 1020 if (!reg) 1021 return; 1022 1023 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1024 u64 ftr_mask = arm64_ftr_mask(ftrp); 1025 s64 ftr_new = arm64_ftr_value(ftrp, new); 1026 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1027 1028 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1029 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1030 char *str = NULL; 1031 1032 if (ftr_ovr != tmp) { 1033 /* Unsafe, remove the override */ 1034 reg->override->mask &= ~ftr_mask; 1035 reg->override->val &= ~ftr_mask; 1036 tmp = ftr_ovr; 1037 str = "ignoring override"; 1038 } else if (ftr_new != tmp) { 1039 /* Override was valid */ 1040 ftr_new = tmp; 1041 str = "forced"; 1042 } else { 1043 /* Override was the safe value */ 1044 str = "already set"; 1045 } 1046 1047 pr_warn("%s[%d:%d]: %s to %llx\n", 1048 reg->name, 1049 ftrp->shift + ftrp->width - 1, 1050 ftrp->shift, str, 1051 tmp & (BIT(ftrp->width) - 1)); 1052 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1053 reg->override->val &= ~ftr_mask; 1054 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1055 reg->name, 1056 ftrp->shift + ftrp->width - 1, 1057 ftrp->shift); 1058 } 1059 1060 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1061 1062 valid_mask |= ftr_mask; 1063 if (!ftrp->strict) 1064 strict_mask &= ~ftr_mask; 1065 if (ftrp->visible) 1066 user_mask |= ftr_mask; 1067 else 1068 reg->user_val = arm64_ftr_set_value(ftrp, 1069 reg->user_val, 1070 ftrp->safe_val); 1071 } 1072 1073 val &= valid_mask; 1074 1075 reg->sys_val = val; 1076 reg->strict_mask = strict_mask; 1077 reg->user_mask = user_mask; 1078} 1079 1080extern const struct arm64_cpu_capabilities arm64_errata[]; 1081static const struct arm64_cpu_capabilities arm64_features[]; 1082 1083static void __init 1084init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1085{ 1086 for (; caps->matches; caps++) { 1087 if (WARN(caps->capability >= ARM64_NCAPS, 1088 "Invalid capability %d\n", caps->capability)) 1089 continue; 1090 if (WARN(cpucap_ptrs[caps->capability], 1091 "Duplicate entry for capability %d\n", 1092 caps->capability)) 1093 continue; 1094 cpucap_ptrs[caps->capability] = caps; 1095 } 1096} 1097 1098static void __init init_cpucap_indirect_list(void) 1099{ 1100 init_cpucap_indirect_list_from_array(arm64_features); 1101 init_cpucap_indirect_list_from_array(arm64_errata); 1102} 1103 1104static void __init setup_boot_cpu_capabilities(void); 1105 1106static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1107{ 1108 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1109 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1110 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1111 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1112 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1113 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1114 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1115 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1116 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1117 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1118 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1119 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1120 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1121 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1122 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1123 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1124 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1125 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1126 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1127 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1128 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1129} 1130 1131#ifdef CONFIG_ARM64_PSEUDO_NMI 1132static bool enable_pseudo_nmi; 1133 1134static int __init early_enable_pseudo_nmi(char *p) 1135{ 1136 return kstrtobool(p, &enable_pseudo_nmi); 1137} 1138early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1139 1140static __init void detect_system_supports_pseudo_nmi(void) 1141{ 1142 struct device_node *np; 1143 1144 if (!enable_pseudo_nmi) 1145 return; 1146 1147 /* 1148 * Detect broken MediaTek firmware that doesn't properly save and 1149 * restore GIC priorities. 1150 */ 1151 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1152 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1153 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1154 enable_pseudo_nmi = false; 1155 } 1156 of_node_put(np); 1157} 1158#else /* CONFIG_ARM64_PSEUDO_NMI */ 1159static inline void detect_system_supports_pseudo_nmi(void) { } 1160#endif 1161 1162void __init init_cpu_features(struct cpuinfo_arm64 *info) 1163{ 1164 /* Before we start using the tables, make sure it is sorted */ 1165 sort_ftr_regs(); 1166 1167 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1168 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1169 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1170 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1171 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1172 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1173 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1174 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1175 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1176 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1177 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1178 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1179 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1180 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1181 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1182 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1183 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1184 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1185 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1186 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1187 1188 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1189 init_32bit_cpu_features(&info->aarch32); 1190 1191 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1192 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1193 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1194 1195 vec_init_vq_map(ARM64_VEC_SVE); 1196 1197 cpacr_restore(cpacr); 1198 } 1199 1200 if (IS_ENABLED(CONFIG_ARM64_SME) && 1201 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1202 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1203 1204 vec_init_vq_map(ARM64_VEC_SME); 1205 1206 cpacr_restore(cpacr); 1207 } 1208 1209 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1210 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1211 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1212 } 1213 1214 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1215 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1216} 1217 1218static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1219{ 1220 const struct arm64_ftr_bits *ftrp; 1221 1222 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1223 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1224 s64 ftr_new = arm64_ftr_value(ftrp, new); 1225 1226 if (ftr_cur == ftr_new) 1227 continue; 1228 /* Find a safe value */ 1229 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1230 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1231 } 1232 1233} 1234 1235static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1236{ 1237 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1238 1239 if (!regp) 1240 return 0; 1241 1242 update_cpu_ftr_reg(regp, val); 1243 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1244 return 0; 1245 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1246 regp->name, boot, cpu, val); 1247 return 1; 1248} 1249 1250static void relax_cpu_ftr_reg(u32 sys_id, int field) 1251{ 1252 const struct arm64_ftr_bits *ftrp; 1253 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1254 1255 if (!regp) 1256 return; 1257 1258 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1259 if (ftrp->shift == field) { 1260 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1261 break; 1262 } 1263 } 1264 1265 /* Bogus field? */ 1266 WARN_ON(!ftrp->width); 1267} 1268 1269static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1270 struct cpuinfo_arm64 *boot) 1271{ 1272 static bool boot_cpu_32bit_regs_overridden = false; 1273 1274 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1275 return; 1276 1277 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1278 return; 1279 1280 boot->aarch32 = info->aarch32; 1281 init_32bit_cpu_features(&boot->aarch32); 1282 boot_cpu_32bit_regs_overridden = true; 1283} 1284 1285static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1286 struct cpuinfo_32bit *boot) 1287{ 1288 int taint = 0; 1289 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1290 1291 /* 1292 * If we don't have AArch32 at EL1, then relax the strictness of 1293 * EL1-dependent register fields to avoid spurious sanity check fails. 1294 */ 1295 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1296 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1297 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1298 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1299 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1300 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1301 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1302 } 1303 1304 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1305 info->reg_id_dfr0, boot->reg_id_dfr0); 1306 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1307 info->reg_id_dfr1, boot->reg_id_dfr1); 1308 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1309 info->reg_id_isar0, boot->reg_id_isar0); 1310 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1311 info->reg_id_isar1, boot->reg_id_isar1); 1312 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1313 info->reg_id_isar2, boot->reg_id_isar2); 1314 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1315 info->reg_id_isar3, boot->reg_id_isar3); 1316 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1317 info->reg_id_isar4, boot->reg_id_isar4); 1318 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1319 info->reg_id_isar5, boot->reg_id_isar5); 1320 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1321 info->reg_id_isar6, boot->reg_id_isar6); 1322 1323 /* 1324 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1325 * ACTLR formats could differ across CPUs and therefore would have to 1326 * be trapped for virtualization anyway. 1327 */ 1328 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1329 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1330 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1331 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1332 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1333 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1334 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1335 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1336 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1337 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1338 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1339 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1340 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1341 info->reg_id_pfr0, boot->reg_id_pfr0); 1342 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1343 info->reg_id_pfr1, boot->reg_id_pfr1); 1344 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1345 info->reg_id_pfr2, boot->reg_id_pfr2); 1346 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1347 info->reg_mvfr0, boot->reg_mvfr0); 1348 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1349 info->reg_mvfr1, boot->reg_mvfr1); 1350 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1351 info->reg_mvfr2, boot->reg_mvfr2); 1352 1353 return taint; 1354} 1355 1356/* 1357 * Update system wide CPU feature registers with the values from a 1358 * non-boot CPU. Also performs SANITY checks to make sure that there 1359 * aren't any insane variations from that of the boot CPU. 1360 */ 1361void update_cpu_features(int cpu, 1362 struct cpuinfo_arm64 *info, 1363 struct cpuinfo_arm64 *boot) 1364{ 1365 int taint = 0; 1366 1367 /* 1368 * The kernel can handle differing I-cache policies, but otherwise 1369 * caches should look identical. Userspace JITs will make use of 1370 * *minLine. 1371 */ 1372 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1373 info->reg_ctr, boot->reg_ctr); 1374 1375 /* 1376 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1377 * could result in too much or too little memory being zeroed if a 1378 * process is preempted and migrated between CPUs. 1379 */ 1380 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1381 info->reg_dczid, boot->reg_dczid); 1382 1383 /* If different, timekeeping will be broken (especially with KVM) */ 1384 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1385 info->reg_cntfrq, boot->reg_cntfrq); 1386 1387 /* 1388 * The kernel uses self-hosted debug features and expects CPUs to 1389 * support identical debug features. We presently need CTX_CMPs, WRPs, 1390 * and BRPs to be identical. 1391 * ID_AA64DFR1 is currently RES0. 1392 */ 1393 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1394 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1395 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1396 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1397 /* 1398 * Even in big.LITTLE, processors should be identical instruction-set 1399 * wise. 1400 */ 1401 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1402 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1403 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1404 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1405 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1406 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1407 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1408 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1409 1410 /* 1411 * Differing PARange support is fine as long as all peripherals and 1412 * memory are mapped within the minimum PARange of all CPUs. 1413 * Linux should not care about secure memory. 1414 */ 1415 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1416 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1417 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1418 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1419 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1420 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1421 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1422 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1423 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1424 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1425 1426 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1427 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1428 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1429 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1430 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1431 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1432 1433 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1434 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1435 1436 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1437 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1438 1439 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1440 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1441 1442 /* Probe vector lengths */ 1443 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1444 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1445 if (!system_capabilities_finalized()) { 1446 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1447 1448 vec_update_vq_map(ARM64_VEC_SVE); 1449 1450 cpacr_restore(cpacr); 1451 } 1452 } 1453 1454 if (IS_ENABLED(CONFIG_ARM64_SME) && 1455 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1456 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1457 1458 /* Probe vector lengths */ 1459 if (!system_capabilities_finalized()) 1460 vec_update_vq_map(ARM64_VEC_SME); 1461 1462 cpacr_restore(cpacr); 1463 } 1464 1465 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1466 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1467 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1468 info->reg_mpamidr, boot->reg_mpamidr); 1469 } 1470 1471 /* 1472 * The kernel uses the LDGM/STGM instructions and the number of tags 1473 * they read/write depends on the GMID_EL1.BS field. Check that the 1474 * value is the same on all CPUs. 1475 */ 1476 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1477 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1478 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1479 info->reg_gmid, boot->reg_gmid); 1480 } 1481 1482 /* 1483 * If we don't have AArch32 at all then skip the checks entirely 1484 * as the register values may be UNKNOWN and we're not going to be 1485 * using them for anything. 1486 * 1487 * This relies on a sanitised view of the AArch64 ID registers 1488 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1489 */ 1490 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1491 lazy_init_32bit_cpu_features(info, boot); 1492 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1493 &boot->aarch32); 1494 } 1495 1496 /* 1497 * Mismatched CPU features are a recipe for disaster. Don't even 1498 * pretend to support them. 1499 */ 1500 if (taint) { 1501 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1502 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1503 } 1504} 1505 1506u64 read_sanitised_ftr_reg(u32 id) 1507{ 1508 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1509 1510 if (!regp) 1511 return 0; 1512 return regp->sys_val; 1513} 1514EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1515 1516#define read_sysreg_case(r) \ 1517 case r: val = read_sysreg_s(r); break; 1518 1519/* 1520 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1521 * Read the system register on the current CPU 1522 */ 1523u64 __read_sysreg_by_encoding(u32 sys_id) 1524{ 1525 struct arm64_ftr_reg *regp; 1526 u64 val; 1527 1528 switch (sys_id) { 1529 read_sysreg_case(SYS_ID_PFR0_EL1); 1530 read_sysreg_case(SYS_ID_PFR1_EL1); 1531 read_sysreg_case(SYS_ID_PFR2_EL1); 1532 read_sysreg_case(SYS_ID_DFR0_EL1); 1533 read_sysreg_case(SYS_ID_DFR1_EL1); 1534 read_sysreg_case(SYS_ID_MMFR0_EL1); 1535 read_sysreg_case(SYS_ID_MMFR1_EL1); 1536 read_sysreg_case(SYS_ID_MMFR2_EL1); 1537 read_sysreg_case(SYS_ID_MMFR3_EL1); 1538 read_sysreg_case(SYS_ID_MMFR4_EL1); 1539 read_sysreg_case(SYS_ID_MMFR5_EL1); 1540 read_sysreg_case(SYS_ID_ISAR0_EL1); 1541 read_sysreg_case(SYS_ID_ISAR1_EL1); 1542 read_sysreg_case(SYS_ID_ISAR2_EL1); 1543 read_sysreg_case(SYS_ID_ISAR3_EL1); 1544 read_sysreg_case(SYS_ID_ISAR4_EL1); 1545 read_sysreg_case(SYS_ID_ISAR5_EL1); 1546 read_sysreg_case(SYS_ID_ISAR6_EL1); 1547 read_sysreg_case(SYS_MVFR0_EL1); 1548 read_sysreg_case(SYS_MVFR1_EL1); 1549 read_sysreg_case(SYS_MVFR2_EL1); 1550 1551 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1552 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1553 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1554 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1555 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1556 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1557 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1558 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1559 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1560 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1561 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1562 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1563 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1564 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1565 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1566 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1567 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1568 1569 read_sysreg_case(SYS_CNTFRQ_EL0); 1570 read_sysreg_case(SYS_CTR_EL0); 1571 read_sysreg_case(SYS_DCZID_EL0); 1572 1573 default: 1574 BUG(); 1575 return 0; 1576 } 1577 1578 regp = get_arm64_ftr_reg(sys_id); 1579 if (regp) { 1580 val &= ~regp->override->mask; 1581 val |= (regp->override->val & regp->override->mask); 1582 } 1583 1584 return val; 1585} 1586 1587#include <linux/irqchip/arm-gic-v3.h> 1588 1589static bool 1590has_always(const struct arm64_cpu_capabilities *entry, int scope) 1591{ 1592 return true; 1593} 1594 1595static bool 1596feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1597{ 1598 int val, min, max; 1599 u64 tmp; 1600 1601 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1602 entry->field_width, 1603 entry->sign); 1604 1605 tmp = entry->min_field_value; 1606 tmp <<= entry->field_pos; 1607 1608 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1609 entry->field_width, 1610 entry->sign); 1611 1612 tmp = entry->max_field_value; 1613 tmp <<= entry->field_pos; 1614 1615 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1616 entry->field_width, 1617 entry->sign); 1618 1619 return val >= min && val <= max; 1620} 1621 1622static u64 1623read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1624{ 1625 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1626 if (scope == SCOPE_SYSTEM) 1627 return read_sanitised_ftr_reg(entry->sys_reg); 1628 else 1629 return __read_sysreg_by_encoding(entry->sys_reg); 1630} 1631 1632static bool 1633has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1634{ 1635 int mask; 1636 struct arm64_ftr_reg *regp; 1637 u64 val = read_scoped_sysreg(entry, scope); 1638 1639 regp = get_arm64_ftr_reg(entry->sys_reg); 1640 if (!regp) 1641 return false; 1642 1643 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1644 entry->field_pos, 1645 entry->field_width); 1646 if (!mask) 1647 return false; 1648 1649 return feature_matches(val, entry); 1650} 1651 1652static bool 1653has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1654{ 1655 u64 val = read_scoped_sysreg(entry, scope); 1656 return feature_matches(val, entry); 1657} 1658 1659const struct cpumask *system_32bit_el0_cpumask(void) 1660{ 1661 if (!system_supports_32bit_el0()) 1662 return cpu_none_mask; 1663 1664 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1665 return cpu_32bit_el0_mask; 1666 1667 return cpu_possible_mask; 1668} 1669 1670const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1671{ 1672 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1673} 1674 1675static int __init parse_32bit_el0_param(char *str) 1676{ 1677 allow_mismatched_32bit_el0 = true; 1678 return 0; 1679} 1680early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1681 1682static ssize_t aarch32_el0_show(struct device *dev, 1683 struct device_attribute *attr, char *buf) 1684{ 1685 const struct cpumask *mask = system_32bit_el0_cpumask(); 1686 1687 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1688} 1689static const DEVICE_ATTR_RO(aarch32_el0); 1690 1691static int __init aarch32_el0_sysfs_init(void) 1692{ 1693 struct device *dev_root; 1694 int ret = 0; 1695 1696 if (!allow_mismatched_32bit_el0) 1697 return 0; 1698 1699 dev_root = bus_get_dev_root(&cpu_subsys); 1700 if (dev_root) { 1701 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1702 put_device(dev_root); 1703 } 1704 return ret; 1705} 1706device_initcall(aarch32_el0_sysfs_init); 1707 1708static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1709{ 1710 if (!has_cpuid_feature(entry, scope)) 1711 return allow_mismatched_32bit_el0; 1712 1713 if (scope == SCOPE_SYSTEM) 1714 pr_info("detected: 32-bit EL0 Support\n"); 1715 1716 return true; 1717} 1718 1719static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1720{ 1721 bool has_sre; 1722 1723 if (!has_cpuid_feature(entry, scope)) 1724 return false; 1725 1726 has_sre = gic_enable_sre(); 1727 if (!has_sre) 1728 pr_warn_once("%s present but disabled by higher exception level\n", 1729 entry->desc); 1730 1731 return has_sre; 1732} 1733 1734static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1735 int scope) 1736{ 1737 u64 ctr; 1738 1739 if (scope == SCOPE_SYSTEM) 1740 ctr = arm64_ftr_reg_ctrel0.sys_val; 1741 else 1742 ctr = read_cpuid_effective_cachetype(); 1743 1744 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1745} 1746 1747static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1748{ 1749 /* 1750 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1751 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1752 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1753 * value. 1754 */ 1755 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1756 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1757} 1758 1759static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1760 int scope) 1761{ 1762 u64 ctr; 1763 1764 if (scope == SCOPE_SYSTEM) 1765 ctr = arm64_ftr_reg_ctrel0.sys_val; 1766 else 1767 ctr = read_cpuid_cachetype(); 1768 1769 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1770} 1771 1772static bool __maybe_unused 1773has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1774{ 1775 /* 1776 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1777 * may share TLB entries with a CPU stuck in the crashed 1778 * kernel. 1779 */ 1780 if (is_kdump_kernel()) 1781 return false; 1782 1783 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1784 return false; 1785 1786 return has_cpuid_feature(entry, scope); 1787} 1788 1789static bool __meltdown_safe = true; 1790static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1791 1792static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1793 int scope) 1794{ 1795 /* List of CPUs that are not vulnerable and don't need KPTI */ 1796 static const struct midr_range kpti_safe_list[] = { 1797 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1798 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1799 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1800 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1801 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1802 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1803 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1804 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1805 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1806 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1807 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1808 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1809 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1810 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1811 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1812 { /* sentinel */ } 1813 }; 1814 char const *str = "kpti command line option"; 1815 bool meltdown_safe; 1816 1817 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1818 1819 /* Defer to CPU feature registers */ 1820 if (has_cpuid_feature(entry, scope)) 1821 meltdown_safe = true; 1822 1823 if (!meltdown_safe) 1824 __meltdown_safe = false; 1825 1826 /* 1827 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1828 * ThunderX leads to apparent I-cache corruption of kernel text, which 1829 * ends as well as you might imagine. Don't even try. We cannot rely 1830 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1831 * because cpucap detection order may change. However, since we know 1832 * affected CPUs are always in a homogeneous configuration, it is 1833 * safe to rely on this_cpu_has_cap() here. 1834 */ 1835 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1836 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1837 __kpti_forced = -1; 1838 } 1839 1840 /* Useful for KASLR robustness */ 1841 if (kaslr_enabled() && kaslr_requires_kpti()) { 1842 if (!__kpti_forced) { 1843 str = "KASLR"; 1844 __kpti_forced = 1; 1845 } 1846 } 1847 1848 if (cpu_mitigations_off() && !__kpti_forced) { 1849 str = "mitigations=off"; 1850 __kpti_forced = -1; 1851 } 1852 1853 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1854 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1855 return false; 1856 } 1857 1858 /* Forced? */ 1859 if (__kpti_forced) { 1860 pr_info_once("kernel page table isolation forced %s by %s\n", 1861 __kpti_forced > 0 ? "ON" : "OFF", str); 1862 return __kpti_forced > 0; 1863 } 1864 1865 return !meltdown_safe; 1866} 1867 1868static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1869{ 1870 /* 1871 * Although the Apple M2 family appears to support NV1, the 1872 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1873 * that it doesn't support NV1 at all. 1874 */ 1875 static const struct midr_range nv1_ni_list[] = { 1876 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1877 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1878 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1879 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1880 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1881 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1882 {} 1883 }; 1884 1885 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1886 !(has_cpuid_feature(entry, scope) || 1887 is_midr_in_range_list(nv1_ni_list))); 1888} 1889 1890#if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1891static bool has_lpa2_at_stage1(u64 mmfr0) 1892{ 1893 unsigned int tgran; 1894 1895 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1896 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1897 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1898} 1899 1900static bool has_lpa2_at_stage2(u64 mmfr0) 1901{ 1902 unsigned int tgran; 1903 1904 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1905 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1906 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1907} 1908 1909static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1910{ 1911 u64 mmfr0; 1912 1913 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1914 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1915} 1916#else 1917static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1918{ 1919 return false; 1920} 1921#endif 1922 1923#ifdef CONFIG_HW_PERF_EVENTS 1924static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1925{ 1926 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1927 unsigned int pmuver; 1928 1929 /* 1930 * PMUVer follows the standard ID scheme for an unsigned field with the 1931 * exception of 0xF (IMP_DEF) which is treated specially and implies 1932 * FEAT_PMUv3 is not implemented. 1933 * 1934 * See DDI0487L.a D24.1.3.2 for more details. 1935 */ 1936 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1937 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1938 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1939 return false; 1940 1941 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1942} 1943#endif 1944 1945static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1946{ 1947 if (__this_cpu_read(this_cpu_vector) == vectors) { 1948 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1949 1950 __this_cpu_write(this_cpu_vector, v); 1951 } 1952 1953} 1954 1955static int __init parse_kpti(char *str) 1956{ 1957 bool enabled; 1958 int ret = kstrtobool(str, &enabled); 1959 1960 if (ret) 1961 return ret; 1962 1963 __kpti_forced = enabled ? 1 : -1; 1964 return 0; 1965} 1966early_param("kpti", parse_kpti); 1967 1968#ifdef CONFIG_ARM64_HW_AFDBM 1969static struct cpumask dbm_cpus __read_mostly; 1970 1971static inline void __cpu_enable_hw_dbm(void) 1972{ 1973 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1974 1975 write_sysreg(tcr, tcr_el1); 1976 isb(); 1977 local_flush_tlb_all(); 1978} 1979 1980static bool cpu_has_broken_dbm(void) 1981{ 1982 /* List of CPUs which have broken DBM support. */ 1983 static const struct midr_range cpus[] = { 1984#ifdef CONFIG_ARM64_ERRATUM_1024718 1985 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1986 /* Kryo4xx Silver (rdpe => r1p0) */ 1987 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1988#endif 1989#ifdef CONFIG_ARM64_ERRATUM_2051678 1990 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1991#endif 1992 {}, 1993 }; 1994 1995 return is_midr_in_range_list(cpus); 1996} 1997 1998static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1999{ 2000 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2001 !cpu_has_broken_dbm(); 2002} 2003 2004static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2005{ 2006 if (cpu_can_use_dbm(cap)) { 2007 __cpu_enable_hw_dbm(); 2008 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2009 } 2010} 2011 2012static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2013 int __unused) 2014{ 2015 /* 2016 * DBM is a non-conflicting feature. i.e, the kernel can safely 2017 * run a mix of CPUs with and without the feature. So, we 2018 * unconditionally enable the capability to allow any late CPU 2019 * to use the feature. We only enable the control bits on the 2020 * CPU, if it is supported. 2021 */ 2022 2023 return true; 2024} 2025 2026#endif 2027 2028#ifdef CONFIG_ARM64_AMU_EXTN 2029 2030/* 2031 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2032 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2033 * information regarding all the events that it supports. When a CPU bit is 2034 * set in the cpumask, the user of this feature can only rely on the presence 2035 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2036 * counters are enabled or access to these counters is enabled by code 2037 * executed at higher exception levels (firmware). 2038 */ 2039static struct cpumask amu_cpus __read_mostly; 2040 2041bool cpu_has_amu_feat(int cpu) 2042{ 2043 return cpumask_test_cpu(cpu, &amu_cpus); 2044} 2045 2046int get_cpu_with_amu_feat(void) 2047{ 2048 return cpumask_any(&amu_cpus); 2049} 2050 2051static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2052{ 2053 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2054 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2055 2056 /* 0 reference values signal broken/disabled counters */ 2057 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2058 update_freq_counters_refs(); 2059 } 2060} 2061 2062static bool has_amu(const struct arm64_cpu_capabilities *cap, 2063 int __unused) 2064{ 2065 /* 2066 * The AMU extension is a non-conflicting feature: the kernel can 2067 * safely run a mix of CPUs with and without support for the 2068 * activity monitors extension. Therefore, unconditionally enable 2069 * the capability to allow any late CPU to use the feature. 2070 * 2071 * With this feature unconditionally enabled, the cpu_enable 2072 * function will be called for all CPUs that match the criteria, 2073 * including secondary and hotplugged, marking this feature as 2074 * present on that respective CPU. The enable function will also 2075 * print a detection message. 2076 */ 2077 2078 return true; 2079} 2080#else 2081int get_cpu_with_amu_feat(void) 2082{ 2083 return nr_cpu_ids; 2084} 2085#endif 2086 2087static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2088{ 2089 return is_kernel_in_hyp_mode(); 2090} 2091 2092static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2093{ 2094 /* 2095 * Copy register values that aren't redirected by hardware. 2096 * 2097 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2098 * this value to tpidr_el2 before we patch the code. Once we've done 2099 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2100 * do anything here. 2101 */ 2102 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2103 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2104} 2105 2106static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2107 int scope) 2108{ 2109 if (kvm_get_mode() != KVM_MODE_NV) 2110 return false; 2111 2112 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2113 pr_warn("unavailable: %s\n", cap->desc); 2114 return false; 2115 } 2116 2117 return true; 2118} 2119 2120static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2121 int __unused) 2122{ 2123 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2124} 2125 2126bool cpu_supports_bbml2_noabort(void) 2127{ 2128 /* 2129 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2130 * as possible. This list is therefore an allow-list of known-good 2131 * implementations that both support BBML2 and additionally, fulfill the 2132 * extra constraint of never generating TLB conflict aborts when using 2133 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2134 * kernel contexts difficult to prove safe against recursive aborts). 2135 * 2136 * Note that implementations can only be considered "known-good" if their 2137 * implementors attest to the fact that the implementation never raises 2138 * TLB conflict aborts for BBML2 mapping granularity changes. 2139 */ 2140 static const struct midr_range supports_bbml2_noabort_list[] = { 2141 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2142 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2143 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2144 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2145 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2146 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2147 {} 2148 }; 2149 2150 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2151 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2152 return false; 2153 2154 /* 2155 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2156 * about whether the MIDR check passes. 2157 */ 2158 2159 return true; 2160} 2161 2162static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2163{ 2164 return cpu_supports_bbml2_noabort(); 2165} 2166 2167#ifdef CONFIG_ARM64_PAN 2168static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2169{ 2170 /* 2171 * We modify PSTATE. This won't work from irq context as the PSTATE 2172 * is discarded once we return from the exception. 2173 */ 2174 WARN_ON_ONCE(in_interrupt()); 2175 2176 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2177 set_pstate_pan(1); 2178} 2179#endif /* CONFIG_ARM64_PAN */ 2180 2181#ifdef CONFIG_ARM64_RAS_EXTN 2182static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2183{ 2184 /* Firmware may have left a deferred SError in this register. */ 2185 write_sysreg_s(0, SYS_DISR_EL1); 2186} 2187static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2188{ 2189 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2190 { 2191 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2192 }, 2193 { 2194 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2195 }, 2196 { 2197 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2198 }, 2199 }; 2200 2201 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2202 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2203 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2204} 2205#endif /* CONFIG_ARM64_RAS_EXTN */ 2206 2207#ifdef CONFIG_ARM64_PTR_AUTH 2208static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2209{ 2210 int boot_val, sec_val; 2211 2212 /* We don't expect to be called with SCOPE_SYSTEM */ 2213 WARN_ON(scope == SCOPE_SYSTEM); 2214 /* 2215 * The ptr-auth feature levels are not intercompatible with lower 2216 * levels. Hence we must match ptr-auth feature level of the secondary 2217 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2218 * from the sanitised register whereas direct register read is done for 2219 * the secondary CPUs. 2220 * The sanitised feature state is guaranteed to match that of the 2221 * boot CPU as a mismatched secondary CPU is parked before it gets 2222 * a chance to update the state, with the capability. 2223 */ 2224 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2225 entry->field_pos, entry->sign); 2226 if (scope & SCOPE_BOOT_CPU) 2227 return boot_val >= entry->min_field_value; 2228 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2229 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2230 entry->field_pos, entry->sign); 2231 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2232} 2233 2234static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2235 int scope) 2236{ 2237 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2238 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2239 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2240 2241 return apa || apa3 || api; 2242} 2243 2244static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2245 int __unused) 2246{ 2247 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2248 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2249 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2250 2251 return gpa || gpa3 || gpi; 2252} 2253#endif /* CONFIG_ARM64_PTR_AUTH */ 2254 2255#ifdef CONFIG_ARM64_E0PD 2256static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2257{ 2258 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2259 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2260} 2261#endif /* CONFIG_ARM64_E0PD */ 2262 2263#ifdef CONFIG_ARM64_PSEUDO_NMI 2264static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2265 int scope) 2266{ 2267 /* 2268 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2269 * feature, so will be detected earlier. 2270 */ 2271 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2272 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2273 return false; 2274 2275 return enable_pseudo_nmi; 2276} 2277 2278static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2279 int scope) 2280{ 2281 /* 2282 * If we're not using priority masking then we won't be poking PMR_EL1, 2283 * and there's no need to relax synchronization of writes to it, and 2284 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2285 * that. 2286 * 2287 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2288 * feature, so will be detected earlier. 2289 */ 2290 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2291 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2292 return false; 2293 2294 /* 2295 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2296 * hint for interrupt distribution, a DSB is not necessary when 2297 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2298 * 2299 * Linux itself doesn't use 1:N distribution, so has no need to 2300 * set PMHE. The only reason to have it set is if EL3 requires it 2301 * (and we can't change it). 2302 */ 2303 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2304} 2305#endif 2306 2307static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2308 int scope) 2309{ 2310 static const struct midr_range has_vgic_v3[] = { 2311 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2312 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2313 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2314 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2315 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2316 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2317 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2318 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2319 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2320 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2321 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2322 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2323 {}, 2324 }; 2325 struct arm_smccc_res res = {}; 2326 2327 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2328 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2329 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2330 !is_midr_in_range_list(has_vgic_v3)) 2331 return false; 2332 2333 if (!is_hyp_mode_available()) 2334 return false; 2335 2336 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2337 return true; 2338 2339 /* 2340 * pKVM prevents late onlining of CPUs. This means that whatever 2341 * state the capability is in after deprivilege cannot be affected 2342 * by a new CPU booting -- this is garanteed to be a CPU we have 2343 * already seen, and the cap is therefore unchanged. 2344 */ 2345 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2346 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2347 2348 if (is_kernel_in_hyp_mode()) 2349 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2350 else 2351 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2352 2353 if (res.a0 == HVC_STUB_ERR) 2354 return false; 2355 2356 return res.a1 & ICH_VTR_EL2_TDS; 2357} 2358 2359#ifdef CONFIG_ARM64_BTI 2360static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2361{ 2362 /* 2363 * Use of X16/X17 for tail-calls and trampolines that jump to 2364 * function entry points using BR is a requirement for 2365 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2366 * So, be strict and forbid other BRs using other registers to 2367 * jump onto a PACIxSP instruction: 2368 */ 2369 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2370 isb(); 2371} 2372#endif /* CONFIG_ARM64_BTI */ 2373 2374#ifdef CONFIG_ARM64_MTE 2375static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2376{ 2377 static bool cleared_zero_page = false; 2378 2379 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2380 2381 mte_cpu_setup(); 2382 2383 /* 2384 * Clear the tags in the zero page. This needs to be done via the 2385 * linear map which has the Tagged attribute. Since this page is 2386 * always mapped as pte_special(), set_pte_at() will not attempt to 2387 * clear the tags or set PG_mte_tagged. 2388 */ 2389 if (!cleared_zero_page) { 2390 cleared_zero_page = true; 2391 mte_clear_page_tags(lm_alias(empty_zero_page)); 2392 } 2393 2394 kasan_init_hw_tags_cpu(); 2395} 2396#endif /* CONFIG_ARM64_MTE */ 2397 2398static void user_feature_fixup(void) 2399{ 2400 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2401 struct arm64_ftr_reg *regp; 2402 2403 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2404 if (regp) 2405 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2406 } 2407 2408 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2409 struct arm64_ftr_reg *regp; 2410 2411 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2412 if (regp) 2413 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2414 } 2415} 2416 2417static void elf_hwcap_fixup(void) 2418{ 2419#ifdef CONFIG_COMPAT 2420 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2421 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2422#endif /* CONFIG_COMPAT */ 2423} 2424 2425#ifdef CONFIG_KVM 2426static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2427{ 2428 return kvm_get_mode() == KVM_MODE_PROTECTED; 2429} 2430#endif /* CONFIG_KVM */ 2431 2432static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2433{ 2434 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2435} 2436 2437static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2438{ 2439 set_pstate_dit(1); 2440} 2441 2442static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2443{ 2444 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2445} 2446 2447#ifdef CONFIG_ARM64_POE 2448static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2449{ 2450 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2451 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2452} 2453#endif 2454 2455#ifdef CONFIG_ARM64_GCS 2456static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2457{ 2458 /* GCSPR_EL0 is always readable */ 2459 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2460} 2461#endif 2462 2463/* Internal helper functions to match cpu capability type */ 2464static bool 2465cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2466{ 2467 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2468} 2469 2470static bool 2471cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2472{ 2473 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2474} 2475 2476static bool 2477cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2478{ 2479 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2480} 2481 2482static bool 2483test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2484{ 2485 if (!has_cpuid_feature(entry, scope)) 2486 return false; 2487 2488 /* Check firmware actually enabled MPAM on this cpu. */ 2489 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2490} 2491 2492static void 2493cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2494{ 2495 /* 2496 * Access by the kernel (at EL1) should use the reserved PARTID 2497 * which is configured unrestricted. This avoids priority-inversion 2498 * where latency sensitive tasks have to wait for a task that has 2499 * been throttled to release the lock. 2500 */ 2501 write_sysreg_s(0, SYS_MPAM1_EL1); 2502} 2503 2504static bool 2505test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2506{ 2507 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2508 2509 return idr & MPAMIDR_EL1_HAS_HCR; 2510} 2511 2512static bool 2513test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2514{ 2515 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2516 return false; 2517 2518 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2519} 2520 2521static const struct arm64_cpu_capabilities arm64_features[] = { 2522 { 2523 .capability = ARM64_ALWAYS_BOOT, 2524 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2525 .matches = has_always, 2526 }, 2527 { 2528 .capability = ARM64_ALWAYS_SYSTEM, 2529 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2530 .matches = has_always, 2531 }, 2532 { 2533 .desc = "GICv3 CPU interface", 2534 .capability = ARM64_HAS_GICV3_CPUIF, 2535 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2536 .matches = has_useable_gicv3_cpuif, 2537 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2538 }, 2539 { 2540 .desc = "Enhanced Counter Virtualization", 2541 .capability = ARM64_HAS_ECV, 2542 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2543 .matches = has_cpuid_feature, 2544 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2545 }, 2546 { 2547 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2548 .capability = ARM64_HAS_ECV_CNTPOFF, 2549 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2550 .matches = has_cpuid_feature, 2551 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2552 }, 2553#ifdef CONFIG_ARM64_PAN 2554 { 2555 .desc = "Privileged Access Never", 2556 .capability = ARM64_HAS_PAN, 2557 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2558 .matches = has_cpuid_feature, 2559 .cpu_enable = cpu_enable_pan, 2560 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2561 }, 2562#endif /* CONFIG_ARM64_PAN */ 2563#ifdef CONFIG_ARM64_EPAN 2564 { 2565 .desc = "Enhanced Privileged Access Never", 2566 .capability = ARM64_HAS_EPAN, 2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2568 .matches = has_cpuid_feature, 2569 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2570 }, 2571#endif /* CONFIG_ARM64_EPAN */ 2572#ifdef CONFIG_ARM64_LSE_ATOMICS 2573 { 2574 .desc = "LSE atomic instructions", 2575 .capability = ARM64_HAS_LSE_ATOMICS, 2576 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2577 .matches = has_cpuid_feature, 2578 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2579 }, 2580#endif /* CONFIG_ARM64_LSE_ATOMICS */ 2581 { 2582 .desc = "Virtualization Host Extensions", 2583 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2584 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2585 .matches = runs_at_el2, 2586 .cpu_enable = cpu_copy_el2regs, 2587 }, 2588 { 2589 .desc = "Nested Virtualization Support", 2590 .capability = ARM64_HAS_NESTED_VIRT, 2591 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2592 .matches = has_nested_virt_support, 2593 .match_list = (const struct arm64_cpu_capabilities []){ 2594 { 2595 .matches = has_cpuid_feature, 2596 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2597 }, 2598 { 2599 .matches = has_cpuid_feature, 2600 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2601 }, 2602 { /* Sentinel */ } 2603 }, 2604 }, 2605 { 2606 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2607 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2608 .matches = has_32bit_el0, 2609 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2610 }, 2611#ifdef CONFIG_KVM 2612 { 2613 .desc = "32-bit EL1 Support", 2614 .capability = ARM64_HAS_32BIT_EL1, 2615 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2616 .matches = has_cpuid_feature, 2617 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2618 }, 2619 { 2620 .desc = "Protected KVM", 2621 .capability = ARM64_KVM_PROTECTED_MODE, 2622 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2623 .matches = is_kvm_protected_mode, 2624 }, 2625 { 2626 .desc = "HCRX_EL2 register", 2627 .capability = ARM64_HAS_HCX, 2628 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2629 .matches = has_cpuid_feature, 2630 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2631 }, 2632#endif 2633 { 2634 .desc = "Kernel page table isolation (KPTI)", 2635 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2636 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2637 .cpu_enable = cpu_enable_kpti, 2638 .matches = unmap_kernel_at_el0, 2639 /* 2640 * The ID feature fields below are used to indicate that 2641 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2642 * more details. 2643 */ 2644 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2645 }, 2646 { 2647 .capability = ARM64_HAS_FPSIMD, 2648 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2649 .matches = has_cpuid_feature, 2650 .cpu_enable = cpu_enable_fpsimd, 2651 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2652 }, 2653#ifdef CONFIG_ARM64_PMEM 2654 { 2655 .desc = "Data cache clean to Point of Persistence", 2656 .capability = ARM64_HAS_DCPOP, 2657 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2658 .matches = has_cpuid_feature, 2659 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2660 }, 2661 { 2662 .desc = "Data cache clean to Point of Deep Persistence", 2663 .capability = ARM64_HAS_DCPODP, 2664 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2665 .matches = has_cpuid_feature, 2666 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2667 }, 2668#endif 2669#ifdef CONFIG_ARM64_SVE 2670 { 2671 .desc = "Scalable Vector Extension", 2672 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2673 .capability = ARM64_SVE, 2674 .cpu_enable = cpu_enable_sve, 2675 .matches = has_cpuid_feature, 2676 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2677 }, 2678#endif /* CONFIG_ARM64_SVE */ 2679#ifdef CONFIG_ARM64_RAS_EXTN 2680 { 2681 .desc = "RAS Extension Support", 2682 .capability = ARM64_HAS_RAS_EXTN, 2683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2684 .matches = has_cpuid_feature, 2685 .cpu_enable = cpu_clear_disr, 2686 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2687 }, 2688 { 2689 .desc = "RASv1p1 Extension Support", 2690 .capability = ARM64_HAS_RASV1P1_EXTN, 2691 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2692 .matches = has_rasv1p1, 2693 }, 2694#endif /* CONFIG_ARM64_RAS_EXTN */ 2695#ifdef CONFIG_ARM64_AMU_EXTN 2696 { 2697 .desc = "Activity Monitors Unit (AMU)", 2698 .capability = ARM64_HAS_AMU_EXTN, 2699 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2700 .matches = has_amu, 2701 .cpu_enable = cpu_amu_enable, 2702 .cpus = &amu_cpus, 2703 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2704 }, 2705#endif /* CONFIG_ARM64_AMU_EXTN */ 2706 { 2707 .desc = "Data cache clean to the PoU not required for I/D coherence", 2708 .capability = ARM64_HAS_CACHE_IDC, 2709 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2710 .matches = has_cache_idc, 2711 .cpu_enable = cpu_emulate_effective_ctr, 2712 }, 2713 { 2714 .desc = "Instruction cache invalidation not required for I/D coherence", 2715 .capability = ARM64_HAS_CACHE_DIC, 2716 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2717 .matches = has_cache_dic, 2718 }, 2719 { 2720 .desc = "Stage-2 Force Write-Back", 2721 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2722 .capability = ARM64_HAS_STAGE2_FWB, 2723 .matches = has_cpuid_feature, 2724 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2725 }, 2726 { 2727 .desc = "ARMv8.4 Translation Table Level", 2728 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2729 .capability = ARM64_HAS_ARMv8_4_TTL, 2730 .matches = has_cpuid_feature, 2731 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2732 }, 2733 { 2734 .desc = "TLB range maintenance instructions", 2735 .capability = ARM64_HAS_TLB_RANGE, 2736 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2737 .matches = has_cpuid_feature, 2738 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2739 }, 2740#ifdef CONFIG_ARM64_HW_AFDBM 2741 { 2742 .desc = "Hardware dirty bit management", 2743 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2744 .capability = ARM64_HW_DBM, 2745 .matches = has_hw_dbm, 2746 .cpu_enable = cpu_enable_hw_dbm, 2747 .cpus = &dbm_cpus, 2748 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2749 }, 2750#endif 2751#ifdef CONFIG_ARM64_HAFT 2752 { 2753 .desc = "Hardware managed Access Flag for Table Descriptors", 2754 /* 2755 * Contrary to the page/block access flag, the table access flag 2756 * cannot be emulated in software (no access fault will occur). 2757 * Therefore this should be used only if it's supported system 2758 * wide. 2759 */ 2760 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2761 .capability = ARM64_HAFT, 2762 .matches = has_cpuid_feature, 2763 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2764 }, 2765#endif 2766 { 2767 .desc = "CRC32 instructions", 2768 .capability = ARM64_HAS_CRC32, 2769 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2770 .matches = has_cpuid_feature, 2771 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2772 }, 2773 { 2774 .desc = "Speculative Store Bypassing Safe (SSBS)", 2775 .capability = ARM64_SSBS, 2776 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2777 .matches = has_cpuid_feature, 2778 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2779 }, 2780#ifdef CONFIG_ARM64_CNP 2781 { 2782 .desc = "Common not Private translations", 2783 .capability = ARM64_HAS_CNP, 2784 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2785 .matches = has_useable_cnp, 2786 .cpu_enable = cpu_enable_cnp, 2787 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2788 }, 2789#endif 2790 { 2791 .desc = "Speculation barrier (SB)", 2792 .capability = ARM64_HAS_SB, 2793 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2794 .matches = has_cpuid_feature, 2795 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2796 }, 2797#ifdef CONFIG_ARM64_PTR_AUTH 2798 { 2799 .desc = "Address authentication (architected QARMA5 algorithm)", 2800 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2801 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2802 .matches = has_address_auth_cpucap, 2803 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2804 }, 2805 { 2806 .desc = "Address authentication (architected QARMA3 algorithm)", 2807 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2808 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2809 .matches = has_address_auth_cpucap, 2810 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2811 }, 2812 { 2813 .desc = "Address authentication (IMP DEF algorithm)", 2814 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2815 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2816 .matches = has_address_auth_cpucap, 2817 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2818 }, 2819 { 2820 .capability = ARM64_HAS_ADDRESS_AUTH, 2821 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2822 .matches = has_address_auth_metacap, 2823 }, 2824 { 2825 .desc = "Generic authentication (architected QARMA5 algorithm)", 2826 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2827 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2828 .matches = has_cpuid_feature, 2829 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2830 }, 2831 { 2832 .desc = "Generic authentication (architected QARMA3 algorithm)", 2833 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2834 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2835 .matches = has_cpuid_feature, 2836 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2837 }, 2838 { 2839 .desc = "Generic authentication (IMP DEF algorithm)", 2840 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2841 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2842 .matches = has_cpuid_feature, 2843 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2844 }, 2845 { 2846 .capability = ARM64_HAS_GENERIC_AUTH, 2847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2848 .matches = has_generic_auth, 2849 }, 2850#endif /* CONFIG_ARM64_PTR_AUTH */ 2851#ifdef CONFIG_ARM64_PSEUDO_NMI 2852 { 2853 /* 2854 * Depends on having GICv3 2855 */ 2856 .desc = "IRQ priority masking", 2857 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2858 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2859 .matches = can_use_gic_priorities, 2860 }, 2861 { 2862 /* 2863 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2864 */ 2865 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2866 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2867 .matches = has_gic_prio_relaxed_sync, 2868 }, 2869#endif 2870 { 2871 /* 2872 * Depends on having GICv3 2873 */ 2874 .desc = "ICV_DIR_EL1 trapping", 2875 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2876 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2877 .matches = can_trap_icv_dir_el1, 2878 }, 2879#ifdef CONFIG_ARM64_E0PD 2880 { 2881 .desc = "E0PD", 2882 .capability = ARM64_HAS_E0PD, 2883 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2884 .cpu_enable = cpu_enable_e0pd, 2885 .matches = has_cpuid_feature, 2886 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2887 }, 2888#endif 2889 { 2890 .desc = "Random Number Generator", 2891 .capability = ARM64_HAS_RNG, 2892 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2893 .matches = has_cpuid_feature, 2894 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2895 }, 2896#ifdef CONFIG_ARM64_BTI 2897 { 2898 .desc = "Branch Target Identification", 2899 .capability = ARM64_BTI, 2900#ifdef CONFIG_ARM64_BTI_KERNEL 2901 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2902#else 2903 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2904#endif 2905 .matches = has_cpuid_feature, 2906 .cpu_enable = bti_enable, 2907 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2908 }, 2909#endif 2910#ifdef CONFIG_ARM64_MTE 2911 { 2912 .desc = "Memory Tagging Extension", 2913 .capability = ARM64_MTE, 2914 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2915 .matches = has_cpuid_feature, 2916 .cpu_enable = cpu_enable_mte, 2917 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2918 }, 2919 { 2920 .desc = "Asymmetric MTE Tag Check Fault", 2921 .capability = ARM64_MTE_ASYMM, 2922 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2923 .matches = has_cpuid_feature, 2924 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2925 }, 2926 { 2927 .desc = "FAR on MTE Tag Check Fault", 2928 .capability = ARM64_MTE_FAR, 2929 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2930 .matches = has_cpuid_feature, 2931 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2932 }, 2933 { 2934 .desc = "Store Only MTE Tag Check", 2935 .capability = ARM64_MTE_STORE_ONLY, 2936 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2937 .matches = has_cpuid_feature, 2938 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2939 }, 2940#endif /* CONFIG_ARM64_MTE */ 2941 { 2942 .desc = "RCpc load-acquire (LDAPR)", 2943 .capability = ARM64_HAS_LDAPR, 2944 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2945 .matches = has_cpuid_feature, 2946 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2947 }, 2948 { 2949 .desc = "Fine Grained Traps", 2950 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2951 .capability = ARM64_HAS_FGT, 2952 .matches = has_cpuid_feature, 2953 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2954 }, 2955 { 2956 .desc = "Fine Grained Traps 2", 2957 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2958 .capability = ARM64_HAS_FGT2, 2959 .matches = has_cpuid_feature, 2960 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2961 }, 2962#ifdef CONFIG_ARM64_SME 2963 { 2964 .desc = "Scalable Matrix Extension", 2965 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2966 .capability = ARM64_SME, 2967 .matches = has_cpuid_feature, 2968 .cpu_enable = cpu_enable_sme, 2969 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2970 }, 2971 /* FA64 should be sorted after the base SME capability */ 2972 { 2973 .desc = "FA64", 2974 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2975 .capability = ARM64_SME_FA64, 2976 .matches = has_cpuid_feature, 2977 .cpu_enable = cpu_enable_fa64, 2978 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2979 }, 2980 { 2981 .desc = "SME2", 2982 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2983 .capability = ARM64_SME2, 2984 .matches = has_cpuid_feature, 2985 .cpu_enable = cpu_enable_sme2, 2986 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2987 }, 2988#endif /* CONFIG_ARM64_SME */ 2989 { 2990 .desc = "WFx with timeout", 2991 .capability = ARM64_HAS_WFXT, 2992 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2993 .matches = has_cpuid_feature, 2994 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2995 }, 2996 { 2997 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2998 .capability = ARM64_HAS_TIDCP1, 2999 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3000 .matches = has_cpuid_feature, 3001 .cpu_enable = cpu_trap_el0_impdef, 3002 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 3003 }, 3004 { 3005 .desc = "Data independent timing control (DIT)", 3006 .capability = ARM64_HAS_DIT, 3007 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3008 .matches = has_cpuid_feature, 3009 .cpu_enable = cpu_enable_dit, 3010 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3011 }, 3012 { 3013 .desc = "Memory Copy and Memory Set instructions", 3014 .capability = ARM64_HAS_MOPS, 3015 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3016 .matches = has_cpuid_feature, 3017 .cpu_enable = cpu_enable_mops, 3018 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3019 }, 3020 { 3021 .capability = ARM64_HAS_TCR2, 3022 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3023 .matches = has_cpuid_feature, 3024 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3025 }, 3026 { 3027 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3028 .capability = ARM64_HAS_S1PIE, 3029 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3030 .matches = has_cpuid_feature, 3031 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3032 }, 3033 { 3034 .desc = "VHE for hypervisor only", 3035 .capability = ARM64_KVM_HVHE, 3036 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3037 .matches = hvhe_possible, 3038 }, 3039 { 3040 .desc = "Enhanced Virtualization Traps", 3041 .capability = ARM64_HAS_EVT, 3042 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3043 .matches = has_cpuid_feature, 3044 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3045 }, 3046 { 3047 .desc = "BBM Level 2 without TLB conflict abort", 3048 .capability = ARM64_HAS_BBML2_NOABORT, 3049 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3050 .matches = has_bbml2_noabort, 3051 }, 3052 { 3053 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3054 .capability = ARM64_HAS_LPA2, 3055 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3056 .matches = has_lpa2, 3057 }, 3058 { 3059 .desc = "FPMR", 3060 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3061 .capability = ARM64_HAS_FPMR, 3062 .matches = has_cpuid_feature, 3063 .cpu_enable = cpu_enable_fpmr, 3064 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3065 }, 3066#ifdef CONFIG_ARM64_VA_BITS_52 3067 { 3068 .capability = ARM64_HAS_VA52, 3069 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3070 .matches = has_cpuid_feature, 3071#ifdef CONFIG_ARM64_64K_PAGES 3072 .desc = "52-bit Virtual Addressing (LVA)", 3073 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3074#else 3075 .desc = "52-bit Virtual Addressing (LPA2)", 3076#ifdef CONFIG_ARM64_4K_PAGES 3077 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3078#else 3079 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3080#endif 3081#endif 3082 }, 3083#endif 3084 { 3085 .desc = "Memory Partitioning And Monitoring", 3086 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3087 .capability = ARM64_MPAM, 3088 .matches = test_has_mpam, 3089 .cpu_enable = cpu_enable_mpam, 3090 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3091 }, 3092 { 3093 .desc = "Memory Partitioning And Monitoring Virtualisation", 3094 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3095 .capability = ARM64_MPAM_HCR, 3096 .matches = test_has_mpam_hcr, 3097 }, 3098 { 3099 .desc = "NV1", 3100 .capability = ARM64_HAS_HCR_NV1, 3101 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3102 .matches = has_nv1, 3103 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3104 }, 3105#ifdef CONFIG_ARM64_POE 3106 { 3107 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3108 .capability = ARM64_HAS_S1POE, 3109 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3110 .matches = has_cpuid_feature, 3111 .cpu_enable = cpu_enable_poe, 3112 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3113 }, 3114#endif 3115#ifdef CONFIG_ARM64_GCS 3116 { 3117 .desc = "Guarded Control Stack (GCS)", 3118 .capability = ARM64_HAS_GCS, 3119 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3120 .cpu_enable = cpu_enable_gcs, 3121 .matches = has_cpuid_feature, 3122 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3123 }, 3124#endif 3125#ifdef CONFIG_HW_PERF_EVENTS 3126 { 3127 .desc = "PMUv3", 3128 .capability = ARM64_HAS_PMUV3, 3129 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3130 .matches = has_pmuv3, 3131 }, 3132#endif 3133 { 3134 .desc = "SCTLR2", 3135 .capability = ARM64_HAS_SCTLR2, 3136 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3137 .matches = has_cpuid_feature, 3138 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3139 }, 3140 { 3141 .desc = "GICv5 CPU interface", 3142 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3143 .capability = ARM64_HAS_GICV5_CPUIF, 3144 .matches = has_cpuid_feature, 3145 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3146 }, 3147 { 3148 .desc = "GICv5 Legacy vCPU interface", 3149 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3150 .capability = ARM64_HAS_GICV5_LEGACY, 3151 .matches = test_has_gicv5_legacy, 3152 }, 3153 { 3154 .desc = "XNX", 3155 .capability = ARM64_HAS_XNX, 3156 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3157 .matches = has_cpuid_feature, 3158 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3159 }, 3160 {}, 3161}; 3162 3163#define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3164 .matches = has_user_cpuid_feature, \ 3165 ARM64_CPUID_FIELDS(reg, field, min_value) 3166 3167#define __HWCAP_CAP(name, cap_type, cap) \ 3168 .desc = name, \ 3169 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3170 .hwcap_type = cap_type, \ 3171 .hwcap = cap, \ 3172 3173#define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3174 { \ 3175 __HWCAP_CAP(#cap, cap_type, cap) \ 3176 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3177 } 3178 3179#define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3180 { \ 3181 __HWCAP_CAP(#cap, cap_type, cap) \ 3182 .matches = cpucap_multi_entry_cap_matches, \ 3183 .match_list = list, \ 3184 } 3185 3186#define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3187 { \ 3188 __HWCAP_CAP(#cap, cap_type, cap) \ 3189 .matches = match, \ 3190 } 3191 3192#define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3193 { \ 3194 __HWCAP_CAP(#cap, cap_type, cap) \ 3195 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3196 .matches = match, \ 3197 } 3198 3199#ifdef CONFIG_ARM64_PTR_AUTH 3200static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3201 { 3202 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3203 }, 3204 { 3205 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3206 }, 3207 { 3208 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3209 }, 3210 {}, 3211}; 3212 3213static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3214 { 3215 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3216 }, 3217 { 3218 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3219 }, 3220 { 3221 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3222 }, 3223 {}, 3224}; 3225#endif 3226 3227#ifdef CONFIG_ARM64_SVE 3228static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3229{ 3230 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3231} 3232#endif 3233 3234#ifdef CONFIG_ARM64_SME 3235static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3236{ 3237 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3238} 3239#endif 3240 3241static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3242 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3243 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3244 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3245 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3246 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3247 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3248 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3249 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3250 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3251 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3252 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3253 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3254 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3255 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3256 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3257 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3258 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3259 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3260 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3261 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3262 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3263 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3264 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3265 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3266 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3267 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3268 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3269 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3270 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3271 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3272 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3273 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3274 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3275 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3276 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3277 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3278 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3279 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3280 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3281 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3282 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3283#ifdef CONFIG_ARM64_SVE 3284 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3285 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3286 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3287 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3288 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3289 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3290 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3291 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3292 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3293 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3294 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3295 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3296 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3297 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3298 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3299 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3300 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3301 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3302 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3303#endif 3304#ifdef CONFIG_ARM64_GCS 3305 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3306#endif 3307 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3308#ifdef CONFIG_ARM64_BTI 3309 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3310#endif 3311#ifdef CONFIG_ARM64_PTR_AUTH 3312 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3313 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3314#endif 3315#ifdef CONFIG_ARM64_MTE 3316 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3317 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3318 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3319 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3320#endif /* CONFIG_ARM64_MTE */ 3321 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3322 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3323 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3324 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3325 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3326 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3327 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3328 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3329 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3330#ifdef CONFIG_ARM64_SME 3331 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3332 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3333 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3334 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3335 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3336 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3337 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3338 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3339 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3340 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3341 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3342 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3343 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3344 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3345 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3346 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3347 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3348 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3349 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3350 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3351 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3352 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3353 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3354 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3355 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3356 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3357#endif /* CONFIG_ARM64_SME */ 3358 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3359 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3360 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3361 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3362 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3363 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3364 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3365 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3366#ifdef CONFIG_ARM64_POE 3367 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3368#endif 3369 {}, 3370}; 3371 3372#ifdef CONFIG_COMPAT 3373static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3374{ 3375 /* 3376 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3377 * in line with that of arm32 as in vfp_init(). We make sure that the 3378 * check is future proof, by making sure value is non-zero. 3379 */ 3380 u32 mvfr1; 3381 3382 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3383 if (scope == SCOPE_SYSTEM) 3384 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3385 else 3386 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3387 3388 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3389 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3390 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3391} 3392#endif 3393 3394static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3395#ifdef CONFIG_COMPAT 3396 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3397 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3398 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3399 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3400 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3401 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3402 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3403 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3404 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3405 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3406 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3407 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3408 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3409 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3410 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3411 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3412 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3413 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3414#endif 3415 {}, 3416}; 3417 3418static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3419{ 3420 switch (cap->hwcap_type) { 3421 case CAP_HWCAP: 3422 cpu_set_feature(cap->hwcap); 3423 break; 3424#ifdef CONFIG_COMPAT 3425 case CAP_COMPAT_HWCAP: 3426 compat_elf_hwcap |= (u32)cap->hwcap; 3427 break; 3428 case CAP_COMPAT_HWCAP2: 3429 compat_elf_hwcap2 |= (u32)cap->hwcap; 3430 break; 3431#endif 3432 default: 3433 WARN_ON(1); 3434 break; 3435 } 3436} 3437 3438/* Check if we have a particular HWCAP enabled */ 3439static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3440{ 3441 bool rc; 3442 3443 switch (cap->hwcap_type) { 3444 case CAP_HWCAP: 3445 rc = cpu_have_feature(cap->hwcap); 3446 break; 3447#ifdef CONFIG_COMPAT 3448 case CAP_COMPAT_HWCAP: 3449 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3450 break; 3451 case CAP_COMPAT_HWCAP2: 3452 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3453 break; 3454#endif 3455 default: 3456 WARN_ON(1); 3457 rc = false; 3458 } 3459 3460 return rc; 3461} 3462 3463static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3464{ 3465 /* We support emulation of accesses to CPU ID feature registers */ 3466 cpu_set_named_feature(CPUID); 3467 for (; hwcaps->matches; hwcaps++) 3468 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3469 cap_set_elf_hwcap(hwcaps); 3470} 3471 3472static void update_cpu_capabilities(u16 scope_mask) 3473{ 3474 int i; 3475 const struct arm64_cpu_capabilities *caps; 3476 3477 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3478 for (i = 0; i < ARM64_NCAPS; i++) { 3479 bool match_all = false; 3480 bool caps_set = false; 3481 bool boot_cpu = false; 3482 3483 caps = cpucap_ptrs[i]; 3484 if (!caps || !(caps->type & scope_mask)) 3485 continue; 3486 3487 match_all = cpucap_match_all_early_cpus(caps); 3488 caps_set = cpus_have_cap(caps->capability); 3489 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3490 3491 /* 3492 * Unless it's a match-all CPUs feature, avoid probing if 3493 * already detected. 3494 */ 3495 if (!match_all && caps_set) 3496 continue; 3497 3498 /* 3499 * A match-all CPUs capability is only set when probing the 3500 * boot CPU. It may be cleared subsequently if not detected on 3501 * secondary ones. 3502 */ 3503 if (match_all && !caps_set && !boot_cpu) 3504 continue; 3505 3506 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3507 if (match_all) 3508 __clear_bit(caps->capability, system_cpucaps); 3509 continue; 3510 } 3511 3512 /* 3513 * Match-all CPUs capabilities are logged later when the 3514 * system capabilities are finalised. 3515 */ 3516 if (!match_all && caps->desc && !caps->cpus) 3517 pr_info("detected: %s\n", caps->desc); 3518 3519 __set_bit(caps->capability, system_cpucaps); 3520 3521 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3522 set_bit(caps->capability, boot_cpucaps); 3523 } 3524} 3525 3526/* 3527 * Enable all the available capabilities on this CPU. The capabilities 3528 * with BOOT_CPU scope are handled separately and hence skipped here. 3529 */ 3530static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3531{ 3532 int i; 3533 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3534 3535 for_each_available_cap(i) { 3536 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3537 3538 if (WARN_ON(!cap)) 3539 continue; 3540 3541 if (!(cap->type & non_boot_scope)) 3542 continue; 3543 3544 if (cap->cpu_enable) 3545 cap->cpu_enable(cap); 3546 } 3547 return 0; 3548} 3549 3550/* 3551 * Run through the enabled capabilities and enable() it on all active 3552 * CPUs 3553 */ 3554static void __init enable_cpu_capabilities(u16 scope_mask) 3555{ 3556 int i; 3557 const struct arm64_cpu_capabilities *caps; 3558 bool boot_scope; 3559 3560 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3561 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3562 3563 for (i = 0; i < ARM64_NCAPS; i++) { 3564 caps = cpucap_ptrs[i]; 3565 if (!caps || !(caps->type & scope_mask) || 3566 !cpus_have_cap(caps->capability)) 3567 continue; 3568 3569 if (boot_scope && caps->cpu_enable) 3570 /* 3571 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3572 * before any secondary CPU boots. Thus, each secondary 3573 * will enable the capability as appropriate via 3574 * check_local_cpu_capabilities(). The only exception is 3575 * the boot CPU, for which the capability must be 3576 * enabled here. This approach avoids costly 3577 * stop_machine() calls for this case. 3578 */ 3579 caps->cpu_enable(caps); 3580 } 3581 3582 /* 3583 * For all non-boot scope capabilities, use stop_machine() 3584 * as it schedules the work allowing us to modify PSTATE, 3585 * instead of on_each_cpu() which uses an IPI, giving us a 3586 * PSTATE that disappears when we return. 3587 */ 3588 if (!boot_scope) 3589 stop_machine(cpu_enable_non_boot_scope_capabilities, 3590 NULL, cpu_online_mask); 3591} 3592 3593/* 3594 * Run through the list of capabilities to check for conflicts. 3595 * If the system has already detected a capability, take necessary 3596 * action on this CPU. 3597 */ 3598static void verify_local_cpu_caps(u16 scope_mask) 3599{ 3600 int i; 3601 bool cpu_has_cap, system_has_cap; 3602 const struct arm64_cpu_capabilities *caps; 3603 3604 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3605 3606 for (i = 0; i < ARM64_NCAPS; i++) { 3607 caps = cpucap_ptrs[i]; 3608 if (!caps || !(caps->type & scope_mask)) 3609 continue; 3610 3611 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3612 system_has_cap = cpus_have_cap(caps->capability); 3613 3614 if (system_has_cap) { 3615 /* 3616 * Check if the new CPU misses an advertised feature, 3617 * which is not safe to miss. 3618 */ 3619 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3620 break; 3621 /* 3622 * We have to issue cpu_enable() irrespective of 3623 * whether the CPU has it or not, as it is enabeld 3624 * system wide. It is upto the call back to take 3625 * appropriate action on this CPU. 3626 */ 3627 if (caps->cpu_enable) 3628 caps->cpu_enable(caps); 3629 } else { 3630 /* 3631 * Check if the CPU has this capability if it isn't 3632 * safe to have when the system doesn't. 3633 */ 3634 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3635 break; 3636 } 3637 } 3638 3639 if (i < ARM64_NCAPS) { 3640 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3641 smp_processor_id(), caps->capability, 3642 caps->desc, system_has_cap, cpu_has_cap); 3643 3644 if (cpucap_panic_on_conflict(caps)) 3645 cpu_panic_kernel(); 3646 else 3647 cpu_die_early(); 3648 } 3649} 3650 3651/* 3652 * Check for CPU features that are used in early boot 3653 * based on the Boot CPU value. 3654 */ 3655static void check_early_cpu_features(void) 3656{ 3657 verify_cpu_asid_bits(); 3658 3659 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3660} 3661 3662static void 3663__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3664{ 3665 3666 for (; caps->matches; caps++) 3667 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3668 pr_crit("CPU%d: missing HWCAP: %s\n", 3669 smp_processor_id(), caps->desc); 3670 cpu_die_early(); 3671 } 3672} 3673 3674static void verify_local_elf_hwcaps(void) 3675{ 3676 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3677 3678 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3679 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3680} 3681 3682static void verify_sve_features(void) 3683{ 3684 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3685 3686 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3687 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3688 smp_processor_id()); 3689 cpu_die_early(); 3690 } 3691 3692 cpacr_restore(cpacr); 3693} 3694 3695static void verify_sme_features(void) 3696{ 3697 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3698 3699 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3700 pr_crit("CPU%d: SME: vector length support mismatch\n", 3701 smp_processor_id()); 3702 cpu_die_early(); 3703 } 3704 3705 cpacr_restore(cpacr); 3706} 3707 3708static void verify_hyp_capabilities(void) 3709{ 3710 u64 safe_mmfr1, mmfr0, mmfr1; 3711 int parange, ipa_max; 3712 unsigned int safe_vmid_bits, vmid_bits; 3713 3714 if (!IS_ENABLED(CONFIG_KVM)) 3715 return; 3716 3717 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3718 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3719 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3720 3721 /* Verify VMID bits */ 3722 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3723 vmid_bits = get_vmid_bits(mmfr1); 3724 if (vmid_bits < safe_vmid_bits) { 3725 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3726 cpu_die_early(); 3727 } 3728 3729 /* Verify IPA range */ 3730 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3731 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3732 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3733 if (ipa_max < get_kvm_ipa_limit()) { 3734 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3735 cpu_die_early(); 3736 } 3737} 3738 3739static void verify_mpam_capabilities(void) 3740{ 3741 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3742 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3743 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3744 3745 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3746 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3747 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3748 cpu_die_early(); 3749 } 3750 3751 cpu_idr = read_cpuid(MPAMIDR_EL1); 3752 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3753 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3754 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3755 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3756 cpu_die_early(); 3757 } 3758 3759 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3760 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3761 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3762 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3763 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3764 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3765 cpu_die_early(); 3766 } 3767} 3768 3769/* 3770 * Run through the enabled system capabilities and enable() it on this CPU. 3771 * The capabilities were decided based on the available CPUs at the boot time. 3772 * Any new CPU should match the system wide status of the capability. If the 3773 * new CPU doesn't have a capability which the system now has enabled, we 3774 * cannot do anything to fix it up and could cause unexpected failures. So 3775 * we park the CPU. 3776 */ 3777static void verify_local_cpu_capabilities(void) 3778{ 3779 /* 3780 * The capabilities with SCOPE_BOOT_CPU are checked from 3781 * check_early_cpu_features(), as they need to be verified 3782 * on all secondary CPUs. 3783 */ 3784 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3785 verify_local_elf_hwcaps(); 3786 3787 if (system_supports_sve()) 3788 verify_sve_features(); 3789 3790 if (system_supports_sme()) 3791 verify_sme_features(); 3792 3793 if (is_hyp_mode_available()) 3794 verify_hyp_capabilities(); 3795 3796 if (system_supports_mpam()) 3797 verify_mpam_capabilities(); 3798} 3799 3800void check_local_cpu_capabilities(void) 3801{ 3802 /* 3803 * All secondary CPUs should conform to the early CPU features 3804 * in use by the kernel based on boot CPU. 3805 */ 3806 check_early_cpu_features(); 3807 3808 /* 3809 * If we haven't finalised the system capabilities, this CPU gets 3810 * a chance to update the errata work arounds and local features. 3811 * Otherwise, this CPU should verify that it has all the system 3812 * advertised capabilities. 3813 */ 3814 if (!system_capabilities_finalized()) 3815 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3816 else 3817 verify_local_cpu_capabilities(); 3818} 3819 3820bool this_cpu_has_cap(unsigned int n) 3821{ 3822 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3823 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3824 3825 if (cap) 3826 return cap->matches(cap, SCOPE_LOCAL_CPU); 3827 } 3828 3829 return false; 3830} 3831EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3832 3833/* 3834 * This helper function is used in a narrow window when, 3835 * - The system wide safe registers are set with all the SMP CPUs and, 3836 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3837 */ 3838static bool __maybe_unused __system_matches_cap(unsigned int n) 3839{ 3840 if (n < ARM64_NCAPS) { 3841 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3842 3843 if (cap) 3844 return cap->matches(cap, SCOPE_SYSTEM); 3845 } 3846 return false; 3847} 3848 3849void cpu_set_feature(unsigned int num) 3850{ 3851 set_bit(num, elf_hwcap); 3852} 3853 3854bool cpu_have_feature(unsigned int num) 3855{ 3856 return test_bit(num, elf_hwcap); 3857} 3858EXPORT_SYMBOL_GPL(cpu_have_feature); 3859 3860unsigned long cpu_get_elf_hwcap(void) 3861{ 3862 /* 3863 * We currently only populate the first 32 bits of AT_HWCAP. Please 3864 * note that for userspace compatibility we guarantee that bits 62 3865 * and 63 will always be returned as 0. 3866 */ 3867 return elf_hwcap[0]; 3868} 3869 3870unsigned long cpu_get_elf_hwcap2(void) 3871{ 3872 return elf_hwcap[1]; 3873} 3874 3875unsigned long cpu_get_elf_hwcap3(void) 3876{ 3877 return elf_hwcap[2]; 3878} 3879 3880static void __init setup_boot_cpu_capabilities(void) 3881{ 3882 kvm_arm_target_impl_cpu_init(); 3883 /* 3884 * The boot CPU's feature register values have been recorded. Detect 3885 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3886 * patch alternatives for the available boot cpucaps. 3887 */ 3888 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3889 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3890 apply_boot_alternatives(); 3891} 3892 3893void __init setup_boot_cpu_features(void) 3894{ 3895 /* 3896 * Initialize the indirect array of CPU capabilities pointers before we 3897 * handle the boot CPU. 3898 */ 3899 init_cpucap_indirect_list(); 3900 3901 /* 3902 * Detect broken pseudo-NMI. Must be called _before_ the call to 3903 * setup_boot_cpu_capabilities() since it interacts with 3904 * can_use_gic_priorities(). 3905 */ 3906 detect_system_supports_pseudo_nmi(); 3907 3908 setup_boot_cpu_capabilities(); 3909} 3910 3911static void __init setup_system_capabilities(void) 3912{ 3913 /* 3914 * The system-wide safe feature register values have been finalized. 3915 * Detect, enable, and patch alternatives for the available system 3916 * cpucaps. 3917 */ 3918 update_cpu_capabilities(SCOPE_SYSTEM); 3919 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3920 apply_alternatives_all(); 3921 3922 for (int i = 0; i < ARM64_NCAPS; i++) { 3923 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3924 3925 if (!caps || !caps->desc) 3926 continue; 3927 3928 /* 3929 * Log any cpucaps with a cpumask as these aren't logged by 3930 * update_cpu_capabilities(). 3931 */ 3932 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3933 pr_info("detected: %s on CPU%*pbl\n", 3934 caps->desc, cpumask_pr_args(caps->cpus)); 3935 3936 /* Log match-all CPUs capabilities */ 3937 if (cpucap_match_all_early_cpus(caps) && 3938 cpus_have_cap(caps->capability)) 3939 pr_info("detected: %s\n", caps->desc); 3940 } 3941 3942 /* 3943 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3944 */ 3945 if (system_uses_ttbr0_pan()) 3946 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3947 3948 /* 3949 * Report Spectre mitigations status. 3950 */ 3951 spectre_print_disabled_mitigations(); 3952} 3953 3954void __init setup_system_features(void) 3955{ 3956 setup_system_capabilities(); 3957 3958 linear_map_maybe_split_to_ptes(); 3959 kpti_install_ng_mappings(); 3960 3961 sve_setup(); 3962 sme_setup(); 3963 3964 /* 3965 * Check for sane CTR_EL0.CWG value. 3966 */ 3967 if (!cache_type_cwg()) 3968 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3969 ARCH_DMA_MINALIGN); 3970} 3971 3972void __init setup_user_features(void) 3973{ 3974 user_feature_fixup(); 3975 3976 setup_elf_hwcaps(arm64_elf_hwcaps); 3977 3978 if (system_supports_32bit_el0()) { 3979 setup_elf_hwcaps(compat_elf_hwcaps); 3980 elf_hwcap_fixup(); 3981 } 3982 3983 minsigstksz_setup(); 3984} 3985 3986static int enable_mismatched_32bit_el0(unsigned int cpu) 3987{ 3988 /* 3989 * The first 32-bit-capable CPU we detected and so can no longer 3990 * be offlined by userspace. -1 indicates we haven't yet onlined 3991 * a 32-bit-capable CPU. 3992 */ 3993 static int lucky_winner = -1; 3994 3995 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3996 bool cpu_32bit = false; 3997 3998 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3999 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 4000 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 4001 else 4002 cpu_32bit = true; 4003 } 4004 4005 if (cpu_32bit) { 4006 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4007 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4008 } 4009 4010 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4011 return 0; 4012 4013 if (lucky_winner >= 0) 4014 return 0; 4015 4016 /* 4017 * We've detected a mismatch. We need to keep one of our CPUs with 4018 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4019 * every CPU in the system for a 32-bit task. 4020 */ 4021 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4022 cpu_active_mask); 4023 get_cpu_device(lucky_winner)->offline_disabled = true; 4024 setup_elf_hwcaps(compat_elf_hwcaps); 4025 elf_hwcap_fixup(); 4026 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4027 cpu, lucky_winner); 4028 return 0; 4029} 4030 4031static int __init init_32bit_el0_mask(void) 4032{ 4033 if (!allow_mismatched_32bit_el0) 4034 return 0; 4035 4036 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4037 return -ENOMEM; 4038 4039 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4040 "arm64/mismatched_32bit_el0:online", 4041 enable_mismatched_32bit_el0, NULL); 4042} 4043subsys_initcall_sync(init_32bit_el0_mask); 4044 4045static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4046{ 4047 cpu_enable_swapper_cnp(); 4048} 4049 4050/* 4051 * We emulate only the following system register space. 4052 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4053 * See Table C5-6 System instruction encodings for System register accesses, 4054 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4055 */ 4056static inline bool __attribute_const__ is_emulated(u32 id) 4057{ 4058 return (sys_reg_Op0(id) == 0x3 && 4059 sys_reg_CRn(id) == 0x0 && 4060 sys_reg_Op1(id) == 0x0 && 4061 (sys_reg_CRm(id) == 0 || 4062 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4063} 4064 4065/* 4066 * With CRm == 0, reg should be one of : 4067 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4068 */ 4069static inline int emulate_id_reg(u32 id, u64 *valp) 4070{ 4071 switch (id) { 4072 case SYS_MIDR_EL1: 4073 *valp = read_cpuid_id(); 4074 break; 4075 case SYS_MPIDR_EL1: 4076 *valp = SYS_MPIDR_SAFE_VAL; 4077 break; 4078 case SYS_REVIDR_EL1: 4079 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4080 *valp = 0; 4081 break; 4082 default: 4083 return -EINVAL; 4084 } 4085 4086 return 0; 4087} 4088 4089static int emulate_sys_reg(u32 id, u64 *valp) 4090{ 4091 struct arm64_ftr_reg *regp; 4092 4093 if (!is_emulated(id)) 4094 return -EINVAL; 4095 4096 if (sys_reg_CRm(id) == 0) 4097 return emulate_id_reg(id, valp); 4098 4099 regp = get_arm64_ftr_reg_nowarn(id); 4100 if (regp) 4101 *valp = arm64_ftr_reg_user_value(regp); 4102 else 4103 /* 4104 * The untracked registers are either IMPLEMENTATION DEFINED 4105 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4106 */ 4107 *valp = 0; 4108 return 0; 4109} 4110 4111int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4112{ 4113 int rc; 4114 u64 val; 4115 4116 rc = emulate_sys_reg(sys_reg, &val); 4117 if (!rc) { 4118 pt_regs_write_reg(regs, rt, val); 4119 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4120 } 4121 return rc; 4122} 4123 4124bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4125{ 4126 u32 sys_reg, rt; 4127 4128 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4129 return false; 4130 4131 /* 4132 * sys_reg values are defined as used in mrs/msr instruction. 4133 * shift the imm value to get the encoding. 4134 */ 4135 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4136 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4137 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4138} 4139 4140enum mitigation_state arm64_get_meltdown_state(void) 4141{ 4142 if (__meltdown_safe) 4143 return SPECTRE_UNAFFECTED; 4144 4145 if (arm64_kernel_unmapped_at_el0()) 4146 return SPECTRE_MITIGATED; 4147 4148 return SPECTRE_VULNERABLE; 4149} 4150 4151ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4152 char *buf) 4153{ 4154 switch (arm64_get_meltdown_state()) { 4155 case SPECTRE_UNAFFECTED: 4156 return sprintf(buf, "Not affected\n"); 4157 4158 case SPECTRE_MITIGATED: 4159 return sprintf(buf, "Mitigation: PTI\n"); 4160 4161 default: 4162 return sprintf(buf, "Vulnerable\n"); 4163 } 4164}
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