traps.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Based on arch/arm/include/asm/traps.h
  4 *
  5 * Copyright (C) 2012 ARM Ltd.
  6 */
  7#ifndef __ASM_TRAP_H
  8#define __ASM_TRAP_H
  9
 10#include <linux/list.h>
 11#include <asm/esr.h>
 12#include <asm/ptrace.h>
 13#include <asm/sections.h>
 14
 15#ifdef CONFIG_ARMV8_DEPRECATED
 16bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn);
 17#else
 18static inline bool
 19try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn)
 20{
 21	return false;
 22}
 23#endif /* CONFIG_ARMV8_DEPRECATED */
 24
 25void force_signal_inject(int signal, int code, unsigned long address, unsigned long err);
 26void arm64_notify_segfault(unsigned long addr);
 27void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);
 28void arm64_force_sig_fault_pkey(unsigned long far, const char *str, int pkey);
 29void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
 30void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str);
 31
 32int bug_brk_handler(struct pt_regs *regs, unsigned long esr);
 33int cfi_brk_handler(struct pt_regs *regs, unsigned long esr);
 34int reserved_fault_brk_handler(struct pt_regs *regs, unsigned long esr);
 35int kasan_brk_handler(struct pt_regs *regs, unsigned long esr);
 36int ubsan_brk_handler(struct pt_regs *regs, unsigned long esr);
 37
 38int early_brk64(unsigned long addr, unsigned long esr, struct pt_regs *regs);
 39void dump_kernel_instr(unsigned long kaddr);
 40
 41/*
 42 * Move regs->pc to next instruction and do necessary setup before it
 43 * is executed.
 44 */
 45void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
 46
 47static inline int __in_irqentry_text(unsigned long ptr)
 48{
 49	return ptr >= (unsigned long)&__irqentry_text_start &&
 50	       ptr < (unsigned long)&__irqentry_text_end;
 51}
 52
 53static inline int in_entry_text(unsigned long ptr)
 54{
 55	return ptr >= (unsigned long)&__entry_text_start &&
 56	       ptr < (unsigned long)&__entry_text_end;
 57}
 58
 59/*
 60 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
 61 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
 62 * have a ISS-Valid bit in the same position.
 63 * If this bit is set, we know its not a RAS SError.
 64 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
 65 * errors share the same encoding as an all-zeros encoding from a CPU that
 66 * doesn't support RAS.
 67 */
 68static inline bool arm64_is_ras_serror(unsigned long esr)
 69{
 70	WARN_ON(preemptible());
 71
 72	if (esr & ESR_ELx_IDS)
 73		return false;
 74
 75	if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
 76		return true;
 77	else
 78		return false;
 79}
 80
 81/*
 82 * Return the AET bits from a RAS SError's ESR.
 83 *
 84 * It is implementation defined whether Uncategorized errors are containable.
 85 * We treat them as Uncontainable.
 86 * Non-RAS SError's are reported as Uncontained/Uncategorized.
 87 */
 88static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)
 89{
 90	unsigned long aet = esr & ESR_ELx_AET;
 91
 92	if (!arm64_is_ras_serror(esr)) {
 93		/* Not a RAS error, we can't interpret the ESR. */
 94		return ESR_ELx_AET_UC;
 95	}
 96
 97	/*
 98	 * AET is RES0 if 'the value returned in the DFSC field is not
 99	 * [ESR_ELx_FSC_SERROR]'
100	 */
101	if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
102		/* No severity information : Uncategorized */
103		return ESR_ELx_AET_UC;
104	}
105
106	return aet;
107}
108
109bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);
110void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);
111
112static inline void arm64_mops_reset_regs(struct user_pt_regs *regs, unsigned long esr)
113{
114	bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION;
115	bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A;
116	int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr);
117	int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr);
118	int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr);
119	unsigned long dst, size;
120
121	dst = regs->regs[dstreg];
122	size = regs->regs[sizereg];
123
124	/*
125	 * Put the registers back in the original format suitable for a
126	 * prologue instruction, using the generic return routine from the
127	 * Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH.
128	 */
129	if (esr & ESR_ELx_MOPS_ISS_MEM_INST) {
130		/* SET* instruction */
131		if (option_a ^ wrong_option) {
132			/* Format is from Option A; forward set */
133			regs->regs[dstreg] = dst + size;
134			regs->regs[sizereg] = -size;
135		}
136	} else {
137		/* CPY* instruction */
138		unsigned long src = regs->regs[srcreg];
139		if (!(option_a ^ wrong_option)) {
140			/* Format is from Option B */
141			if (regs->pstate & PSR_N_BIT) {
142				/* Backward copy */
143				regs->regs[dstreg] = dst - size;
144				regs->regs[srcreg] = src - size;
145			}
146		} else {
147			/* Format is from Option A */
148			if (size & BIT(63)) {
149				/* Forward copy */
150				regs->regs[dstreg] = dst + size;
151				regs->regs[srcreg] = src + size;
152				regs->regs[sizereg] = -size;
153			}
154		}
155	}
156
157	if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE)
158		regs->pc -= 8;
159	else
160		regs->pc -= 4;
161}
162#endif