File Index
Files and directories
Sign in
FILE

sysreg.h

File preview with syntax highlighting.

linux-6.19.14/arch/arm64/include/asm/sysreg.h C 
   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Macros for accessing system registers with older binutils.
   4 *
   5 * Copyright (C) 2014 ARM Ltd.
   6 * Author: Catalin Marinas <catalin.marinas@arm.com>
   7 */
   8
   9#ifndef __ASM_SYSREG_H
  10#define __ASM_SYSREG_H
  11
  12#include <linux/bits.h>
  13#include <linux/stringify.h>
  14#include <linux/kasan-tags.h>
  15#include <linux/kconfig.h>
  16
  17#include <asm/gpr-num.h>
  18
  19/*
  20 * ARMv8 ARM reserves the following encoding for system registers:
  21 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
  22 *  C5.2, version:ARM DDI 0487A.f)
  23 *	[20-19] : Op0
  24 *	[18-16] : Op1
  25 *	[15-12] : CRn
  26 *	[11-8]  : CRm
  27 *	[7-5]   : Op2
  28 */
  29#define Op0_shift	19
  30#define Op0_mask	0x3
  31#define Op1_shift	16
  32#define Op1_mask	0x7
  33#define CRn_shift	12
  34#define CRn_mask	0xf
  35#define CRm_shift	8
  36#define CRm_mask	0xf
  37#define Op2_shift	5
  38#define Op2_mask	0x7
  39
  40#define sys_reg(op0, op1, crn, crm, op2) \
  41	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
  42	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
  43	 ((op2) << Op2_shift))
  44
  45#define sys_insn	sys_reg
  46
  47#define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
  48#define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
  49#define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
  50#define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
  51#define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
  52
  53#ifndef CONFIG_BROKEN_GAS_INST
  54
  55#ifdef __ASSEMBLER__
  56// The space separator is omitted so that __emit_inst(x) can be parsed as
  57// either an assembler directive or an assembler macro argument.
  58#define __emit_inst(x)			.inst(x)
  59#else
  60#define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
  61#endif
  62
  63#else  /* CONFIG_BROKEN_GAS_INST */
  64
  65#ifndef CONFIG_CPU_BIG_ENDIAN
  66#define __INSTR_BSWAP(x)		(x)
  67#else  /* CONFIG_CPU_BIG_ENDIAN */
  68#define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
  69					 (((x) <<  8) & 0x00ff0000)	| \
  70					 (((x) >>  8) & 0x0000ff00)	| \
  71					 (((x) >> 24) & 0x000000ff))
  72#endif	/* CONFIG_CPU_BIG_ENDIAN */
  73
  74#ifdef __ASSEMBLER__
  75#define __emit_inst(x)			.long __INSTR_BSWAP(x)
  76#else  /* __ASSEMBLER__ */
  77#define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
  78#endif	/* __ASSEMBLER__ */
  79
  80#endif	/* CONFIG_BROKEN_GAS_INST */
  81
  82/*
  83 * Instructions for modifying PSTATE fields.
  84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
  85 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
  86 * for accessing PSTATE fields have the following encoding:
  87 *	Op0 = 0, CRn = 4
  88 *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
  89 *	CRm = Imm4 for the instruction.
  90 *	Rt = 0x1f
  91 */
  92#define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
  93#define PSTATE_Imm_shift		CRm_shift
  94#define ENCODE_PSTATE(x, r)		(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
  95#define SET_PSTATE(x, r)		__emit_inst(ENCODE_PSTATE(x, r))
  96
  97#define PSTATE_PAN			pstate_field(0, 4)
  98#define PSTATE_UAO			pstate_field(0, 3)
  99#define PSTATE_SSBS			pstate_field(3, 1)
 100#define PSTATE_DIT			pstate_field(3, 2)
 101#define PSTATE_TCO			pstate_field(3, 4)
 102
 103#define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
 104#define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
 105#define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
 106#define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
 107#define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
 108
 109#define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
 110#define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
 111#define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
 112#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
 113
 114/* Register-based PAN access, for save/restore purposes */
 115#define SYS_PSTATE_PAN			sys_reg(3, 0, 4, 2, 3)
 116
 117#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt)			\
 118	__emit_inst(0xd5000000					|	\
 119		    sys_insn((op0), (op1), (CRn), (CRm), (op2))	|	\
 120		    ((Rt) & 0x1f))
 121
 122#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
 123#define GSB_SYS_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)
 124#define GSB_ACK_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)
 125
 126/* Data cache zero operations */
 127#define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
 128#define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
 129#define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
 130#define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
 131#define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
 132#define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
 133#define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
 134#define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
 135#define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
 136
 137#define SYS_IC_IALLUIS			sys_insn(1, 0, 7, 1, 0)
 138#define SYS_IC_IALLU			sys_insn(1, 0, 7, 5, 0)
 139#define SYS_IC_IVAU			sys_insn(1, 3, 7, 5, 1)
 140
 141#define SYS_DC_IVAC			sys_insn(1, 0, 7, 6, 1)
 142#define SYS_DC_IGVAC			sys_insn(1, 0, 7, 6, 3)
 143#define SYS_DC_IGDVAC			sys_insn(1, 0, 7, 6, 5)
 144
 145#define SYS_DC_CVAC			sys_insn(1, 3, 7, 10, 1)
 146#define SYS_DC_CGVAC			sys_insn(1, 3, 7, 10, 3)
 147#define SYS_DC_CGDVAC			sys_insn(1, 3, 7, 10, 5)
 148
 149#define SYS_DC_CVAU			sys_insn(1, 3, 7, 11, 1)
 150
 151#define SYS_DC_CVAP			sys_insn(1, 3, 7, 12, 1)
 152#define SYS_DC_CGVAP			sys_insn(1, 3, 7, 12, 3)
 153#define SYS_DC_CGDVAP			sys_insn(1, 3, 7, 12, 5)
 154
 155#define SYS_DC_CVADP			sys_insn(1, 3, 7, 13, 1)
 156#define SYS_DC_CGVADP			sys_insn(1, 3, 7, 13, 3)
 157#define SYS_DC_CGDVADP			sys_insn(1, 3, 7, 13, 5)
 158
 159#define SYS_DC_CIVAC			sys_insn(1, 3, 7, 14, 1)
 160#define SYS_DC_CIGVAC			sys_insn(1, 3, 7, 14, 3)
 161#define SYS_DC_CIGDVAC			sys_insn(1, 3, 7, 14, 5)
 162
 163#define SYS_DC_ZVA			sys_insn(1, 3, 7, 4, 1)
 164#define SYS_DC_GVA			sys_insn(1, 3, 7, 4, 3)
 165#define SYS_DC_GZVA			sys_insn(1, 3, 7, 4, 4)
 166
 167#define SYS_DC_CIVAPS			sys_insn(1, 0, 7, 15, 1)
 168#define SYS_DC_CIGDVAPS			sys_insn(1, 0, 7, 15, 5)
 169
 170/*
 171 * Automatically generated definitions for system registers, the
 172 * manual encodings below are in the process of being converted to
 173 * come from here. The header relies on the definition of sys_reg()
 174 * earlier in this file.
 175 */
 176#include "asm/sysreg-defs.h"
 177
 178/*
 179 * System registers, organised loosely by encoding but grouped together
 180 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
 181 */
 182#define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
 183#define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
 184#define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
 185
 186#define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
 187#define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
 188#define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
 189#define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
 190#define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
 191
 192#define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
 193#define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
 194#define OSLSR_EL1_OSLM_NI		0
 195#define OSLSR_EL1_OSLM_IMPLEMENTED	BIT(3)
 196#define OSLSR_EL1_OSLK			BIT(1)
 197
 198#define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
 199#define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
 200#define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
 201#define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
 202#define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
 203#define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
 204#define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
 205#define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
 206#define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
 207#define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
 208
 209#define SYS_BRBINF_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
 210#define SYS_BRBSRC_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
 211#define SYS_BRBTGT_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
 212
 213#define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
 214#define SYS_TRCACATR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
 215#define SYS_TRCACVR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
 216#define SYS_TRCAUTHSTATUS		sys_reg(2, 1, 7, 14, 6)
 217#define SYS_TRCAUXCTLR			sys_reg(2, 1, 0, 6, 0)
 218#define SYS_TRCBBCTLR			sys_reg(2, 1, 0, 15, 0)
 219#define SYS_TRCCCCTLR			sys_reg(2, 1, 0, 14, 0)
 220#define SYS_TRCCIDCCTLR0		sys_reg(2, 1, 3, 0, 2)
 221#define SYS_TRCCIDCCTLR1		sys_reg(2, 1, 3, 1, 2)
 222#define SYS_TRCCIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 0)
 223#define SYS_TRCCLAIMCLR			sys_reg(2, 1, 7, 9, 6)
 224#define SYS_TRCCLAIMSET			sys_reg(2, 1, 7, 8, 6)
 225#define SYS_TRCCNTCTLR(m)		sys_reg(2, 1, 0, (4 | (m & 3)), 5)
 226#define SYS_TRCCNTRLDVR(m)		sys_reg(2, 1, 0, (0 | (m & 3)), 5)
 227#define SYS_TRCCNTVR(m)			sys_reg(2, 1, 0, (8 | (m & 3)), 5)
 228#define SYS_TRCCONFIGR			sys_reg(2, 1, 0, 4, 0)
 229#define SYS_TRCDEVARCH			sys_reg(2, 1, 7, 15, 6)
 230#define SYS_TRCDEVID			sys_reg(2, 1, 7, 2, 7)
 231#define SYS_TRCEVENTCTL0R		sys_reg(2, 1, 0, 8, 0)
 232#define SYS_TRCEVENTCTL1R		sys_reg(2, 1, 0, 9, 0)
 233#define SYS_TRCEXTINSELR(m)		sys_reg(2, 1, 0, (8 | (m & 3)), 4)
 234#define SYS_TRCIDR0			sys_reg(2, 1, 0, 8, 7)
 235#define SYS_TRCIDR10			sys_reg(2, 1, 0, 2, 6)
 236#define SYS_TRCIDR11			sys_reg(2, 1, 0, 3, 6)
 237#define SYS_TRCIDR12			sys_reg(2, 1, 0, 4, 6)
 238#define SYS_TRCIDR13			sys_reg(2, 1, 0, 5, 6)
 239#define SYS_TRCIDR1			sys_reg(2, 1, 0, 9, 7)
 240#define SYS_TRCIDR2			sys_reg(2, 1, 0, 10, 7)
 241#define SYS_TRCIDR3			sys_reg(2, 1, 0, 11, 7)
 242#define SYS_TRCIDR4			sys_reg(2, 1, 0, 12, 7)
 243#define SYS_TRCIDR5			sys_reg(2, 1, 0, 13, 7)
 244#define SYS_TRCIDR6			sys_reg(2, 1, 0, 14, 7)
 245#define SYS_TRCIDR7			sys_reg(2, 1, 0, 15, 7)
 246#define SYS_TRCIDR8			sys_reg(2, 1, 0, 0, 6)
 247#define SYS_TRCIDR9			sys_reg(2, 1, 0, 1, 6)
 248#define SYS_TRCIMSPEC(m)		sys_reg(2, 1, 0, (m & 7), 7)
 249#define SYS_TRCITEEDCR			sys_reg(2, 1, 0, 2, 1)
 250#define SYS_TRCOSLSR			sys_reg(2, 1, 1, 1, 4)
 251#define SYS_TRCPRGCTLR			sys_reg(2, 1, 0, 1, 0)
 252#define SYS_TRCQCTLR			sys_reg(2, 1, 0, 1, 1)
 253#define SYS_TRCRSCTLR(m)		sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
 254#define SYS_TRCRSR			sys_reg(2, 1, 0, 10, 0)
 255#define SYS_TRCSEQEVR(m)		sys_reg(2, 1, 0, (m & 3), 4)
 256#define SYS_TRCSEQRSTEVR		sys_reg(2, 1, 0, 6, 4)
 257#define SYS_TRCSEQSTR			sys_reg(2, 1, 0, 7, 4)
 258#define SYS_TRCSSCCR(m)			sys_reg(2, 1, 1, (m & 7), 2)
 259#define SYS_TRCSSCSR(m)			sys_reg(2, 1, 1, (8 | (m & 7)), 2)
 260#define SYS_TRCSSPCICR(m)		sys_reg(2, 1, 1, (m & 7), 3)
 261#define SYS_TRCSTALLCTLR		sys_reg(2, 1, 0, 11, 0)
 262#define SYS_TRCSTATR			sys_reg(2, 1, 0, 3, 0)
 263#define SYS_TRCSYNCPR			sys_reg(2, 1, 0, 13, 0)
 264#define SYS_TRCTRACEIDR			sys_reg(2, 1, 0, 0, 1)
 265#define SYS_TRCTSCTLR			sys_reg(2, 1, 0, 12, 0)
 266#define SYS_TRCVICTLR			sys_reg(2, 1, 0, 0, 2)
 267#define SYS_TRCVIIECTLR			sys_reg(2, 1, 0, 1, 2)
 268#define SYS_TRCVIPCSSCTLR		sys_reg(2, 1, 0, 3, 2)
 269#define SYS_TRCVISSCTLR			sys_reg(2, 1, 0, 2, 2)
 270#define SYS_TRCVMIDCCTLR0		sys_reg(2, 1, 3, 2, 2)
 271#define SYS_TRCVMIDCCTLR1		sys_reg(2, 1, 3, 3, 2)
 272#define SYS_TRCVMIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 1)
 273
 274/* ETM */
 275#define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)
 276
 277#define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
 278#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
 279#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
 280
 281#define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
 282#define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
 283#define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
 284
 285#define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
 286#define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
 287#define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
 288#define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
 289
 290#define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
 291#define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
 292#define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
 293#define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
 294
 295#define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
 296#define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
 297
 298#define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
 299#define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
 300
 301#define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
 302
 303#define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
 304#define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
 305#define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
 306
 307#define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
 308#define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
 309#define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
 310#define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
 311#define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
 312#define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
 313#define SYS_ERXPFGF_EL1			sys_reg(3, 0, 5, 4, 4)
 314#define SYS_ERXPFGCTL_EL1		sys_reg(3, 0, 5, 4, 5)
 315#define SYS_ERXPFGCDN_EL1		sys_reg(3, 0, 5, 4, 6)
 316#define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
 317#define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
 318#define SYS_ERXMISC2_EL1		sys_reg(3, 0, 5, 5, 2)
 319#define SYS_ERXMISC3_EL1		sys_reg(3, 0, 5, 5, 3)
 320#define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
 321#define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
 322
 323#define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
 324
 325#define SYS_PAR_EL1_F			BIT(0)
 326/* When PAR_EL1.F == 1 */
 327#define SYS_PAR_EL1_FST			GENMASK(6, 1)
 328#define SYS_PAR_EL1_PTW			BIT(8)
 329#define SYS_PAR_EL1_S			BIT(9)
 330#define SYS_PAR_EL1_AssuredOnly		BIT(12)
 331#define SYS_PAR_EL1_TopLevel		BIT(13)
 332#define SYS_PAR_EL1_Overlay		BIT(14)
 333#define SYS_PAR_EL1_DirtyBit		BIT(15)
 334#define SYS_PAR_EL1_F1_IMPDEF		GENMASK_ULL(63, 48)
 335#define SYS_PAR_EL1_F1_RES0		(BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
 336#define SYS_PAR_EL1_RES1		BIT(11)
 337/* When PAR_EL1.F == 0 */
 338#define SYS_PAR_EL1_SH			GENMASK_ULL(8, 7)
 339#define SYS_PAR_EL1_NS			BIT(9)
 340#define SYS_PAR_EL1_F0_IMPDEF		BIT(10)
 341#define SYS_PAR_EL1_NSE			BIT(11)
 342#define SYS_PAR_EL1_PA			GENMASK_ULL(51, 12)
 343#define SYS_PAR_EL1_ATTR		GENMASK_ULL(63, 56)
 344#define SYS_PAR_EL1_F0_RES0		(GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
 345
 346/* Buffer error reporting */
 347#define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
 348#define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
 349
 350#define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
 351#define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
 352
 353#define PMBSR_EL1_BUF_BSC_FULL		0x1UL
 354
 355/*** End of Statistical Profiling Extension ***/
 356
 357#define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
 358#define TRBSR_EL1_BSC_SHIFT		0
 359
 360#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 361#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
 362
 363#define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
 364
 365#define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
 366#define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
 367
 368#define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
 369#define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
 370
 371#define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
 372#define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
 373#define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
 374#define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
 375#define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
 376#define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
 377#define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
 378#define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
 379#define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
 380#define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
 381#define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
 382#define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
 383#define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
 384#define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
 385#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
 386#define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
 387#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
 388#define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
 389#define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
 390#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
 391#define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
 392#define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
 393#define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
 394#define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
 395#define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
 396#define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
 397#define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
 398
 399#define SYS_ACCDATA_EL1			sys_reg(3, 0, 13, 0, 5)
 400
 401#define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
 402
 403#define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
 404
 405#define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
 406#define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 407
 408#define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
 409#define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
 410#define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
 411#define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
 412#define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
 413#define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
 414#define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
 415#define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
 416#define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
 417#define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
 418#define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
 419#define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
 420
 421#define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
 422#define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
 423#define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
 424
 425#define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
 426
 427/* Definitions for system register interface to AMU for ARMv8.4 onwards */
 428#define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
 429#define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
 430#define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
 431#define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
 432#define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
 433#define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
 434#define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
 435#define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
 436#define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
 437
 438/*
 439 * Group 0 of activity monitors (architected):
 440 *                op0  op1  CRn   CRm       op2
 441 * Counter:       11   011  1101  010:n<3>  n<2:0>
 442 * Type:          11   011  1101  011:n<3>  n<2:0>
 443 * n: 0-15
 444 *
 445 * Group 1 of activity monitors (auxiliary):
 446 *                op0  op1  CRn   CRm       op2
 447 * Counter:       11   011  1101  110:n<3>  n<2:0>
 448 * Type:          11   011  1101  111:n<3>  n<2:0>
 449 * n: 0-15
 450 */
 451
 452#define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
 453#define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
 454#define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
 455#define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
 456
 457/* AMU v1: Fixed (architecturally defined) activity monitors */
 458#define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
 459#define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
 460#define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
 461#define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
 462
 463#define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
 464
 465#define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
 466#define SYS_CNTVCT_EL0			sys_reg(3, 3, 14, 0, 2)
 467#define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
 468#define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
 469
 470#define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
 471#define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
 472#define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
 473
 474#define SYS_CNTV_TVAL_EL0		sys_reg(3, 3, 14, 3, 0)
 475#define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
 476#define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
 477
 478#define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
 479#define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
 480#define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
 481#define SYS_AARCH32_CNTVCT		sys_reg(0, 1, 0, 14, 0)
 482#define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
 483#define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
 484#define SYS_AARCH32_CNTVCTSS		sys_reg(0, 9, 0, 14, 0)
 485
 486#define __PMEV_op2(n)			((n) & 0x7)
 487#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
 488#define SYS_PMEVCNTSVRn_EL1(n)		sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
 489#define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
 490#define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
 491#define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
 492
 493#define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
 494
 495#define	SYS_SPMCGCRn_EL1(n)		sys_reg(2, 0, 9, 13, ((n) & 1))
 496
 497#define __SPMEV_op2(n)			((n) & 0x7)
 498#define __SPMEV_crm(p, n)		((((p) & 7) << 1) | (((n) >> 3) & 1))
 499#define SYS_SPMEVCNTRn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
 500#define	SYS_SPMEVFILT2Rn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
 501#define	SYS_SPMEVFILTRn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
 502#define	SYS_SPMEVTYPERn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
 503
 504#define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
 505#define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
 506
 507#define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
 508#define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
 509#define SYS_SCTLR2_EL2			sys_reg(3, 4, 1, 0, 3)
 510#define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
 511#define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
 512#define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
 513#define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
 514#define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
 515
 516#define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
 517#define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
 518#define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
 519#define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
 520#define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
 521
 522#define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
 523#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
 524#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
 525#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
 526#define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)
 527#define SYS_SPSR_abt			sys_reg(3, 4, 4, 3, 1)
 528#define SYS_SPSR_und			sys_reg(3, 4, 4, 3, 2)
 529#define SYS_SPSR_fiq			sys_reg(3, 4, 4, 3, 3)
 530#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
 531#define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
 532#define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
 533#define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
 534#define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
 535#define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
 536#define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
 537
 538#define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
 539#define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
 540
 541#define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
 542#define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
 543
 544#define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
 545#define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
 546#define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
 547#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
 548#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
 549#define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
 550#define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
 551#define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
 552#define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
 553
 554#define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
 555#define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
 556#define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
 557#define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
 558#define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
 559
 560#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
 561#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
 562#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
 563#define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
 564#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
 565
 566#define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
 567#define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
 568#define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
 569#define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
 570#define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
 571#define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
 572#define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
 573#define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
 574#define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
 575
 576#define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
 577#define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
 578#define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
 579#define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
 580#define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
 581#define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
 582#define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
 583#define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
 584#define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
 585
 586#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
 587#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
 588#define SYS_SCXTNUM_EL2			sys_reg(3, 4, 13, 0, 7)
 589
 590#define __AMEV_op2(m)			(m & 0x7)
 591#define __AMEV_CRm(n, m)		(n | ((m & 0x8) >> 3))
 592#define __SYS__AMEVCNTVOFF0n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
 593#define SYS_AMEVCNTVOFF0n_EL2(m)	__SYS__AMEVCNTVOFF0n_EL2(m)
 594#define __SYS__AMEVCNTVOFF1n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
 595#define SYS_AMEVCNTVOFF1n_EL2(m)	__SYS__AMEVCNTVOFF1n_EL2(m)
 596
 597#define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
 598#define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
 599#define SYS_CNTHP_TVAL_EL2		sys_reg(3, 4, 14, 2, 0)
 600#define SYS_CNTHP_CTL_EL2		sys_reg(3, 4, 14, 2, 1)
 601#define SYS_CNTHP_CVAL_EL2		sys_reg(3, 4, 14, 2, 2)
 602#define SYS_CNTHV_TVAL_EL2		sys_reg(3, 4, 14, 3, 0)
 603#define SYS_CNTHV_CTL_EL2		sys_reg(3, 4, 14, 3, 1)
 604#define SYS_CNTHV_CVAL_EL2		sys_reg(3, 4, 14, 3, 2)
 605
 606/* VHE encodings for architectural EL0/1 system registers */
 607#define SYS_BRBCR_EL12			sys_reg(2, 5, 9, 0, 0)
 608#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
 609#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
 610#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
 611#define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
 612#define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
 613#define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
 614#define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
 615#define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
 616#define SYS_PMSCR_EL12			sys_reg(3, 5, 9, 9, 0)
 617#define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
 618#define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
 619#define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
 620#define SYS_SCXTNUM_EL12		sys_reg(3, 5, 13, 0, 7)
 621#define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
 622#define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
 623#define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
 624#define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
 625#define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
 626#define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
 627#define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
 628
 629#define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
 630
 631/* AT instructions */
 632#define AT_Op0 1
 633#define AT_CRn 7
 634
 635#define OP_AT_S1E1R	sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
 636#define OP_AT_S1E1W	sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
 637#define OP_AT_S1E0R	sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
 638#define OP_AT_S1E0W	sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
 639#define OP_AT_S1E1RP	sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
 640#define OP_AT_S1E1WP	sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
 641#define OP_AT_S1E1A	sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
 642#define OP_AT_S1E2R	sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
 643#define OP_AT_S1E2W	sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
 644#define OP_AT_S12E1R	sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
 645#define OP_AT_S12E1W	sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
 646#define OP_AT_S12E0R	sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
 647#define OP_AT_S12E0W	sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
 648#define OP_AT_S1E2A	sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
 649
 650/* TLBI instructions */
 651#define TLBI_Op0	1
 652
 653#define TLBI_Op1_EL1	0	/* Accessible from EL1 or higher */
 654#define TLBI_Op1_EL2	4	/* Accessible from EL2 or higher */
 655
 656#define TLBI_CRn_XS	8	/* Extra Slow (the common one) */
 657#define TLBI_CRn_nXS	9	/* not Extra Slow (which nobody uses)*/
 658
 659#define TLBI_CRm_IPAIS	0	/* S2 Inner-Shareable */
 660#define TLBI_CRm_nROS	1	/* non-Range, Outer-Sharable */
 661#define TLBI_CRm_RIS	2	/* Range, Inner-Sharable */
 662#define TLBI_CRm_nRIS	3	/* non-Range, Inner-Sharable */
 663#define TLBI_CRm_IPAONS	4	/* S2 Outer and Non-Shareable */
 664#define TLBI_CRm_ROS	5	/* Range, Outer-Sharable */
 665#define TLBI_CRm_RNS	6	/* Range, Non-Sharable */
 666#define TLBI_CRm_nRNS	7	/* non-Range, Non-Sharable */
 667
 668#define OP_TLBI_VMALLE1OS		sys_insn(1, 0, 8, 1, 0)
 669#define OP_TLBI_VAE1OS			sys_insn(1, 0, 8, 1, 1)
 670#define OP_TLBI_ASIDE1OS		sys_insn(1, 0, 8, 1, 2)
 671#define OP_TLBI_VAAE1OS			sys_insn(1, 0, 8, 1, 3)
 672#define OP_TLBI_VALE1OS			sys_insn(1, 0, 8, 1, 5)
 673#define OP_TLBI_VAALE1OS		sys_insn(1, 0, 8, 1, 7)
 674#define OP_TLBI_RVAE1IS			sys_insn(1, 0, 8, 2, 1)
 675#define OP_TLBI_RVAAE1IS		sys_insn(1, 0, 8, 2, 3)
 676#define OP_TLBI_RVALE1IS		sys_insn(1, 0, 8, 2, 5)
 677#define OP_TLBI_RVAALE1IS		sys_insn(1, 0, 8, 2, 7)
 678#define OP_TLBI_VMALLE1IS		sys_insn(1, 0, 8, 3, 0)
 679#define OP_TLBI_VAE1IS			sys_insn(1, 0, 8, 3, 1)
 680#define OP_TLBI_ASIDE1IS		sys_insn(1, 0, 8, 3, 2)
 681#define OP_TLBI_VAAE1IS			sys_insn(1, 0, 8, 3, 3)
 682#define OP_TLBI_VALE1IS			sys_insn(1, 0, 8, 3, 5)
 683#define OP_TLBI_VAALE1IS		sys_insn(1, 0, 8, 3, 7)
 684#define OP_TLBI_RVAE1OS			sys_insn(1, 0, 8, 5, 1)
 685#define OP_TLBI_RVAAE1OS		sys_insn(1, 0, 8, 5, 3)
 686#define OP_TLBI_RVALE1OS		sys_insn(1, 0, 8, 5, 5)
 687#define OP_TLBI_RVAALE1OS		sys_insn(1, 0, 8, 5, 7)
 688#define OP_TLBI_RVAE1			sys_insn(1, 0, 8, 6, 1)
 689#define OP_TLBI_RVAAE1			sys_insn(1, 0, 8, 6, 3)
 690#define OP_TLBI_RVALE1			sys_insn(1, 0, 8, 6, 5)
 691#define OP_TLBI_RVAALE1			sys_insn(1, 0, 8, 6, 7)
 692#define OP_TLBI_VMALLE1			sys_insn(1, 0, 8, 7, 0)
 693#define OP_TLBI_VAE1			sys_insn(1, 0, 8, 7, 1)
 694#define OP_TLBI_ASIDE1			sys_insn(1, 0, 8, 7, 2)
 695#define OP_TLBI_VAAE1			sys_insn(1, 0, 8, 7, 3)
 696#define OP_TLBI_VALE1			sys_insn(1, 0, 8, 7, 5)
 697#define OP_TLBI_VAALE1			sys_insn(1, 0, 8, 7, 7)
 698#define OP_TLBI_VMALLE1OSNXS		sys_insn(1, 0, 9, 1, 0)
 699#define OP_TLBI_VAE1OSNXS		sys_insn(1, 0, 9, 1, 1)
 700#define OP_TLBI_ASIDE1OSNXS		sys_insn(1, 0, 9, 1, 2)
 701#define OP_TLBI_VAAE1OSNXS		sys_insn(1, 0, 9, 1, 3)
 702#define OP_TLBI_VALE1OSNXS		sys_insn(1, 0, 9, 1, 5)
 703#define OP_TLBI_VAALE1OSNXS		sys_insn(1, 0, 9, 1, 7)
 704#define OP_TLBI_RVAE1ISNXS		sys_insn(1, 0, 9, 2, 1)
 705#define OP_TLBI_RVAAE1ISNXS		sys_insn(1, 0, 9, 2, 3)
 706#define OP_TLBI_RVALE1ISNXS		sys_insn(1, 0, 9, 2, 5)
 707#define OP_TLBI_RVAALE1ISNXS		sys_insn(1, 0, 9, 2, 7)
 708#define OP_TLBI_VMALLE1ISNXS		sys_insn(1, 0, 9, 3, 0)
 709#define OP_TLBI_VAE1ISNXS		sys_insn(1, 0, 9, 3, 1)
 710#define OP_TLBI_ASIDE1ISNXS		sys_insn(1, 0, 9, 3, 2)
 711#define OP_TLBI_VAAE1ISNXS		sys_insn(1, 0, 9, 3, 3)
 712#define OP_TLBI_VALE1ISNXS		sys_insn(1, 0, 9, 3, 5)
 713#define OP_TLBI_VAALE1ISNXS		sys_insn(1, 0, 9, 3, 7)
 714#define OP_TLBI_RVAE1OSNXS		sys_insn(1, 0, 9, 5, 1)
 715#define OP_TLBI_RVAAE1OSNXS		sys_insn(1, 0, 9, 5, 3)
 716#define OP_TLBI_RVALE1OSNXS		sys_insn(1, 0, 9, 5, 5)
 717#define OP_TLBI_RVAALE1OSNXS		sys_insn(1, 0, 9, 5, 7)
 718#define OP_TLBI_RVAE1NXS		sys_insn(1, 0, 9, 6, 1)
 719#define OP_TLBI_RVAAE1NXS		sys_insn(1, 0, 9, 6, 3)
 720#define OP_TLBI_RVALE1NXS		sys_insn(1, 0, 9, 6, 5)
 721#define OP_TLBI_RVAALE1NXS		sys_insn(1, 0, 9, 6, 7)
 722#define OP_TLBI_VMALLE1NXS		sys_insn(1, 0, 9, 7, 0)
 723#define OP_TLBI_VAE1NXS			sys_insn(1, 0, 9, 7, 1)
 724#define OP_TLBI_ASIDE1NXS		sys_insn(1, 0, 9, 7, 2)
 725#define OP_TLBI_VAAE1NXS		sys_insn(1, 0, 9, 7, 3)
 726#define OP_TLBI_VALE1NXS		sys_insn(1, 0, 9, 7, 5)
 727#define OP_TLBI_VAALE1NXS		sys_insn(1, 0, 9, 7, 7)
 728#define OP_TLBI_IPAS2E1IS		sys_insn(1, 4, 8, 0, 1)
 729#define OP_TLBI_RIPAS2E1IS		sys_insn(1, 4, 8, 0, 2)
 730#define OP_TLBI_IPAS2LE1IS		sys_insn(1, 4, 8, 0, 5)
 731#define OP_TLBI_RIPAS2LE1IS		sys_insn(1, 4, 8, 0, 6)
 732#define OP_TLBI_ALLE2OS			sys_insn(1, 4, 8, 1, 0)
 733#define OP_TLBI_VAE2OS			sys_insn(1, 4, 8, 1, 1)
 734#define OP_TLBI_ALLE1OS			sys_insn(1, 4, 8, 1, 4)
 735#define OP_TLBI_VALE2OS			sys_insn(1, 4, 8, 1, 5)
 736#define OP_TLBI_VMALLS12E1OS		sys_insn(1, 4, 8, 1, 6)
 737#define OP_TLBI_RVAE2IS			sys_insn(1, 4, 8, 2, 1)
 738#define OP_TLBI_RVALE2IS		sys_insn(1, 4, 8, 2, 5)
 739#define OP_TLBI_ALLE2IS			sys_insn(1, 4, 8, 3, 0)
 740#define OP_TLBI_VAE2IS			sys_insn(1, 4, 8, 3, 1)
 741#define OP_TLBI_ALLE1IS			sys_insn(1, 4, 8, 3, 4)
 742#define OP_TLBI_VALE2IS			sys_insn(1, 4, 8, 3, 5)
 743#define OP_TLBI_VMALLS12E1IS		sys_insn(1, 4, 8, 3, 6)
 744#define OP_TLBI_IPAS2E1OS		sys_insn(1, 4, 8, 4, 0)
 745#define OP_TLBI_IPAS2E1			sys_insn(1, 4, 8, 4, 1)
 746#define OP_TLBI_RIPAS2E1		sys_insn(1, 4, 8, 4, 2)
 747#define OP_TLBI_RIPAS2E1OS		sys_insn(1, 4, 8, 4, 3)
 748#define OP_TLBI_IPAS2LE1OS		sys_insn(1, 4, 8, 4, 4)
 749#define OP_TLBI_IPAS2LE1		sys_insn(1, 4, 8, 4, 5)
 750#define OP_TLBI_RIPAS2LE1		sys_insn(1, 4, 8, 4, 6)
 751#define OP_TLBI_RIPAS2LE1OS		sys_insn(1, 4, 8, 4, 7)
 752#define OP_TLBI_RVAE2OS			sys_insn(1, 4, 8, 5, 1)
 753#define OP_TLBI_RVALE2OS		sys_insn(1, 4, 8, 5, 5)
 754#define OP_TLBI_RVAE2			sys_insn(1, 4, 8, 6, 1)
 755#define OP_TLBI_RVALE2			sys_insn(1, 4, 8, 6, 5)
 756#define OP_TLBI_ALLE2			sys_insn(1, 4, 8, 7, 0)
 757#define OP_TLBI_VAE2			sys_insn(1, 4, 8, 7, 1)
 758#define OP_TLBI_ALLE1			sys_insn(1, 4, 8, 7, 4)
 759#define OP_TLBI_VALE2			sys_insn(1, 4, 8, 7, 5)
 760#define OP_TLBI_VMALLS12E1		sys_insn(1, 4, 8, 7, 6)
 761#define OP_TLBI_IPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 1)
 762#define OP_TLBI_RIPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 2)
 763#define OP_TLBI_IPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 5)
 764#define OP_TLBI_RIPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 6)
 765#define OP_TLBI_ALLE2OSNXS		sys_insn(1, 4, 9, 1, 0)
 766#define OP_TLBI_VAE2OSNXS		sys_insn(1, 4, 9, 1, 1)
 767#define OP_TLBI_ALLE1OSNXS		sys_insn(1, 4, 9, 1, 4)
 768#define OP_TLBI_VALE2OSNXS		sys_insn(1, 4, 9, 1, 5)
 769#define OP_TLBI_VMALLS12E1OSNXS		sys_insn(1, 4, 9, 1, 6)
 770#define OP_TLBI_RVAE2ISNXS		sys_insn(1, 4, 9, 2, 1)
 771#define OP_TLBI_RVALE2ISNXS		sys_insn(1, 4, 9, 2, 5)
 772#define OP_TLBI_ALLE2ISNXS		sys_insn(1, 4, 9, 3, 0)
 773#define OP_TLBI_VAE2ISNXS		sys_insn(1, 4, 9, 3, 1)
 774#define OP_TLBI_ALLE1ISNXS		sys_insn(1, 4, 9, 3, 4)
 775#define OP_TLBI_VALE2ISNXS		sys_insn(1, 4, 9, 3, 5)
 776#define OP_TLBI_VMALLS12E1ISNXS		sys_insn(1, 4, 9, 3, 6)
 777#define OP_TLBI_IPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 0)
 778#define OP_TLBI_IPAS2E1NXS		sys_insn(1, 4, 9, 4, 1)
 779#define OP_TLBI_RIPAS2E1NXS		sys_insn(1, 4, 9, 4, 2)
 780#define OP_TLBI_RIPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 3)
 781#define OP_TLBI_IPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 4)
 782#define OP_TLBI_IPAS2LE1NXS		sys_insn(1, 4, 9, 4, 5)
 783#define OP_TLBI_RIPAS2LE1NXS		sys_insn(1, 4, 9, 4, 6)
 784#define OP_TLBI_RIPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 7)
 785#define OP_TLBI_RVAE2OSNXS		sys_insn(1, 4, 9, 5, 1)
 786#define OP_TLBI_RVALE2OSNXS		sys_insn(1, 4, 9, 5, 5)
 787#define OP_TLBI_RVAE2NXS		sys_insn(1, 4, 9, 6, 1)
 788#define OP_TLBI_RVALE2NXS		sys_insn(1, 4, 9, 6, 5)
 789#define OP_TLBI_ALLE2NXS		sys_insn(1, 4, 9, 7, 0)
 790#define OP_TLBI_VAE2NXS			sys_insn(1, 4, 9, 7, 1)
 791#define OP_TLBI_ALLE1NXS		sys_insn(1, 4, 9, 7, 4)
 792#define OP_TLBI_VALE2NXS		sys_insn(1, 4, 9, 7, 5)
 793#define OP_TLBI_VMALLS12E1NXS		sys_insn(1, 4, 9, 7, 6)
 794
 795/* Misc instructions */
 796#define OP_GCSPUSHX			sys_insn(1, 0, 7, 7, 4)
 797#define OP_GCSPOPCX			sys_insn(1, 0, 7, 7, 5)
 798#define OP_GCSPOPX			sys_insn(1, 0, 7, 7, 6)
 799#define OP_GCSPUSHM			sys_insn(1, 3, 7, 7, 0)
 800
 801#define OP_BRB_IALL			sys_insn(1, 1, 7, 2, 4)
 802#define OP_BRB_INJ			sys_insn(1, 1, 7, 2, 5)
 803#define OP_CFP_RCTX			sys_insn(1, 3, 7, 3, 4)
 804#define OP_DVP_RCTX			sys_insn(1, 3, 7, 3, 5)
 805#define OP_COSP_RCTX			sys_insn(1, 3, 7, 3, 6)
 806#define OP_CPP_RCTX			sys_insn(1, 3, 7, 3, 7)
 807
 808/*
 809 * BRBE Instructions
 810 */
 811#define BRB_IALL_INSN	__emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
 812#define BRB_INJ_INSN	__emit_inst(0xd5000000 | OP_BRB_INJ  | (0x1f))
 813
 814/* Common SCTLR_ELx flags. */
 815#define SCTLR_ELx_ENTP2	(BIT(60))
 816#define SCTLR_ELx_DSSBS	(BIT(44))
 817#define SCTLR_ELx_ATA	(BIT(43))
 818
 819#define SCTLR_ELx_EE_SHIFT	25
 820#define SCTLR_ELx_ENIA_SHIFT	31
 821
 822#define SCTLR_ELx_ITFSB	 (BIT(37))
 823#define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
 824#define SCTLR_ELx_ENIB	 (BIT(30))
 825#define SCTLR_ELx_LSMAOE (BIT(29))
 826#define SCTLR_ELx_nTLSMD (BIT(28))
 827#define SCTLR_ELx_ENDA	 (BIT(27))
 828#define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
 829#define SCTLR_ELx_EIS	 (BIT(22))
 830#define SCTLR_ELx_IESB	 (BIT(21))
 831#define SCTLR_ELx_TSCXT	 (BIT(20))
 832#define SCTLR_ELx_WXN	 (BIT(19))
 833#define SCTLR_ELx_ENDB	 (BIT(13))
 834#define SCTLR_ELx_I	 (BIT(12))
 835#define SCTLR_ELx_EOS	 (BIT(11))
 836#define SCTLR_ELx_SA	 (BIT(3))
 837#define SCTLR_ELx_C	 (BIT(2))
 838#define SCTLR_ELx_A	 (BIT(1))
 839#define SCTLR_ELx_M	 (BIT(0))
 840
 841/* SCTLR_EL2 specific flags. */
 842#define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
 843			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
 844			 (BIT(29)))
 845
 846#define SCTLR_EL2_BT	(BIT(36))
 847#ifdef CONFIG_CPU_BIG_ENDIAN
 848#define ENDIAN_SET_EL2		SCTLR_ELx_EE
 849#else
 850#define ENDIAN_SET_EL2		0
 851#endif
 852
 853#define INIT_SCTLR_EL2_MMU_ON						\
 854	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
 855	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
 856	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
 857
 858#define INIT_SCTLR_EL2_MMU_OFF \
 859	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
 860
 861/* SCTLR_EL1 specific flags. */
 862#ifdef CONFIG_CPU_BIG_ENDIAN
 863#define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
 864#else
 865#define ENDIAN_SET_EL1		0
 866#endif
 867
 868#define INIT_SCTLR_EL1_MMU_OFF \
 869	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
 870	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
 871
 872#define INIT_SCTLR_EL1_MMU_ON \
 873	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
 874	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
 875	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
 876	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
 877	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
 878	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
 879	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
 880
 881/* MAIR_ELx memory attributes (used by Linux) */
 882#define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
 883#define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
 884#define MAIR_ATTR_NORMAL_NC		UL(0x44)
 885#define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
 886#define MAIR_ATTR_NORMAL		UL(0xff)
 887#define MAIR_ATTR_MASK			UL(0xff)
 888
 889/* Position the attr at the correct index */
 890#define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
 891
 892/* id_aa64mmfr0 */
 893#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
 894#define ID_AA64MMFR0_EL1_TGRAN4_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
 895#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
 896#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
 897#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
 898#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
 899#define ID_AA64MMFR0_EL1_TGRAN16_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
 900#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
 901
 902#define ARM64_MIN_PARANGE_BITS		32
 903
 904#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
 905#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
 906#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
 907#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2		0x3
 908#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
 909
 910#ifdef CONFIG_ARM64_PA_BITS_52
 911#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
 912#else
 913#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
 914#endif
 915
 916#if defined(CONFIG_ARM64_4K_PAGES)
 917#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
 918#define ID_AA64MMFR0_EL1_TGRAN_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
 919#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
 920#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
 921#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
 922#elif defined(CONFIG_ARM64_16K_PAGES)
 923#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
 924#define ID_AA64MMFR0_EL1_TGRAN_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
 925#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
 926#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
 927#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
 928#elif defined(CONFIG_ARM64_64K_PAGES)
 929#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
 930#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
 931#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
 932#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
 933#endif
 934
 935#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
 936#define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
 937
 938#define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
 939#define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
 940
 941#define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
 942#define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
 943
 944/* GCR_EL1 Definitions */
 945#define SYS_GCR_EL1_RRND	(BIT(16))
 946#define SYS_GCR_EL1_EXCL_MASK	0xffffUL
 947
 948#ifdef CONFIG_KASAN_HW_TAGS
 949/*
 950 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
 951 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
 952 */
 953#define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
 954#define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
 955#define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
 956#define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
 957#else
 958#define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
 959#endif
 960
 961#define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
 962
 963/* RGSR_EL1 Definitions */
 964#define SYS_RGSR_EL1_TAG_MASK	0xfUL
 965#define SYS_RGSR_EL1_SEED_SHIFT	8
 966#define SYS_RGSR_EL1_SEED_MASK	0xffffUL
 967
 968/* TFSR{,E0}_EL1 bit definitions */
 969#define SYS_TFSR_EL1_TF0_SHIFT	0
 970#define SYS_TFSR_EL1_TF1_SHIFT	1
 971#define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
 972#define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
 973
 974/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
 975#define SYS_MPIDR_SAFE_VAL	(BIT(31))
 976
 977/* GIC Hypervisor interface registers */
 978/* ICH_LR*_EL2 bit definitions */
 979#define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
 980
 981#define ICH_LR_EOI		(1ULL << 41)
 982#define ICH_LR_GROUP		(1ULL << 60)
 983#define ICH_LR_HW		(1ULL << 61)
 984#define ICH_LR_STATE		(3ULL << 62)
 985#define ICH_LR_PENDING_BIT	(1ULL << 62)
 986#define ICH_LR_ACTIVE_BIT	(1ULL << 63)
 987#define ICH_LR_PHYS_ID_SHIFT	32
 988#define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
 989#define ICH_LR_PRIORITY_SHIFT	48
 990#define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
 991
 992/* ICH_VMCR_EL2 bit definitions */
 993#define ICH_VMCR_ACK_CTL_SHIFT	2
 994#define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
 995#define ICH_VMCR_FIQ_EN_SHIFT	3
 996#define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
 997#define ICH_VMCR_CBPR_SHIFT	4
 998#define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
 999#define ICH_VMCR_EOIM_SHIFT	9
1000#define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
1001#define ICH_VMCR_BPR1_SHIFT	18
1002#define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
1003#define ICH_VMCR_BPR0_SHIFT	21
1004#define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
1005#define ICH_VMCR_PMR_SHIFT	24
1006#define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
1007#define ICH_VMCR_ENG0_SHIFT	0
1008#define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
1009#define ICH_VMCR_ENG1_SHIFT	1
1010#define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
1011
1012/*
1013 * Permission Indirection Extension (PIE) permission encodings.
1014 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
1015 */
1016#define PIE_NONE_O	UL(0x0)
1017#define PIE_R_O		UL(0x1)
1018#define PIE_X_O		UL(0x2)
1019#define PIE_RX_O	UL(0x3)
1020#define PIE_RW_O	UL(0x5)
1021#define PIE_RWnX_O	UL(0x6)
1022#define PIE_RWX_O	UL(0x7)
1023#define PIE_R		UL(0x8)
1024#define PIE_GCS		UL(0x9)
1025#define PIE_RX		UL(0xa)
1026#define PIE_RW		UL(0xc)
1027#define PIE_RWX		UL(0xe)
1028#define PIE_MASK	UL(0xf)
1029
1030#define PIRx_ELx_BITS_PER_IDX		4
1031#define PIRx_ELx_PERM_SHIFT(idx)	((idx) * PIRx_ELx_BITS_PER_IDX)
1032#define PIRx_ELx_PERM_PREP(idx, perm)	(((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx))
1033
1034/*
1035 * Permission Overlay Extension (POE) permission encodings.
1036 */
1037#define POE_NONE	UL(0x0)
1038#define POE_R		UL(0x1)
1039#define POE_X		UL(0x2)
1040#define POE_RX		UL(0x3)
1041#define POE_W		UL(0x4)
1042#define POE_RW		UL(0x5)
1043#define POE_WX		UL(0x6)
1044#define POE_RWX		UL(0x7)
1045#define POE_MASK	UL(0xf)
1046
1047#define POR_ELx_BITS_PER_IDX		4
1048#define POR_ELx_PERM_SHIFT(idx)		((idx) * POR_ELx_BITS_PER_IDX)
1049#define POR_ELx_PERM_GET(idx, reg)	(((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK)
1050#define POR_ELx_PERM_PREP(idx, perm)	(((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))
1051
1052/*
1053 * Definitions for Guarded Control Stack
1054 */
1055
1056#define GCS_CAP_ADDR_MASK		GENMASK(63, 12)
1057#define GCS_CAP_ADDR_SHIFT		12
1058#define GCS_CAP_ADDR_WIDTH		52
1059#define GCS_CAP_ADDR(x)			FIELD_GET(GCS_CAP_ADDR_MASK, x)
1060
1061#define GCS_CAP_TOKEN_MASK		GENMASK(11, 0)
1062#define GCS_CAP_TOKEN_SHIFT		0
1063#define GCS_CAP_TOKEN_WIDTH		12
1064#define GCS_CAP_TOKEN(x)		FIELD_GET(GCS_CAP_TOKEN_MASK, x)
1065
1066#define GCS_CAP_VALID_TOKEN		0x1
1067#define GCS_CAP_IN_PROGRESS_TOKEN	0x5
1068
1069#define GCS_CAP(x)	((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
1070					       GCS_CAP_VALID_TOKEN)
1071/*
1072 * Definitions for GICv5 instructions
1073 */
1074#define GICV5_OP_GIC_CDAFF		sys_insn(1, 0, 12, 1, 3)
1075#define GICV5_OP_GIC_CDDI		sys_insn(1, 0, 12, 2, 0)
1076#define GICV5_OP_GIC_CDDIS		sys_insn(1, 0, 12, 1, 0)
1077#define GICV5_OP_GIC_CDHM		sys_insn(1, 0, 12, 2, 1)
1078#define GICV5_OP_GIC_CDEN		sys_insn(1, 0, 12, 1, 1)
1079#define GICV5_OP_GIC_CDEOI		sys_insn(1, 0, 12, 1, 7)
1080#define GICV5_OP_GIC_CDPEND		sys_insn(1, 0, 12, 1, 4)
1081#define GICV5_OP_GIC_CDPRI		sys_insn(1, 0, 12, 1, 2)
1082#define GICV5_OP_GIC_CDRCFG		sys_insn(1, 0, 12, 1, 5)
1083#define GICV5_OP_GICR_CDIA		sys_insn(1, 0, 12, 3, 0)
1084
1085/* Definitions for GIC CDAFF */
1086#define GICV5_GIC_CDAFF_IAFFID_MASK	GENMASK_ULL(47, 32)
1087#define GICV5_GIC_CDAFF_TYPE_MASK	GENMASK_ULL(31, 29)
1088#define GICV5_GIC_CDAFF_IRM_MASK	BIT_ULL(28)
1089#define GICV5_GIC_CDAFF_ID_MASK		GENMASK_ULL(23, 0)
1090
1091/* Definitions for GIC CDDI */
1092#define GICV5_GIC_CDDI_TYPE_MASK	GENMASK_ULL(31, 29)
1093#define GICV5_GIC_CDDI_ID_MASK		GENMASK_ULL(23, 0)
1094
1095/* Definitions for GIC CDDIS */
1096#define GICV5_GIC_CDDIS_TYPE_MASK	GENMASK_ULL(31, 29)
1097#define GICV5_GIC_CDDIS_TYPE(r)		FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r)
1098#define GICV5_GIC_CDDIS_ID_MASK		GENMASK_ULL(23, 0)
1099#define GICV5_GIC_CDDIS_ID(r)		FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r)
1100
1101/* Definitions for GIC CDEN */
1102#define GICV5_GIC_CDEN_TYPE_MASK	GENMASK_ULL(31, 29)
1103#define GICV5_GIC_CDEN_ID_MASK		GENMASK_ULL(23, 0)
1104
1105/* Definitions for GIC CDHM */
1106#define GICV5_GIC_CDHM_HM_MASK		BIT_ULL(32)
1107#define GICV5_GIC_CDHM_TYPE_MASK	GENMASK_ULL(31, 29)
1108#define GICV5_GIC_CDHM_ID_MASK		GENMASK_ULL(23, 0)
1109
1110/* Definitions for GIC CDPEND */
1111#define GICV5_GIC_CDPEND_PENDING_MASK	BIT_ULL(32)
1112#define GICV5_GIC_CDPEND_TYPE_MASK	GENMASK_ULL(31, 29)
1113#define GICV5_GIC_CDPEND_ID_MASK	GENMASK_ULL(23, 0)
1114
1115/* Definitions for GIC CDPRI */
1116#define GICV5_GIC_CDPRI_PRIORITY_MASK	GENMASK_ULL(39, 35)
1117#define GICV5_GIC_CDPRI_TYPE_MASK	GENMASK_ULL(31, 29)
1118#define GICV5_GIC_CDPRI_ID_MASK		GENMASK_ULL(23, 0)
1119
1120/* Definitions for GIC CDRCFG */
1121#define GICV5_GIC_CDRCFG_TYPE_MASK	GENMASK_ULL(31, 29)
1122#define GICV5_GIC_CDRCFG_ID_MASK	GENMASK_ULL(23, 0)
1123
1124/* Definitions for GICR CDIA */
1125#define GICV5_GIC_CDIA_VALID_MASK	BIT_ULL(32)
1126#define GICV5_GICR_CDIA_VALID(r)	FIELD_GET(GICV5_GIC_CDIA_VALID_MASK, r)
1127#define GICV5_GIC_CDIA_TYPE_MASK	GENMASK_ULL(31, 29)
1128#define GICV5_GIC_CDIA_ID_MASK		GENMASK_ULL(23, 0)
1129
1130#define gicr_insn(insn)			read_sysreg_s(GICV5_OP_GICR_##insn)
1131#define gic_insn(v, insn)		write_sysreg_s(v, GICV5_OP_GIC_##insn)
1132
1133#ifdef __ASSEMBLER__
1134
1135	.macro	mrs_s, rt, sreg
1136	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1137	.endm
1138
1139	.macro	msr_s, sreg, rt
1140	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1141	.endm
1142
1143	.macro	msr_hcr_el2, reg
1144#if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23)
1145	dsb	nsh
1146	msr	hcr_el2, \reg
1147	isb
1148#else
1149	msr	hcr_el2, \reg
1150#endif
1151	.endm
1152#else
1153
1154#include <linux/bitfield.h>
1155#include <linux/build_bug.h>
1156#include <linux/types.h>
1157#include <asm/alternative.h>
1158
1159#define DEFINE_MRS_S						\
1160	__DEFINE_ASM_GPR_NUMS					\
1161"	.macro	mrs_s, rt, sreg\n"				\
1162	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
1163"	.endm\n"
1164
1165#define DEFINE_MSR_S						\
1166	__DEFINE_ASM_GPR_NUMS					\
1167"	.macro	msr_s, sreg, rt\n"				\
1168	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
1169"	.endm\n"
1170
1171#define UNDEFINE_MRS_S						\
1172"	.purgem	mrs_s\n"
1173
1174#define UNDEFINE_MSR_S						\
1175"	.purgem	msr_s\n"
1176
1177#define __mrs_s(v, r)						\
1178	DEFINE_MRS_S						\
1179"	mrs_s " v ", " __stringify(r) "\n"			\
1180	UNDEFINE_MRS_S
1181
1182#define __msr_s(r, v)						\
1183	DEFINE_MSR_S						\
1184"	msr_s " __stringify(r) ", " v "\n"			\
1185	UNDEFINE_MSR_S
1186
1187/*
1188 * Unlike read_cpuid, calls to read_sysreg are never expected to be
1189 * optimized away or replaced with synthetic values.
1190 */
1191#define read_sysreg(r) ({					\
1192	u64 __val;						\
1193	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
1194	__val;							\
1195})
1196
1197/*
1198 * The "Z" constraint normally means a zero immediate, but when combined with
1199 * the "%x0" template means XZR.
1200 */
1201#define write_sysreg(v, r) do {					\
1202	u64 __val = (u64)(v);					\
1203	asm volatile("msr " __stringify(r) ", %x0"		\
1204		     : : "rZ" (__val));				\
1205} while (0)
1206
1207/*
1208 * For registers without architectural names, or simply unsupported by
1209 * GAS.
1210 *
1211 * __check_r forces warnings to be generated by the compiler when
1212 * evaluating r which wouldn't normally happen due to being passed to
1213 * the assembler via __stringify(r).
1214 */
1215#define read_sysreg_s(r) ({						\
1216	u64 __val;							\
1217	u32 __maybe_unused __check_r = (u32)(r);			\
1218	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
1219	__val;								\
1220})
1221
1222/*
1223 * The "Z" constraint combined with the "%x0" template should be enough
1224 * to force XZR generation if (v) is a constant 0 value but LLVM does not
1225 * yet understand that modifier/constraint combo so a conditional is required
1226 * to nudge the compiler into using XZR as a source for a 0 constant value.
1227 */
1228#define write_sysreg_s(v, r) do {					\
1229	u64 __val = (u64)(v);						\
1230	u32 __maybe_unused __check_r = (u32)(r);			\
1231	if (__builtin_constant_p(__val) && __val == 0)			\
1232		asm volatile(__msr_s(r, "xzr"));			\
1233	else								\
1234		asm volatile(__msr_s(r, "%x0") : : "r" (__val));	\
1235} while (0)
1236
1237/*
1238 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1239 * set mask are set. Other bits are left as-is.
1240 */
1241#define sysreg_clear_set(sysreg, clear, set) do {			\
1242	u64 __scs_val = read_sysreg(sysreg);				\
1243	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1244	if (__scs_new != __scs_val)					\
1245		write_sysreg(__scs_new, sysreg);			\
1246} while (0)
1247
1248#define sysreg_clear_set_hcr(clear, set) do {				\
1249	u64 __scs_val = read_sysreg(hcr_el2);				\
1250	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1251	if (__scs_new != __scs_val)					\
1252		write_sysreg_hcr(__scs_new);			\
1253} while (0)
1254
1255#define sysreg_clear_set_s(sysreg, clear, set) do {			\
1256	u64 __scs_val = read_sysreg_s(sysreg);				\
1257	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1258	if (__scs_new != __scs_val)					\
1259		write_sysreg_s(__scs_new, sysreg);			\
1260} while (0)
1261
1262#define write_sysreg_hcr(__val) do {					\
1263	if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) &&		\
1264	   (!system_capabilities_finalized() ||				\
1265	    alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23))) \
1266		asm volatile("dsb nsh; msr hcr_el2, %x0; isb"		\
1267			     : : "rZ" (__val));				\
1268	else								\
1269		asm volatile("msr hcr_el2, %x0"				\
1270			     : : "rZ" (__val));				\
1271} while (0)
1272
1273#define read_sysreg_par() ({						\
1274	u64 par;							\
1275	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1276	par = read_sysreg(par_el1);					\
1277	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1278	par;								\
1279})
1280
1281#define SYS_FIELD_VALUE(reg, field, val)	reg##_##field##_##val
1282
1283#define SYS_FIELD_GET(reg, field, val)		\
1284		 FIELD_GET(reg##_##field##_MASK, val)
1285
1286#define SYS_FIELD_PREP(reg, field, val)		\
1287		 FIELD_PREP(reg##_##field##_MASK, val)
1288
1289#define SYS_FIELD_PREP_ENUM(reg, field, val)		\
1290		 FIELD_PREP(reg##_##field##_MASK,	\
1291			    SYS_FIELD_VALUE(reg, field, val))
1292
1293#endif
1294
1295#endif	/* __ASM_SYSREG_H */
~/ Read-only file preview.