pgtable-prot.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2016 ARM Ltd.
  4 */
  5#ifndef __ASM_PGTABLE_PROT_H
  6#define __ASM_PGTABLE_PROT_H
  7
  8#include <asm/memory.h>
  9#include <asm/pgtable-hwdef.h>
 10
 11#include <linux/const.h>
 12
 13/*
 14 * Software defined PTE bits definition.
 15 */
 16#define PTE_WRITE		(PTE_DBM)		 /* same as DBM (51) */
 17#define PTE_SWP_EXCLUSIVE	(_AT(pteval_t, 1) << 2)	 /* only for swp ptes */
 18#define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
 19#define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
 20
 21/*
 22 * PTE_PRESENT_INVALID=1 & PTE_VALID=0 indicates that the pte's fields should be
 23 * interpreted according to the HW layout by SW but any attempted HW access to
 24 * the address will result in a fault. pte_present() returns true.
 25 */
 26#define PTE_PRESENT_INVALID	(PTE_NG)		 /* only when !PTE_VALID */
 27
 28#define PTE_PRESENT_VALID_KERNEL (PTE_VALID | PTE_MAYBE_NG)
 29
 30#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
 31#define PTE_UFFD_WP		(_AT(pteval_t, 1) << 58) /* uffd-wp tracking */
 32#define PTE_SWP_UFFD_WP		(_AT(pteval_t, 1) << 3)	 /* only for swp ptes */
 33#else
 34#define PTE_UFFD_WP		(_AT(pteval_t, 0))
 35#define PTE_SWP_UFFD_WP		(_AT(pteval_t, 0))
 36#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
 37
 38#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
 39
 40#define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_MAYBE_NG | PTE_MAYBE_SHARED | PTE_AF)
 41#define PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_MAYBE_NG | PMD_MAYBE_SHARED | PMD_SECT_AF)
 42
 43#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
 44#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 45#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
 46#define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
 47#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
 48
 49#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
 50#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
 51#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
 52
 53#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
 54
 55#define _PAGE_KERNEL		(PROT_NORMAL | PTE_DIRTY)
 56#define _PAGE_KERNEL_RO		((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY | PTE_DIRTY)
 57#define _PAGE_KERNEL_ROX	((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY | PTE_DIRTY)
 58#define _PAGE_KERNEL_EXEC	((PROT_NORMAL & ~PTE_PXN) | PTE_DIRTY)
 59#define _PAGE_KERNEL_EXEC_CONT	((PROT_NORMAL & ~PTE_PXN) | PTE_CONT | PTE_DIRTY)
 60
 61#define _PAGE_SHARED		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
 62#define _PAGE_SHARED_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
 63#define _PAGE_READONLY		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
 64#define _PAGE_READONLY_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
 65#define _PAGE_EXECONLY		(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
 66
 67#ifndef __ASSEMBLER__
 68
 69#include <asm/cpufeature.h>
 70#include <asm/pgtable-types.h>
 71#include <asm/rsi.h>
 72
 73extern bool arm64_use_ng_mappings;
 74extern unsigned long prot_ns_shared;
 75
 76#define PROT_NS_SHARED		(is_realm_world() ? prot_ns_shared : 0)
 77
 78#define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)
 79#define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)
 80
 81#ifndef CONFIG_ARM64_LPA2
 82#define lpa2_is_enabled()	false
 83#define PTE_MAYBE_SHARED	PTE_SHARED
 84#define PMD_MAYBE_SHARED	PMD_SECT_S
 85#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
 86#else
 87static inline bool __pure lpa2_is_enabled(void)
 88{
 89	return read_tcr() & TCR_EL1_DS;
 90}
 91
 92#define PTE_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PTE_SHARED)
 93#define PMD_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PMD_SECT_S)
 94#define PHYS_MASK_SHIFT		(lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)
 95#endif
 96
 97/*
 98 * Highest possible physical address supported.
 99 */
100#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
101
102/*
103 * If we have userspace only BTI we don't want to mark kernel pages
104 * guarded even if the system does support BTI.
105 */
106#define PTE_MAYBE_GP		(system_supports_bti_kernel() ? PTE_GP : 0)
107
108#define PAGE_KERNEL		__pgprot(_PAGE_KERNEL)
109#define PAGE_KERNEL_RO		__pgprot(_PAGE_KERNEL_RO)
110#define PAGE_KERNEL_ROX		__pgprot(_PAGE_KERNEL_ROX)
111#define PAGE_KERNEL_EXEC	__pgprot(_PAGE_KERNEL_EXEC)
112#define PAGE_KERNEL_EXEC_CONT	__pgprot(_PAGE_KERNEL_EXEC_CONT)
113
114#define PAGE_S2_MEMATTR(attr, has_fwb)					\
115	({								\
116		u64 __val;						\
117		if (has_fwb)						\
118			__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr);	\
119		else							\
120			__val = PTE_S2_MEMATTR(MT_S2_ ## attr);		\
121		__val;							\
122	 })
123
124#define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PRESENT_INVALID | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
125/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
126#define PAGE_SHARED		__pgprot(_PAGE_SHARED)
127#define PAGE_SHARED_EXEC	__pgprot(_PAGE_SHARED_EXEC)
128#define PAGE_READONLY		__pgprot(_PAGE_READONLY)
129#define PAGE_READONLY_EXEC	__pgprot(_PAGE_READONLY_EXEC)
130#define PAGE_EXECONLY		__pgprot(_PAGE_EXECONLY)
131
132#endif /* __ASSEMBLER__ */
133
134#define pte_pi_index(pte) ( \
135	((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
136	((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
137	((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
138	((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
139
140/*
141 * Page types used via Permission Indirection Extension (PIE). PIE uses
142 * the USER, DBM, PXN and UXN bits to to generate an index which is used
143 * to look up the actual permission in PIR_ELx and PIRE0_EL1. We define
144 * combinations we use on non-PIE systems with the same encoding, for
145 * convenience these are listed here as comments as are the unallocated
146 * encodings.
147 */
148
149/* 0: PAGE_DEFAULT                                                  */
150/* 1:                                                      PTE_USER */
151/* 2:                                          PTE_WRITE            */
152/* 3:                                          PTE_WRITE | PTE_USER */
153/* 4: PAGE_EXECONLY                  PTE_PXN                        */
154/* 5: PAGE_READONLY_EXEC             PTE_PXN |             PTE_USER */
155/* 6:                                PTE_PXN | PTE_WRITE            */
156/* 7: PAGE_SHARED_EXEC               PTE_PXN | PTE_WRITE | PTE_USER */
157/* 8: PAGE_KERNEL_ROX      PTE_UXN                                  */
158/* 9: PAGE_GCS_RO          PTE_UXN |                       PTE_USER */
159/* a: PAGE_KERNEL_EXEC     PTE_UXN |           PTE_WRITE            */
160/* b: PAGE_GCS             PTE_UXN |           PTE_WRITE | PTE_USER */
161/* c: PAGE_KERNEL_RO       PTE_UXN | PTE_PXN                        */
162/* d: PAGE_READONLY        PTE_UXN | PTE_PXN |             PTE_USER */
163/* e: PAGE_KERNEL          PTE_UXN | PTE_PXN | PTE_WRITE            */
164/* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
165
166#define _PAGE_GCS	(_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_WRITE | PTE_USER)
167#define _PAGE_GCS_RO	(_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_USER)
168
169#define PIE_E0	( \
170	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS),           PIE_GCS)  | \
171	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO),        PIE_R)   | \
172	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
173	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O)  | \
174	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX_O) | \
175	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY),      PIE_R_O)   | \
176	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED),        PIE_RW_O))
177
178#define PIE_E1	( \
179	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS),           PIE_NONE_O) | \
180	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO),        PIE_NONE_O) | \
181	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
182	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
183	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
184	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
185	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
186	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
187	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
188	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
189	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL),        PIE_RW))
190
191#endif /* __ASM_PGTABLE_PROT_H */