mmu.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2012 ARM Ltd.
  4 */
  5#ifndef __ASM_MMU_H
  6#define __ASM_MMU_H
  7
  8#include <asm/cputype.h>
  9
 10#define MMCF_AARCH32	0x1	/* mm context flag for AArch32 executables */
 11#define USER_ASID_BIT	48
 12#define USER_ASID_FLAG	(UL(1) << USER_ASID_BIT)
 13#define TTBR_ASID_MASK	(UL(0xffff) << 48)
 14
 15#ifndef __ASSEMBLER__
 16
 17#include <linux/refcount.h>
 18#include <asm/cpufeature.h>
 19
 20enum pgtable_type {
 21	TABLE_PTE,
 22	TABLE_PMD,
 23	TABLE_PUD,
 24	TABLE_P4D,
 25};
 26
 27typedef struct {
 28	atomic64_t	id;
 29#ifdef CONFIG_COMPAT
 30	void		*sigpage;
 31#endif
 32	refcount_t	pinned;
 33	void		*vdso;
 34	unsigned long	flags;
 35	u8		pkey_allocation_map;
 36} mm_context_t;
 37
 38/*
 39 * We use atomic64_read() here because the ASID for an 'mm_struct' can
 40 * be reallocated when scheduling one of its threads following a
 41 * rollover event (see new_context() and flush_context()). In this case,
 42 * a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush())
 43 * may use a stale ASID. This is fine in principle as the new ASID is
 44 * guaranteed to be clean in the TLB, but the TLBI routines have to take
 45 * care to handle the following race:
 46 *
 47 *    CPU 0                    CPU 1                          CPU 2
 48 *
 49 *    // ptep_clear_flush(mm)
 50 *    xchg_relaxed(pte, 0)
 51 *    DSB ISHST
 52 *    old = ASID(mm)
 53 *         |                                                  <rollover>
 54 *         |                   new = new_context(mm)
 55 *         \-----------------> atomic_set(mm->context.id, new)
 56 *                             cpu_switch_mm(mm)
 57 *                             // Hardware walk of pte using new ASID
 58 *    TLBI(old)
 59 *
 60 * In this scenario, the barrier on CPU 0 and the dependency on CPU 1
 61 * ensure that the page-table walker on CPU 1 *must* see the invalid PTE
 62 * written by CPU 0.
 63 */
 64#define ASID(mm)	(atomic64_read(&(mm)->context.id) & 0xffff)
 65
 66static inline bool arm64_kernel_unmapped_at_el0(void)
 67{
 68	return alternative_has_cap_unlikely(ARM64_UNMAP_KERNEL_AT_EL0);
 69}
 70
 71extern void arm64_memblock_init(void);
 72extern void paging_init(void);
 73extern void bootmem_init(void);
 74extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt,
 75				   phys_addr_t size, pgprot_t prot);
 76extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
 77			       unsigned long virt, phys_addr_t size,
 78			       pgprot_t prot, bool page_mappings_only);
 79extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot);
 80extern void mark_linear_text_alias_ro(void);
 81extern int split_kernel_leaf_mapping(unsigned long start, unsigned long end);
 82extern void linear_map_maybe_split_to_ptes(void);
 83
 84/*
 85 * This check is triggered during the early boot before the cpufeature
 86 * is initialised. Checking the status on the local CPU allows the boot
 87 * CPU to detect the need for non-global mappings and thus avoiding a
 88 * pagetable re-write after all the CPUs are booted. This check will be
 89 * anyway run on individual CPUs, allowing us to get the consistent
 90 * state once the SMP CPUs are up and thus make the switch to non-global
 91 * mappings if required.
 92 */
 93static inline bool kaslr_requires_kpti(void)
 94{
 95	/*
 96	 * E0PD does a similar job to KPTI so can be used instead
 97	 * where available.
 98	 */
 99	if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
100		u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
101		if (cpuid_feature_extract_unsigned_field(mmfr2,
102						ID_AA64MMFR2_EL1_E0PD_SHIFT))
103			return false;
104	}
105
106	return true;
107}
108
109#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
110void kpti_install_ng_mappings(void);
111#else
112static inline void kpti_install_ng_mappings(void) {}
113#endif
114
115#endif	/* !__ASSEMBLER__ */
116#endif