FILE
esr.h

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linux-6.19.14/arch/arm64/include/asm/esr.h C
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2013 - ARM Ltd
  4 * Author: Marc Zyngier <marc.zyngier@arm.com>
  5 */
  6
  7#ifndef __ASM_ESR_H
  8#define __ASM_ESR_H
  9
 10#include <asm/memory.h>
 11#include <asm/sysreg.h>
 12
 13#define ESR_ELx_EC_UNKNOWN	UL(0x00)
 14#define ESR_ELx_EC_WFx		UL(0x01)
 15/* Unallocated EC: 0x02 */
 16#define ESR_ELx_EC_CP15_32	UL(0x03)
 17#define ESR_ELx_EC_CP15_64	UL(0x04)
 18#define ESR_ELx_EC_CP14_MR	UL(0x05)
 19#define ESR_ELx_EC_CP14_LS	UL(0x06)
 20#define ESR_ELx_EC_FP_ASIMD	UL(0x07)
 21#define ESR_ELx_EC_CP10_ID	UL(0x08)	/* EL2 only */
 22#define ESR_ELx_EC_PAC		UL(0x09)	/* EL2 and above */
 23#define ESR_ELx_EC_OTHER	UL(0x0A)
 24/* Unallocated EC: 0x0B */
 25#define ESR_ELx_EC_CP14_64	UL(0x0C)
 26#define ESR_ELx_EC_BTI		UL(0x0D)
 27#define ESR_ELx_EC_ILL		UL(0x0E)
 28/* Unallocated EC: 0x0F - 0x10 */
 29#define ESR_ELx_EC_SVC32	UL(0x11)
 30#define ESR_ELx_EC_HVC32	UL(0x12)	/* EL2 only */
 31#define ESR_ELx_EC_SMC32	UL(0x13)	/* EL2 and above */
 32/* Unallocated EC: 0x14 */
 33#define ESR_ELx_EC_SVC64	UL(0x15)
 34#define ESR_ELx_EC_HVC64	UL(0x16)	/* EL2 and above */
 35#define ESR_ELx_EC_SMC64	UL(0x17)	/* EL2 and above */
 36#define ESR_ELx_EC_SYS64	UL(0x18)
 37#define ESR_ELx_EC_SVE		UL(0x19)
 38#define ESR_ELx_EC_ERET		UL(0x1a)	/* EL2 only */
 39/* Unallocated EC: 0x1B */
 40#define ESR_ELx_EC_FPAC		UL(0x1C)	/* EL1 and above */
 41#define ESR_ELx_EC_SME		UL(0x1D)
 42/* Unallocated EC: 0x1E */
 43#define ESR_ELx_EC_IMP_DEF	UL(0x1f)	/* EL3 only */
 44#define ESR_ELx_EC_IABT_LOW	UL(0x20)
 45#define ESR_ELx_EC_IABT_CUR	UL(0x21)
 46#define ESR_ELx_EC_PC_ALIGN	UL(0x22)
 47/* Unallocated EC: 0x23 */
 48#define ESR_ELx_EC_DABT_LOW	UL(0x24)
 49#define ESR_ELx_EC_DABT_CUR	UL(0x25)
 50#define ESR_ELx_EC_SP_ALIGN	UL(0x26)
 51#define ESR_ELx_EC_MOPS		UL(0x27)
 52#define ESR_ELx_EC_FP_EXC32	UL(0x28)
 53/* Unallocated EC: 0x29 - 0x2B */
 54#define ESR_ELx_EC_FP_EXC64	UL(0x2C)
 55#define ESR_ELx_EC_GCS		UL(0x2D)
 56/* Unallocated EC:  0x2E */
 57#define ESR_ELx_EC_SERROR	UL(0x2F)
 58#define ESR_ELx_EC_BREAKPT_LOW	UL(0x30)
 59#define ESR_ELx_EC_BREAKPT_CUR	UL(0x31)
 60#define ESR_ELx_EC_SOFTSTP_LOW	UL(0x32)
 61#define ESR_ELx_EC_SOFTSTP_CUR	UL(0x33)
 62#define ESR_ELx_EC_WATCHPT_LOW	UL(0x34)
 63#define ESR_ELx_EC_WATCHPT_CUR	UL(0x35)
 64/* Unallocated EC: 0x36 - 0x37 */
 65#define ESR_ELx_EC_BKPT32	UL(0x38)
 66/* Unallocated EC: 0x39 */
 67#define ESR_ELx_EC_VECTOR32	UL(0x3A)	/* EL2 only */
 68/* Unallocated EC: 0x3B */
 69#define ESR_ELx_EC_BRK64	UL(0x3C)
 70/* Unallocated EC: 0x3D - 0x3F */
 71#define ESR_ELx_EC_MAX		UL(0x3F)
 72
 73#define ESR_ELx_EC_SHIFT	(26)
 74#define ESR_ELx_EC_WIDTH	(6)
 75#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
 76#define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 77
 78#define ESR_ELx_IL_SHIFT	(25)
 79#define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
 80#define ESR_ELx_ISS_MASK	(GENMASK(24, 0))
 81#define ESR_ELx_ISS(esr)	((esr) & ESR_ELx_ISS_MASK)
 82#define ESR_ELx_ISS2_SHIFT	(32)
 83#define ESR_ELx_ISS2_MASK	(GENMASK_ULL(55, 32))
 84#define ESR_ELx_ISS2(esr)	(((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
 85
 86/* ISS field definitions shared by different classes */
 87#define ESR_ELx_WNR_SHIFT	(6)
 88#define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
 89
 90/* Asynchronous Error Type */
 91#define ESR_ELx_IDS_SHIFT	(24)
 92#define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
 93#define ESR_ELx_AET_SHIFT	(10)
 94#define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
 95
 96#define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
 97#define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
 98#define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
 99#define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
100#define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
101
102/* Shared ISS field definitions for Data/Instruction aborts */
103#define ESR_ELx_VNCR_SHIFT	(13)
104#define ESR_ELx_VNCR		(UL(1) << ESR_ELx_VNCR_SHIFT)
105#define ESR_ELx_SET_SHIFT	(11)
106#define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
107#define ESR_ELx_FnV_SHIFT	(10)
108#define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
109#define ESR_ELx_EA_SHIFT	(9)
110#define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
111#define ESR_ELx_S1PTW_SHIFT	(7)
112#define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
113
114/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
115#define ESR_ELx_FSC		(0x3F)
116#define ESR_ELx_FSC_TYPE	(0x3C)
117#define ESR_ELx_FSC_LEVEL	(0x03)
118#define ESR_ELx_FSC_EXTABT	(0x10)
119#define ESR_ELx_FSC_MTE		(0x11)
120#define ESR_ELx_FSC_SERROR	(0x11)
121#define ESR_ELx_FSC_ACCESS	(0x08)
122#define ESR_ELx_FSC_FAULT	(0x04)
123#define ESR_ELx_FSC_PERM	(0x0C)
124#define ESR_ELx_FSC_SEA_TTW(n)	(0x14 + (n))
125#define ESR_ELx_FSC_SECC	(0x18)
126#define ESR_ELx_FSC_SECC_TTW(n)	(0x1c + (n))
127#define ESR_ELx_FSC_ADDRSZ	(0x00)
128
129/*
130 * Annoyingly, the negative levels for Address size faults aren't laid out
131 * contiguously (or in the desired order)
132 */
133#define ESR_ELx_FSC_ADDRSZ_nL(n)	((n) == -1 ? 0x25 : 0x2C)
134#define ESR_ELx_FSC_ADDRSZ_L(n)		((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \
135						   (ESR_ELx_FSC_ADDRSZ + (n)))
136
137/* Status codes for individual page table levels */
138#define ESR_ELx_FSC_ACCESS_L(n)	(ESR_ELx_FSC_ACCESS + (n))
139#define ESR_ELx_FSC_PERM_L(n)	(ESR_ELx_FSC_PERM + (n))
140
141#define ESR_ELx_FSC_FAULT_nL	(0x2C)
142#define ESR_ELx_FSC_FAULT_L(n)	(((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
143					    ESR_ELx_FSC_FAULT) + (n))
144
145/* ISS field definitions for Data Aborts */
146#define ESR_ELx_ISV_SHIFT	(24)
147#define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
148#define ESR_ELx_SAS_SHIFT	(22)
149#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
150#define ESR_ELx_SSE_SHIFT	(21)
151#define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
152#define ESR_ELx_SRT_SHIFT	(16)
153#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
154#define ESR_ELx_SF_SHIFT	(15)
155#define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
156#define ESR_ELx_AR_SHIFT	(14)
157#define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
158#define ESR_ELx_CM_SHIFT	(8)
159#define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
160
161/* ISS2 field definitions for Data Aborts */
162#define ESR_ELx_TnD_SHIFT	(10)
163#define ESR_ELx_TnD 		(UL(1) << ESR_ELx_TnD_SHIFT)
164#define ESR_ELx_TagAccess_SHIFT	(9)
165#define ESR_ELx_TagAccess	(UL(1) << ESR_ELx_TagAccess_SHIFT)
166#define ESR_ELx_GCS_SHIFT	(8)
167#define ESR_ELx_GCS 		(UL(1) << ESR_ELx_GCS_SHIFT)
168#define ESR_ELx_Overlay_SHIFT	(6)
169#define ESR_ELx_Overlay		(UL(1) << ESR_ELx_Overlay_SHIFT)
170#define ESR_ELx_DirtyBit_SHIFT	(5)
171#define ESR_ELx_DirtyBit	(UL(1) << ESR_ELx_DirtyBit_SHIFT)
172#define ESR_ELx_Xs_SHIFT	(0)
173#define ESR_ELx_Xs_MASK		(GENMASK_ULL(4, 0))
174
175/* ISS field definitions for exceptions taken in to Hyp */
176#define ESR_ELx_CV		(UL(1) << 24)
177#define ESR_ELx_COND_SHIFT	(20)
178#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
179#define ESR_ELx_WFx_ISS_RN	(UL(0x1F) << 5)
180#define ESR_ELx_WFx_ISS_RV	(UL(1) << 2)
181#define ESR_ELx_WFx_ISS_TI	(UL(3) << 0)
182#define ESR_ELx_WFx_ISS_WFxT	(UL(2) << 0)
183#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
184#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
185#define ESR_ELx_xVC_IMM_MASK	((UL(1) << 16) - 1)
186
187/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */
188#define ESR_ELx_ISS_OTHER_ST64BV	(0)
189#define ESR_ELx_ISS_OTHER_ST64BV0	(1)
190#define ESR_ELx_ISS_OTHER_LDST64B	(2)
191#define ESR_ELx_ISS_OTHER_TSBCSYNC	(3)
192#define ESR_ELx_ISS_OTHER_PSBCSYNC	(4)
193
194#define DISR_EL1_IDS		(UL(1) << 24)
195/*
196 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
197 * different things in the future...
198 */
199#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
200
201/* ESR value templates for specific events */
202#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK |			\
203				 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
204#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
205				 ESR_ELx_WFx_ISS_WFI)
206
207/* BRK instruction trap from AArch64 state */
208#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
209
210/* ISS field definitions for System instruction traps */
211#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
212#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
213#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
214#define ESR_ELx_SYS64_ISS_DIR_READ	0x1
215#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
216
217#define ESR_ELx_SYS64_ISS_RT_SHIFT	5
218#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
219#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
220#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
221#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
222#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
223#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
224#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
225#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
226#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
227#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
228#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
229#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
230					 ESR_ELx_SYS64_ISS_OP1_MASK | \
231					 ESR_ELx_SYS64_ISS_OP2_MASK | \
232					 ESR_ELx_SYS64_ISS_CRN_MASK | \
233					 ESR_ELx_SYS64_ISS_CRM_MASK)
234#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
235					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
236					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
237					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
238					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
239					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
240
241#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
242					 ESR_ELx_SYS64_ISS_DIR_MASK)
243#define ESR_ELx_SYS64_ISS_RT(esr) \
244	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
245/*
246 * User space cache operations have the following sysreg encoding
247 * in System instructions.
248 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
249 */
250#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
251#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
252#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
253#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
254#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
255#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
256
257#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
258						 ESR_ELx_SYS64_ISS_OP1_MASK | \
259						 ESR_ELx_SYS64_ISS_OP2_MASK | \
260						 ESR_ELx_SYS64_ISS_CRN_MASK | \
261						 ESR_ELx_SYS64_ISS_DIR_MASK)
262#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
263				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
264				 ESR_ELx_SYS64_ISS_DIR_WRITE)
265/*
266 * User space MRS operations which are supported for emulation
267 * have the following sysreg encoding in System instructions.
268 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
269 */
270#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
271						 ESR_ELx_SYS64_ISS_OP1_MASK | \
272						 ESR_ELx_SYS64_ISS_CRN_MASK | \
273						 ESR_ELx_SYS64_ISS_DIR_MASK)
274#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
275				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
276				 ESR_ELx_SYS64_ISS_DIR_READ)
277
278#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
279#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
280					 ESR_ELx_SYS64_ISS_DIR_READ)
281
282#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
283					 ESR_ELx_SYS64_ISS_DIR_READ)
284
285#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
286					 ESR_ELx_SYS64_ISS_DIR_READ)
287
288#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
289					 ESR_ELx_SYS64_ISS_DIR_READ)
290
291#define esr_sys64_to_sysreg(e)					\
292	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
293		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
294		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
295		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
296		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
297		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
298		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
299		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
300		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
301		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
302
303#define esr_cp15_to_sysreg(e)					\
304	sys_reg(3,						\
305		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
306		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
307		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
308		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
309		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
310		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
311		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
312		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
313
314/* ISS field definitions for ERET/ERETAA/ERETAB trapping */
315#define ESR_ELx_ERET_ISS_ERET		0x2
316#define ESR_ELx_ERET_ISS_ERETA		0x1
317
318/*
319 * ISS field definitions for floating-point exception traps
320 * (FP_EXC_32/FP_EXC_64).
321 *
322 * (The FPEXC_* constants are used instead for common bits.)
323 */
324
325#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
326
327/*
328 * ISS field definitions for CP15 accesses
329 */
330#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
331#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
332#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
333
334#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
335#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
336#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
337#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
338#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
339#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
340#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
341#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
342#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
343#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
344
345#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
346					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
347					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
348					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
349					 ESR_ELx_CP15_32_ISS_DIR_MASK)
350#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
351					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
352					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
353					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
354					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
355
356#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
357#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
358#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
359
360#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
361#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
362
363#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
364#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
365
366#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
367#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
368#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
369#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
370
371#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
372					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
373					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
374
375#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
376					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
377					 ESR_ELx_CP15_64_ISS_DIR_MASK)
378
379#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
380					 ESR_ELx_CP15_64_ISS_DIR_READ)
381
382#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
383					 ESR_ELx_CP15_64_ISS_DIR_READ)
384
385#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
386					 ESR_ELx_CP15_32_ISS_DIR_READ)
387
388/*
389 * ISS values for SME traps
390 */
391#define ESR_ELx_SME_ISS_SMTC_MASK		GENMASK(2, 0)
392#define ESR_ELx_SME_ISS_SMTC(esr)		((esr) & ESR_ELx_SME_ISS_SMTC_MASK)
393
394#define ESR_ELx_SME_ISS_SMTC_SME_DISABLED	0
395#define ESR_ELx_SME_ISS_SMTC_ILL		1
396#define ESR_ELx_SME_ISS_SMTC_SM_DISABLED	2
397#define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED	3
398#define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED	4
399
400/* ISS field definitions for MOPS exceptions */
401#define ESR_ELx_MOPS_ISS_MEM_INST	(UL(1) << 24)
402#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE	(UL(1) << 18)
403#define ESR_ELx_MOPS_ISS_WRONG_OPTION	(UL(1) << 17)
404#define ESR_ELx_MOPS_ISS_OPTION_A	(UL(1) << 16)
405#define ESR_ELx_MOPS_ISS_DESTREG(esr)	(((esr) & (UL(0x1f) << 10)) >> 10)
406#define ESR_ELx_MOPS_ISS_SRCREG(esr)	(((esr) & (UL(0x1f) << 5)) >> 5)
407#define ESR_ELx_MOPS_ISS_SIZEREG(esr)	(((esr) & (UL(0x1f) << 0)) >> 0)
408
409/* ISS field definitions for GCS */
410#define ESR_ELx_ExType_SHIFT	(20)
411#define ESR_ELx_ExType_MASK		GENMASK(23, 20)
412#define ESR_ELx_Raddr_SHIFT		(10)
413#define ESR_ELx_Raddr_MASK		GENMASK(14, 10)
414#define ESR_ELx_Rn_SHIFT		(5)
415#define ESR_ELx_Rn_MASK			GENMASK(9, 5)
416#define ESR_ELx_Rvalue_SHIFT		5
417#define ESR_ELx_Rvalue_MASK		GENMASK(9, 5)
418#define ESR_ELx_IT_SHIFT		(0)
419#define ESR_ELx_IT_MASK			GENMASK(4, 0)
420
421#define ESR_ELx_ExType_DATA_CHECK	0
422#define ESR_ELx_ExType_EXLOCK		1
423#define ESR_ELx_ExType_STR		2
424
425#define ESR_ELx_IT_RET			0
426#define ESR_ELx_IT_GCSPOPM		1
427#define ESR_ELx_IT_RET_KEYA		2
428#define ESR_ELx_IT_RET_KEYB		3
429#define ESR_ELx_IT_GCSSS1		4
430#define ESR_ELx_IT_GCSSS2		5
431#define ESR_ELx_IT_GCSPOPCX		6
432#define ESR_ELx_IT_GCSPOPX		7
433
434#ifndef __ASSEMBLER__
435#include <asm/types.h>
436
437static inline unsigned long esr_brk_comment(unsigned long esr)
438{
439	return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
440}
441
442static inline bool esr_is_data_abort(unsigned long esr)
443{
444	const unsigned long ec = ESR_ELx_EC(esr);
445
446	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
447}
448
449static inline bool esr_is_cfi_brk(unsigned long esr)
450{
451	return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
452	       (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE;
453}
454
455static inline bool esr_is_ubsan_brk(unsigned long esr)
456{
457	return (esr_brk_comment(esr) & ~UBSAN_BRK_MASK) == UBSAN_BRK_IMM;
458}
459
460static inline bool esr_fsc_is_translation_fault(unsigned long esr)
461{
462	esr = esr & ESR_ELx_FSC;
463
464	return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
465	       (esr == ESR_ELx_FSC_FAULT_L(2)) ||
466	       (esr == ESR_ELx_FSC_FAULT_L(1)) ||
467	       (esr == ESR_ELx_FSC_FAULT_L(0)) ||
468	       (esr == ESR_ELx_FSC_FAULT_L(-1));
469}
470
471static inline bool esr_fsc_is_permission_fault(unsigned long esr)
472{
473	esr = esr & ESR_ELx_FSC;
474
475	return (esr == ESR_ELx_FSC_PERM_L(3)) ||
476	       (esr == ESR_ELx_FSC_PERM_L(2)) ||
477	       (esr == ESR_ELx_FSC_PERM_L(1)) ||
478	       (esr == ESR_ELx_FSC_PERM_L(0));
479}
480
481static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
482{
483	esr = esr & ESR_ELx_FSC;
484
485	return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
486	       (esr == ESR_ELx_FSC_ACCESS_L(2)) ||
487	       (esr == ESR_ELx_FSC_ACCESS_L(1)) ||
488	       (esr == ESR_ELx_FSC_ACCESS_L(0));
489}
490
491static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr)
492{
493	esr &= ESR_ELx_FSC;
494
495	return (esr == ESR_ELx_FSC_ADDRSZ_L(3))	||
496	       (esr == ESR_ELx_FSC_ADDRSZ_L(2))	||
497	       (esr == ESR_ELx_FSC_ADDRSZ_L(1)) ||
498	       (esr == ESR_ELx_FSC_ADDRSZ_L(0))	||
499	       (esr == ESR_ELx_FSC_ADDRSZ_L(-1));
500}
501
502static inline bool esr_fsc_is_sea_ttw(unsigned long esr)
503{
504	esr = esr & ESR_ELx_FSC;
505
506	return (esr == ESR_ELx_FSC_SEA_TTW(3)) ||
507	       (esr == ESR_ELx_FSC_SEA_TTW(2)) ||
508	       (esr == ESR_ELx_FSC_SEA_TTW(1)) ||
509	       (esr == ESR_ELx_FSC_SEA_TTW(0)) ||
510	       (esr == ESR_ELx_FSC_SEA_TTW(-1));
511}
512
513static inline bool esr_fsc_is_secc_ttw(unsigned long esr)
514{
515	esr = esr & ESR_ELx_FSC;
516
517	return (esr == ESR_ELx_FSC_SECC_TTW(3)) ||
518	       (esr == ESR_ELx_FSC_SECC_TTW(2)) ||
519	       (esr == ESR_ELx_FSC_SECC_TTW(1)) ||
520	       (esr == ESR_ELx_FSC_SECC_TTW(0)) ||
521	       (esr == ESR_ELx_FSC_SECC_TTW(-1));
522}
523
524/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */
525static inline bool esr_iss_is_eretax(unsigned long esr)
526{
527	return esr & ESR_ELx_ERET_ISS_ERET;
528}
529
530/* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */
531static inline bool esr_iss_is_eretab(unsigned long esr)
532{
533	return esr & ESR_ELx_ERET_ISS_ERETA;
534}
535
536const char *esr_get_class_string(unsigned long esr);
537#endif /* __ASSEMBLER__ */
538
539#endif /* __ASM_ESR_H */
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