arm_pmuv3.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2012 ARM Ltd.
  4 */
  5
  6#ifndef __ASM_PMUV3_H
  7#define __ASM_PMUV3_H
  8
  9#include <asm/kvm_host.h>
 10
 11#include <asm/cpufeature.h>
 12#include <asm/sysreg.h>
 13
 14#define RETURN_READ_PMEVCNTRN(n) \
 15	return read_sysreg(pmevcntr##n##_el0)
 16static inline unsigned long read_pmevcntrn(int n)
 17{
 18	PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
 19	return 0;
 20}
 21
 22#define WRITE_PMEVCNTRN(n) \
 23	write_sysreg(val, pmevcntr##n##_el0)
 24static inline void write_pmevcntrn(int n, unsigned long val)
 25{
 26	PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
 27}
 28
 29#define WRITE_PMEVTYPERN(n) \
 30	write_sysreg(val, pmevtyper##n##_el0)
 31static inline void write_pmevtypern(int n, unsigned long val)
 32{
 33	PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
 34}
 35
 36#define RETURN_READ_PMEVTYPERN(n) \
 37	return read_sysreg(pmevtyper##n##_el0)
 38static inline unsigned long read_pmevtypern(int n)
 39{
 40	PMEVN_SWITCH(n, RETURN_READ_PMEVTYPERN);
 41	return 0;
 42}
 43
 44static inline unsigned long read_pmmir(void)
 45{
 46	return read_cpuid(PMMIR_EL1);
 47}
 48
 49static inline u32 read_pmuver(void)
 50{
 51	u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
 52
 53	return cpuid_feature_extract_unsigned_field(dfr0,
 54			ID_AA64DFR0_EL1_PMUVer_SHIFT);
 55}
 56
 57static inline bool pmuv3_has_icntr(void)
 58{
 59	u64 dfr1 = read_sysreg(id_aa64dfr1_el1);
 60
 61	return !!cpuid_feature_extract_unsigned_field(dfr1,
 62			ID_AA64DFR1_EL1_PMICNTR_SHIFT);
 63}
 64
 65static inline void write_pmcr(u64 val)
 66{
 67	write_sysreg(val, pmcr_el0);
 68}
 69
 70static inline u64 read_pmcr(void)
 71{
 72	return read_sysreg(pmcr_el0);
 73}
 74
 75static inline void write_pmselr(u32 val)
 76{
 77	write_sysreg(val, pmselr_el0);
 78}
 79
 80static inline void write_pmccntr(u64 val)
 81{
 82	write_sysreg(val, pmccntr_el0);
 83}
 84
 85static inline u64 read_pmccntr(void)
 86{
 87	return read_sysreg(pmccntr_el0);
 88}
 89
 90static inline void write_pmicntr(u64 val)
 91{
 92	write_sysreg_s(val, SYS_PMICNTR_EL0);
 93}
 94
 95static inline u64 read_pmicntr(void)
 96{
 97	return read_sysreg_s(SYS_PMICNTR_EL0);
 98}
 99
100static inline void write_pmcntenset(u64 val)
101{
102	write_sysreg(val, pmcntenset_el0);
103}
104
105static inline void write_pmcntenclr(u64 val)
106{
107	write_sysreg(val, pmcntenclr_el0);
108}
109
110static inline void write_pmintenset(u64 val)
111{
112	write_sysreg(val, pmintenset_el1);
113}
114
115static inline void write_pmintenclr(u64 val)
116{
117	write_sysreg(val, pmintenclr_el1);
118}
119
120static inline void write_pmccfiltr(u64 val)
121{
122	write_sysreg(val, pmccfiltr_el0);
123}
124
125static inline u64 read_pmccfiltr(void)
126{
127	return read_sysreg(pmccfiltr_el0);
128}
129
130static inline void write_pmicfiltr(u64 val)
131{
132	write_sysreg_s(val, SYS_PMICFILTR_EL0);
133}
134
135static inline u64 read_pmicfiltr(void)
136{
137	return read_sysreg_s(SYS_PMICFILTR_EL0);
138}
139
140static inline void write_pmovsclr(u64 val)
141{
142	write_sysreg(val, pmovsclr_el0);
143}
144
145static inline u64 read_pmovsclr(void)
146{
147	return read_sysreg(pmovsclr_el0);
148}
149
150static inline void write_pmuserenr(u32 val)
151{
152	write_sysreg(val, pmuserenr_el0);
153}
154
155static inline void write_pmuacr(u64 val)
156{
157	write_sysreg_s(val, SYS_PMUACR_EL1);
158}
159
160static inline u64 read_pmceid0(void)
161{
162	return read_sysreg(pmceid0_el0);
163}
164
165static inline u64 read_pmceid1(void)
166{
167	return read_sysreg(pmceid1_el0);
168}
169
170static inline bool pmuv3_implemented(int pmuver)
171{
172	return !(pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||
173		 pmuver == ID_AA64DFR0_EL1_PMUVer_NI);
174}
175
176static inline bool is_pmuv3p4(int pmuver)
177{
178	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4;
179}
180
181static inline bool is_pmuv3p5(int pmuver)
182{
183	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5;
184}
185
186static inline bool is_pmuv3p9(int pmuver)
187{
188	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P9;
189}
190
191#endif