arm_dsu_pmu.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * ARM DynamIQ Shared Unit (DSU) PMU Low level register access routines.
  4 *
  5 * Copyright (C) ARM Limited, 2017.
  6 *
  7 * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
  8 */
  9
 10#include <linux/bitops.h>
 11#include <linux/build_bug.h>
 12#include <linux/compiler.h>
 13#include <linux/types.h>
 14#include <asm/barrier.h>
 15#include <asm/sysreg.h>
 16
 17
 18#define CLUSTERPMCR_EL1			sys_reg(3, 0, 15, 5, 0)
 19#define CLUSTERPMCNTENSET_EL1		sys_reg(3, 0, 15, 5, 1)
 20#define CLUSTERPMCNTENCLR_EL1		sys_reg(3, 0, 15, 5, 2)
 21#define CLUSTERPMOVSSET_EL1		sys_reg(3, 0, 15, 5, 3)
 22#define CLUSTERPMOVSCLR_EL1		sys_reg(3, 0, 15, 5, 4)
 23#define CLUSTERPMSELR_EL1		sys_reg(3, 0, 15, 5, 5)
 24#define CLUSTERPMINTENSET_EL1		sys_reg(3, 0, 15, 5, 6)
 25#define CLUSTERPMINTENCLR_EL1		sys_reg(3, 0, 15, 5, 7)
 26#define CLUSTERPMCCNTR_EL1		sys_reg(3, 0, 15, 6, 0)
 27#define CLUSTERPMXEVTYPER_EL1		sys_reg(3, 0, 15, 6, 1)
 28#define CLUSTERPMXEVCNTR_EL1		sys_reg(3, 0, 15, 6, 2)
 29#define CLUSTERPMMDCR_EL1		sys_reg(3, 0, 15, 6, 3)
 30#define CLUSTERPMCEID0_EL1		sys_reg(3, 0, 15, 6, 4)
 31#define CLUSTERPMCEID1_EL1		sys_reg(3, 0, 15, 6, 5)
 32
 33static inline u32 __dsu_pmu_read_pmcr(void)
 34{
 35	return read_sysreg_s(CLUSTERPMCR_EL1);
 36}
 37
 38static inline void __dsu_pmu_write_pmcr(u32 val)
 39{
 40	write_sysreg_s(val, CLUSTERPMCR_EL1);
 41	isb();
 42}
 43
 44static inline u32 __dsu_pmu_get_reset_overflow(void)
 45{
 46	u32 val = read_sysreg_s(CLUSTERPMOVSCLR_EL1);
 47	/* Clear the bit */
 48	write_sysreg_s(val, CLUSTERPMOVSCLR_EL1);
 49	isb();
 50	return val;
 51}
 52
 53static inline void __dsu_pmu_select_counter(int counter)
 54{
 55	write_sysreg_s(counter, CLUSTERPMSELR_EL1);
 56	isb();
 57}
 58
 59static inline u64 __dsu_pmu_read_counter(int counter)
 60{
 61	__dsu_pmu_select_counter(counter);
 62	return read_sysreg_s(CLUSTERPMXEVCNTR_EL1);
 63}
 64
 65static inline void __dsu_pmu_write_counter(int counter, u64 val)
 66{
 67	__dsu_pmu_select_counter(counter);
 68	write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1);
 69	isb();
 70}
 71
 72static inline void __dsu_pmu_set_event(int counter, u32 event)
 73{
 74	__dsu_pmu_select_counter(counter);
 75	write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1);
 76	isb();
 77}
 78
 79static inline u64 __dsu_pmu_read_pmccntr(void)
 80{
 81	return read_sysreg_s(CLUSTERPMCCNTR_EL1);
 82}
 83
 84static inline void __dsu_pmu_write_pmccntr(u64 val)
 85{
 86	write_sysreg_s(val, CLUSTERPMCCNTR_EL1);
 87	isb();
 88}
 89
 90static inline void __dsu_pmu_disable_counter(int counter)
 91{
 92	write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1);
 93	isb();
 94}
 95
 96static inline void __dsu_pmu_enable_counter(int counter)
 97{
 98	write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1);
 99	isb();
100}
101
102static inline void __dsu_pmu_counter_interrupt_enable(int counter)
103{
104	write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1);
105	isb();
106}
107
108static inline void __dsu_pmu_counter_interrupt_disable(int counter)
109{
110	write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1);
111	isb();
112}
113
114
115static inline u32 __dsu_pmu_read_pmceid(int n)
116{
117	switch (n) {
118	case 0:
119		return read_sysreg_s(CLUSTERPMCEID0_EL1);
120	case 1:
121		return read_sysreg_s(CLUSTERPMCEID1_EL1);
122	default:
123		BUILD_BUG();
124		return 0;
125	}
126}