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zynqmp.dtsi
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linux-6.19.14/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/power/xlnx-zynqmp-power.h> 20#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 compatible = "xlnx,zynqmp"; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 options { 29 u-boot { 30 compatible = "u-boot,config"; 31 bootscr-address = /bits/ 64 <0x20000000>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 #cooling-cells = <2>; 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 operating-points-v2 = <&cpu_opp_table>; 45 reg = <0x0>; 46 cpu-idle-states = <&CPU_SLEEP_0>; 47 next-level-cache = <&L2>; 48 }; 49 50 cpu1: cpu@1 { 51 #cooling-cells = <2>; 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 reg = <0x1>; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 next-level-cache = <&L2>; 59 }; 60 61 cpu2: cpu@2 { 62 #cooling-cells = <2>; 63 compatible = "arm,cortex-a53"; 64 device_type = "cpu"; 65 enable-method = "psci"; 66 reg = <0x2>; 67 operating-points-v2 = <&cpu_opp_table>; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 next-level-cache = <&L2>; 70 }; 71 72 cpu3: cpu@3 { 73 #cooling-cells = <2>; 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 reg = <0x3>; 78 operating-points-v2 = <&cpu_opp_table>; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 next-level-cache = <&L2>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 entry-method = "psci"; 91 92 CPU_SLEEP_0: cpu-sleep-0 { 93 compatible = "arm,idle-state"; 94 arm,psci-suspend-param = <0x40000000>; 95 local-timer-stop; 96 entry-latency-us = <300>; 97 exit-latency-us = <600>; 98 min-residency-us = <10000>; 99 }; 100 }; 101 }; 102 103 cpu_opp_table: opp-table-cpu { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 opp00 { 107 opp-hz = /bits/ 64 <1199999988>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <500000>; 110 }; 111 opp01 { 112 opp-hz = /bits/ 64 <599999994>; 113 opp-microvolt = <1000000>; 114 clock-latency-ns = <500000>; 115 }; 116 opp02 { 117 opp-hz = /bits/ 64 <399999996>; 118 opp-microvolt = <1000000>; 119 clock-latency-ns = <500000>; 120 }; 121 opp03 { 122 opp-hz = /bits/ 64 <299999997>; 123 opp-microvolt = <1000000>; 124 clock-latency-ns = <500000>; 125 }; 126 }; 127 128 reserved-memory { 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 rproc_0_fw_image: memory@3ed00000 { 134 no-map; 135 reg = <0x0 0x3ed00000 0x0 0x40000>; 136 }; 137 138 rproc_1_fw_image: memory@3ef00000 { 139 no-map; 140 reg = <0x0 0x3ef00000 0x0 0x40000>; 141 }; 142 }; 143 144 zynqmp_ipi: zynqmp-ipi { 145 bootph-all; 146 compatible = "xlnx,zynqmp-ipi-mailbox"; 147 interrupt-parent = <&gic>; 148 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 149 xlnx,ipi-id = <0>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 ipi_mailbox_pmu1: mailbox@ff9905c0 { 155 bootph-all; 156 compatible = "xlnx,zynqmp-ipi-dest-mailbox"; 157 reg = <0x0 0xff9905c0 0x0 0x20>, 158 <0x0 0xff9905e0 0x0 0x20>, 159 <0x0 0xff990e80 0x0 0x20>, 160 <0x0 0xff990ea0 0x0 0x20>; 161 reg-names = "local_request_region", 162 "local_response_region", 163 "remote_request_region", 164 "remote_response_region"; 165 #mbox-cells = <1>; 166 xlnx,ipi-id = <4>; 167 }; 168 }; 169 170 dcc: dcc { 171 compatible = "arm,dcc"; 172 status = "disabled"; 173 bootph-all; 174 }; 175 176 pmu { 177 compatible = "arm,cortex-a53-pmu"; 178 interrupt-parent = <&gic>; 179 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-affinity = <&cpu0>, 184 <&cpu1>, 185 <&cpu2>, 186 <&cpu3>; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0", "arm,psci-0.2"; 191 method = "smc"; 192 }; 193 194 firmware { 195 zynqmp_firmware: zynqmp-firmware { 196 compatible = "xlnx,zynqmp-firmware"; 197 #power-domain-cells = <1>; 198 method = "smc"; 199 bootph-all; 200 201 zynqmp_power: power-management { 202 bootph-all; 203 compatible = "xlnx,zynqmp-power"; 204 interrupt-parent = <&gic>; 205 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 206 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 207 mbox-names = "tx", "rx"; 208 }; 209 210 soc-nvmem { 211 compatible = "xlnx,zynqmp-nvmem-fw"; 212 nvmem-layout { 213 compatible = "fixed-layout"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 217 soc_revision: soc-revision@0 { 218 reg = <0x0 0x4>; 219 }; 220 /* efuse access */ 221 efuse_dna: efuse-dna@c { 222 reg = <0xc 0xc>; 223 }; 224 efuse_usr0: efuse-usr0@20 { 225 reg = <0x20 0x4>; 226 }; 227 efuse_usr1: efuse-usr1@24 { 228 reg = <0x24 0x4>; 229 }; 230 efuse_usr2: efuse-usr2@28 { 231 reg = <0x28 0x4>; 232 }; 233 efuse_usr3: efuse-usr3@2c { 234 reg = <0x2c 0x4>; 235 }; 236 efuse_usr4: efuse-usr4@30 { 237 reg = <0x30 0x4>; 238 }; 239 efuse_usr5: efuse-usr5@34 { 240 reg = <0x34 0x4>; 241 }; 242 efuse_usr6: efuse-usr6@38 { 243 reg = <0x38 0x4>; 244 }; 245 efuse_usr7: efuse-usr7@3c { 246 reg = <0x3c 0x4>; 247 }; 248 efuse_miscusr: efuse-miscusr@40 { 249 reg = <0x40 0x4>; 250 }; 251 efuse_chash: efuse-chash@50 { 252 reg = <0x50 0x4>; 253 }; 254 efuse_pufmisc: efuse-pufmisc@54 { 255 reg = <0x54 0x4>; 256 }; 257 efuse_sec: efuse-sec@58 { 258 reg = <0x58 0x4>; 259 }; 260 efuse_spkid: efuse-spkid@5c { 261 reg = <0x5c 0x4>; 262 }; 263 efuse_aeskey: efuse-aeskey@60 { 264 reg = <0x60 0x20>; 265 }; 266 efuse_ppk0hash: efuse-ppk0hash@a0 { 267 reg = <0xa0 0x30>; 268 }; 269 efuse_ppk1hash: efuse-ppk1hash@d0 { 270 reg = <0xd0 0x30>; 271 }; 272 efuse_pufuser: efuse-pufuser@100 { 273 reg = <0x100 0x7F>; 274 }; 275 }; 276 }; 277 278 zynqmp_pcap: pcap { 279 compatible = "xlnx,zynqmp-pcap-fpga"; 280 }; 281 282 xlnx_aes: zynqmp-aes { 283 compatible = "xlnx,zynqmp-aes"; 284 }; 285 286 zynqmp_reset: reset-controller { 287 compatible = "xlnx,zynqmp-reset"; 288 #reset-cells = <1>; 289 }; 290 291 pinctrl0: pinctrl { 292 compatible = "xlnx,zynqmp-pinctrl"; 293 status = "disabled"; 294 }; 295 296 modepin_gpio: gpio { 297 compatible = "xlnx,zynqmp-gpio-modepin"; 298 gpio-controller; 299 #gpio-cells = <2>; 300 }; 301 }; 302 }; 303 304 timer { 305 compatible = "arm,armv8-timer"; 306 interrupt-parent = <&gic>; 307 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 308 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 309 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 310 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 311 }; 312 313 fpga_full: fpga-region { 314 compatible = "fpga-region"; 315 fpga-mgr = <&zynqmp_pcap>; 316 #address-cells = <2>; 317 #size-cells = <2>; 318 ranges; 319 }; 320 321 rproc_lockstep: remoteproc@ffe00000 { 322 compatible = "xlnx,zynqmp-r5fss"; 323 xlnx,cluster-mode = <1>; 324 xlnx,tcm-mode = <1>; 325 326 #address-cells = <2>; 327 #size-cells = <2>; 328 329 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 330 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 331 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, 332 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; 333 334 r5f@0 { 335 compatible = "xlnx,zynqmp-r5f"; 336 reg = <0x0 0x0 0x0 0x10000>, 337 <0x0 0x20000 0x0 0x10000>, 338 <0x0 0x10000 0x0 0x10000>, 339 <0x0 0x30000 0x0 0x10000>; 340 reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; 341 power-domains = <&zynqmp_firmware PD_RPU_0>, 342 <&zynqmp_firmware PD_R5_0_ATCM>, 343 <&zynqmp_firmware PD_R5_0_BTCM>, 344 <&zynqmp_firmware PD_R5_1_ATCM>, 345 <&zynqmp_firmware PD_R5_1_BTCM>; 346 memory-region = <&rproc_0_fw_image>; 347 }; 348 349 r5f@1 { 350 compatible = "xlnx,zynqmp-r5f"; 351 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 352 reg-names = "atcm0", "btcm0"; 353 power-domains = <&zynqmp_firmware PD_RPU_1>, 354 <&zynqmp_firmware PD_R5_1_ATCM>, 355 <&zynqmp_firmware PD_R5_1_BTCM>; 356 memory-region = <&rproc_1_fw_image>; 357 }; 358 }; 359 360 rproc_split: remoteproc-split@ffe00000 { 361 status = "disabled"; 362 compatible = "xlnx,zynqmp-r5fss"; 363 xlnx,cluster-mode = <0>; 364 xlnx,tcm-mode = <0>; 365 366 #address-cells = <2>; 367 #size-cells = <2>; 368 369 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 370 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 371 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, 372 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; 373 374 r5f@0 { 375 compatible = "xlnx,zynqmp-r5f"; 376 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; 377 reg-names = "atcm0", "btcm0"; 378 power-domains = <&zynqmp_firmware PD_RPU_0>, 379 <&zynqmp_firmware PD_R5_0_ATCM>, 380 <&zynqmp_firmware PD_R5_0_BTCM>; 381 memory-region = <&rproc_0_fw_image>; 382 }; 383 384 r5f@1 { 385 compatible = "xlnx,zynqmp-r5f"; 386 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 387 reg-names = "atcm0", "btcm0"; 388 power-domains = <&zynqmp_firmware PD_RPU_1>, 389 <&zynqmp_firmware PD_R5_1_ATCM>, 390 <&zynqmp_firmware PD_R5_1_BTCM>; 391 memory-region = <&rproc_1_fw_image>; 392 }; 393 }; 394 395 ams { 396 compatible = "iio-hwmon"; 397 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, 398 <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, 399 <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, 400 <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, 401 <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, 402 <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, 403 <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, 404 <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, 405 <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, 406 <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; 407 }; 408 409 410 tsens_apu: thermal-sensor-apu { 411 compatible = "generic-adc-thermal"; 412 #thermal-sensor-cells = <0>; 413 io-channels = <&xilinx_ams 7>; 414 io-channel-names = "sensor-channel"; 415 }; 416 417 tsens_rpu: thermal-sensor-rpu { 418 compatible = "generic-adc-thermal"; 419 #thermal-sensor-cells = <0>; 420 io-channels = <&xilinx_ams 8>; 421 io-channel-names = "sensor-channel"; 422 }; 423 424 tsens_pl: thermal-sensor-pl { 425 compatible = "generic-adc-thermal"; 426 #thermal-sensor-cells = <0>; 427 io-channels = <&xilinx_ams 20>; 428 io-channel-names = "sensor-channel"; 429 }; 430 431 thermal-zones { 432 apu-thermal { 433 polling-delay-passive = <1000>; 434 polling-delay = <5000>; 435 thermal-sensors = <&tsens_apu>; 436 437 trips { 438 apu_passive: passive { 439 temperature = <93000>; 440 hysteresis = <3500>; 441 type = "passive"; 442 }; 443 444 apu_critical: critical { 445 temperature = <96500>; 446 hysteresis = <3500>; 447 type = "critical"; 448 }; 449 }; 450 451 cooling-maps { 452 map { 453 trip = <&apu_passive>; 454 cooling-device = 455 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 456 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 457 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 458 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 459 }; 460 }; 461 }; 462 463 rpu-thermal { 464 polling-delay = <10000>; 465 thermal-sensors = <&tsens_rpu>; 466 467 trips { 468 critical { 469 temperature = <96500>; 470 hysteresis = <3500>; 471 type = "critical"; 472 }; 473 }; 474 }; 475 476 pl-thermal { 477 polling-delay = <10000>; 478 thermal-sensors = <&tsens_pl>; 479 480 trips { 481 critical { 482 temperature = <96500>; 483 hysteresis = <3500>; 484 type = "critical"; 485 }; 486 }; 487 }; 488 }; 489 490 amba: axi { 491 compatible = "simple-bus"; 492 bootph-all; 493 #address-cells = <2>; 494 #size-cells = <2>; 495 ranges; 496 497 can0: can@ff060000 { 498 compatible = "xlnx,zynq-can-1.0"; 499 status = "disabled"; 500 clock-names = "can_clk", "pclk"; 501 reg = <0x0 0xff060000 0x0 0x1000>; 502 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-parent = <&gic>; 504 tx-fifo-depth = <0x40>; 505 rx-fifo-depth = <0x40>; 506 resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; 507 power-domains = <&zynqmp_firmware PD_CAN_0>; 508 }; 509 510 can1: can@ff070000 { 511 compatible = "xlnx,zynq-can-1.0"; 512 status = "disabled"; 513 clock-names = "can_clk", "pclk"; 514 reg = <0x0 0xff070000 0x0 0x1000>; 515 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-parent = <&gic>; 517 tx-fifo-depth = <0x40>; 518 rx-fifo-depth = <0x40>; 519 resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; 520 power-domains = <&zynqmp_firmware PD_CAN_1>; 521 }; 522 523 cci: cci@fd6e0000 { 524 compatible = "arm,cci-400"; 525 status = "disabled"; 526 reg = <0x0 0xfd6e0000 0x0 0x9000>; 527 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 531 pmu@9000 { 532 compatible = "arm,cci-400-pmu,r1"; 533 reg = <0x9000 0x5000>; 534 interrupt-parent = <&gic>; 535 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 540 }; 541 }; 542 543 cpu0_debug: debug@fec10000 { 544 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 545 reg = <0x0 0xfec10000 0x0 0x1000>; 546 clock-names = "apb_pclk"; 547 cpu = <&cpu0>; 548 status = "disabled"; 549 }; 550 551 cpu1_debug: debug@fed10000 { 552 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 553 reg = <0x0 0xfed10000 0x0 0x1000>; 554 clock-names = "apb_pclk"; 555 cpu = <&cpu1>; 556 status = "disabled"; 557 }; 558 559 cpu2_debug: debug@fee10000 { 560 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 561 reg = <0x0 0xfee10000 0x0 0x1000>; 562 clock-names = "apb_pclk"; 563 cpu = <&cpu2>; 564 status = "disabled"; 565 }; 566 567 cpu3_debug: debug@fef10000 { 568 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 569 reg = <0x0 0xfef10000 0x0 0x1000>; 570 clock-names = "apb_pclk"; 571 cpu = <&cpu3>; 572 status = "disabled"; 573 }; 574 575 /* GDMA */ 576 fpd_dma_chan1: dma-controller@fd500000 { 577 status = "disabled"; 578 compatible = "xlnx,zynqmp-dma-1.0"; 579 reg = <0x0 0xfd500000 0x0 0x1000>; 580 interrupt-parent = <&gic>; 581 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 582 clock-names = "clk_main", "clk_apb"; 583 #dma-cells = <1>; 584 xlnx,bus-width = <128>; 585 /* iommus = <&smmu 0x14e8>; */ 586 power-domains = <&zynqmp_firmware PD_GDMA>; 587 }; 588 589 fpd_dma_chan2: dma-controller@fd510000 { 590 status = "disabled"; 591 compatible = "xlnx,zynqmp-dma-1.0"; 592 reg = <0x0 0xfd510000 0x0 0x1000>; 593 interrupt-parent = <&gic>; 594 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 595 clock-names = "clk_main", "clk_apb"; 596 #dma-cells = <1>; 597 xlnx,bus-width = <128>; 598 /* iommus = <&smmu 0x14e9>; */ 599 power-domains = <&zynqmp_firmware PD_GDMA>; 600 }; 601 602 fpd_dma_chan3: dma-controller@fd520000 { 603 status = "disabled"; 604 compatible = "xlnx,zynqmp-dma-1.0"; 605 reg = <0x0 0xfd520000 0x0 0x1000>; 606 interrupt-parent = <&gic>; 607 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 608 clock-names = "clk_main", "clk_apb"; 609 #dma-cells = <1>; 610 xlnx,bus-width = <128>; 611 /* iommus = <&smmu 0x14ea>; */ 612 power-domains = <&zynqmp_firmware PD_GDMA>; 613 }; 614 615 fpd_dma_chan4: dma-controller@fd530000 { 616 status = "disabled"; 617 compatible = "xlnx,zynqmp-dma-1.0"; 618 reg = <0x0 0xfd530000 0x0 0x1000>; 619 interrupt-parent = <&gic>; 620 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 621 clock-names = "clk_main", "clk_apb"; 622 #dma-cells = <1>; 623 xlnx,bus-width = <128>; 624 /* iommus = <&smmu 0x14eb>; */ 625 power-domains = <&zynqmp_firmware PD_GDMA>; 626 }; 627 628 fpd_dma_chan5: dma-controller@fd540000 { 629 status = "disabled"; 630 compatible = "xlnx,zynqmp-dma-1.0"; 631 reg = <0x0 0xfd540000 0x0 0x1000>; 632 interrupt-parent = <&gic>; 633 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 634 clock-names = "clk_main", "clk_apb"; 635 #dma-cells = <1>; 636 xlnx,bus-width = <128>; 637 /* iommus = <&smmu 0x14ec>; */ 638 power-domains = <&zynqmp_firmware PD_GDMA>; 639 }; 640 641 fpd_dma_chan6: dma-controller@fd550000 { 642 status = "disabled"; 643 compatible = "xlnx,zynqmp-dma-1.0"; 644 reg = <0x0 0xfd550000 0x0 0x1000>; 645 interrupt-parent = <&gic>; 646 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 647 clock-names = "clk_main", "clk_apb"; 648 #dma-cells = <1>; 649 xlnx,bus-width = <128>; 650 /* iommus = <&smmu 0x14ed>; */ 651 power-domains = <&zynqmp_firmware PD_GDMA>; 652 }; 653 654 fpd_dma_chan7: dma-controller@fd560000 { 655 status = "disabled"; 656 compatible = "xlnx,zynqmp-dma-1.0"; 657 reg = <0x0 0xfd560000 0x0 0x1000>; 658 interrupt-parent = <&gic>; 659 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 660 clock-names = "clk_main", "clk_apb"; 661 #dma-cells = <1>; 662 xlnx,bus-width = <128>; 663 /* iommus = <&smmu 0x14ee>; */ 664 power-domains = <&zynqmp_firmware PD_GDMA>; 665 }; 666 667 fpd_dma_chan8: dma-controller@fd570000 { 668 status = "disabled"; 669 compatible = "xlnx,zynqmp-dma-1.0"; 670 reg = <0x0 0xfd570000 0x0 0x1000>; 671 interrupt-parent = <&gic>; 672 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 673 clock-names = "clk_main", "clk_apb"; 674 #dma-cells = <1>; 675 xlnx,bus-width = <128>; 676 /* iommus = <&smmu 0x14ef>; */ 677 power-domains = <&zynqmp_firmware PD_GDMA>; 678 }; 679 680 gic: interrupt-controller@f9010000 { 681 compatible = "arm,gic-400"; 682 #interrupt-cells = <3>; 683 reg = <0x0 0xf9010000 0x0 0x10000>, 684 <0x0 0xf9020000 0x0 0x20000>, 685 <0x0 0xf9040000 0x0 0x20000>, 686 <0x0 0xf9060000 0x0 0x20000>; 687 interrupt-controller; 688 interrupt-parent = <&gic>; 689 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 690 }; 691 692 gpu: gpu@fd4b0000 { 693 status = "disabled"; 694 compatible = "xlnx,zynqmp-mali", "arm,mali-400"; 695 reg = <0x0 0xfd4b0000 0x0 0x10000>; 696 interrupt-parent = <&gic>; 697 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; 704 clock-names = "bus", "core"; 705 power-domains = <&zynqmp_firmware PD_GPU>; 706 }; 707 708 /* LPDDMA default allows only secured access. inorder to enable 709 * These dma channels, Users should ensure that these dma 710 * Channels are allowed for non secure access. 711 */ 712 lpd_dma_chan1: dma-controller@ffa80000 { 713 status = "disabled"; 714 compatible = "xlnx,zynqmp-dma-1.0"; 715 reg = <0x0 0xffa80000 0x0 0x1000>; 716 interrupt-parent = <&gic>; 717 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 718 clock-names = "clk_main", "clk_apb"; 719 #dma-cells = <1>; 720 xlnx,bus-width = <64>; 721 /* iommus = <&smmu 0x868>; */ 722 power-domains = <&zynqmp_firmware PD_ADMA>; 723 }; 724 725 lpd_dma_chan2: dma-controller@ffa90000 { 726 status = "disabled"; 727 compatible = "xlnx,zynqmp-dma-1.0"; 728 reg = <0x0 0xffa90000 0x0 0x1000>; 729 interrupt-parent = <&gic>; 730 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 731 clock-names = "clk_main", "clk_apb"; 732 #dma-cells = <1>; 733 xlnx,bus-width = <64>; 734 /* iommus = <&smmu 0x869>; */ 735 power-domains = <&zynqmp_firmware PD_ADMA>; 736 }; 737 738 lpd_dma_chan3: dma-controller@ffaa0000 { 739 status = "disabled"; 740 compatible = "xlnx,zynqmp-dma-1.0"; 741 reg = <0x0 0xffaa0000 0x0 0x1000>; 742 interrupt-parent = <&gic>; 743 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 744 clock-names = "clk_main", "clk_apb"; 745 #dma-cells = <1>; 746 xlnx,bus-width = <64>; 747 /* iommus = <&smmu 0x86a>; */ 748 power-domains = <&zynqmp_firmware PD_ADMA>; 749 }; 750 751 lpd_dma_chan4: dma-controller@ffab0000 { 752 status = "disabled"; 753 compatible = "xlnx,zynqmp-dma-1.0"; 754 reg = <0x0 0xffab0000 0x0 0x1000>; 755 interrupt-parent = <&gic>; 756 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 757 clock-names = "clk_main", "clk_apb"; 758 #dma-cells = <1>; 759 xlnx,bus-width = <64>; 760 /* iommus = <&smmu 0x86b>; */ 761 power-domains = <&zynqmp_firmware PD_ADMA>; 762 }; 763 764 lpd_dma_chan5: dma-controller@ffac0000 { 765 status = "disabled"; 766 compatible = "xlnx,zynqmp-dma-1.0"; 767 reg = <0x0 0xffac0000 0x0 0x1000>; 768 interrupt-parent = <&gic>; 769 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 770 clock-names = "clk_main", "clk_apb"; 771 #dma-cells = <1>; 772 xlnx,bus-width = <64>; 773 /* iommus = <&smmu 0x86c>; */ 774 power-domains = <&zynqmp_firmware PD_ADMA>; 775 }; 776 777 lpd_dma_chan6: dma-controller@ffad0000 { 778 status = "disabled"; 779 compatible = "xlnx,zynqmp-dma-1.0"; 780 reg = <0x0 0xffad0000 0x0 0x1000>; 781 interrupt-parent = <&gic>; 782 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 783 clock-names = "clk_main", "clk_apb"; 784 #dma-cells = <1>; 785 xlnx,bus-width = <64>; 786 /* iommus = <&smmu 0x86d>; */ 787 power-domains = <&zynqmp_firmware PD_ADMA>; 788 }; 789 790 lpd_dma_chan7: dma-controller@ffae0000 { 791 status = "disabled"; 792 compatible = "xlnx,zynqmp-dma-1.0"; 793 reg = <0x0 0xffae0000 0x0 0x1000>; 794 interrupt-parent = <&gic>; 795 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 796 clock-names = "clk_main", "clk_apb"; 797 #dma-cells = <1>; 798 xlnx,bus-width = <64>; 799 /* iommus = <&smmu 0x86e>; */ 800 power-domains = <&zynqmp_firmware PD_ADMA>; 801 }; 802 803 lpd_dma_chan8: dma-controller@ffaf0000 { 804 status = "disabled"; 805 compatible = "xlnx,zynqmp-dma-1.0"; 806 reg = <0x0 0xffaf0000 0x0 0x1000>; 807 interrupt-parent = <&gic>; 808 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 809 clock-names = "clk_main", "clk_apb"; 810 #dma-cells = <1>; 811 xlnx,bus-width = <64>; 812 /* iommus = <&smmu 0x86f>; */ 813 power-domains = <&zynqmp_firmware PD_ADMA>; 814 }; 815 816 mc: memory-controller@fd070000 { 817 compatible = "xlnx,zynqmp-ddrc-2.40a"; 818 reg = <0x0 0xfd070000 0x0 0x30000>; 819 interrupt-parent = <&gic>; 820 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 821 }; 822 823 nand0: nand-controller@ff100000 { 824 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 825 status = "disabled"; 826 reg = <0x0 0xff100000 0x0 0x1000>; 827 clock-names = "controller", "bus"; 828 interrupt-parent = <&gic>; 829 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 /* iommus = <&smmu 0x872>; */ 833 power-domains = <&zynqmp_firmware PD_NAND>; 834 }; 835 836 gem0: ethernet@ff0b0000 { 837 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 838 status = "disabled"; 839 interrupt-parent = <&gic>; 840 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 842 reg = <0x0 0xff0b0000 0x0 0x1000>; 843 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 844 /* iommus = <&smmu 0x874>; */ 845 power-domains = <&zynqmp_firmware PD_ETH_0>; 846 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 847 reset-names = "gem0_rst"; 848 }; 849 850 gem1: ethernet@ff0c0000 { 851 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 852 status = "disabled"; 853 interrupt-parent = <&gic>; 854 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 856 reg = <0x0 0xff0c0000 0x0 0x1000>; 857 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 858 /* iommus = <&smmu 0x875>; */ 859 power-domains = <&zynqmp_firmware PD_ETH_1>; 860 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 861 reset-names = "gem1_rst"; 862 }; 863 864 gem2: ethernet@ff0d0000 { 865 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 866 status = "disabled"; 867 interrupt-parent = <&gic>; 868 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 870 reg = <0x0 0xff0d0000 0x0 0x1000>; 871 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 872 /* iommus = <&smmu 0x876>; */ 873 power-domains = <&zynqmp_firmware PD_ETH_2>; 874 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 875 reset-names = "gem2_rst"; 876 }; 877 878 gem3: ethernet@ff0e0000 { 879 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 880 status = "disabled"; 881 interrupt-parent = <&gic>; 882 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 884 reg = <0x0 0xff0e0000 0x0 0x1000>; 885 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 886 /* iommus = <&smmu 0x877>; */ 887 power-domains = <&zynqmp_firmware PD_ETH_3>; 888 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 889 reset-names = "gem3_rst"; 890 }; 891 892 gpio: gpio@ff0a0000 { 893 compatible = "xlnx,zynqmp-gpio-1.0"; 894 status = "disabled"; 895 #gpio-cells = <0x2>; 896 gpio-controller; 897 interrupt-parent = <&gic>; 898 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 reg = <0x0 0xff0a0000 0x0 0x1000>; 902 power-domains = <&zynqmp_firmware PD_GPIO>; 903 }; 904 905 i2c0: i2c@ff020000 { 906 compatible = "cdns,i2c-r1p14"; 907 status = "disabled"; 908 interrupt-parent = <&gic>; 909 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 910 clock-frequency = <400000>; 911 reg = <0x0 0xff020000 0x0 0x1000>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 power-domains = <&zynqmp_firmware PD_I2C_0>; 915 }; 916 917 i2c1: i2c@ff030000 { 918 compatible = "cdns,i2c-r1p14"; 919 status = "disabled"; 920 interrupt-parent = <&gic>; 921 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 922 clock-frequency = <400000>; 923 reg = <0x0 0xff030000 0x0 0x1000>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 power-domains = <&zynqmp_firmware PD_I2C_1>; 927 }; 928 929 ocm: memory-controller@ff960000 { 930 compatible = "xlnx,zynqmp-ocmc-1.0"; 931 reg = <0x0 0xff960000 0x0 0x1000>; 932 interrupt-parent = <&gic>; 933 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 934 }; 935 936 pcie: pcie@fd0e0000 { 937 compatible = "xlnx,nwl-pcie-2.11"; 938 status = "disabled"; 939 #address-cells = <3>; 940 #size-cells = <2>; 941 #interrupt-cells = <1>; 942 msi-controller; 943 device_type = "pci"; 944 interrupt-parent = <&gic>; 945 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ 949 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ 950 interrupt-names = "misc", "dummy", "intx", 951 "msi1", "msi0"; 952 msi-parent = <&pcie>; 953 reg = <0x0 0xfd0e0000 0x0 0x1000>, 954 <0x0 0xfd480000 0x0 0x1000>, 955 <0x80 0x00000000 0x0 0x10000000>; 956 reg-names = "breg", "pcireg", "cfg"; 957 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 958 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 959 bus-range = <0x00 0xff>; 960 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 961 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 962 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 963 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 964 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 965 /* iommus = <&smmu 0x4d0>; */ 966 power-domains = <&zynqmp_firmware PD_PCIE>; 967 pcie_intc: legacy-interrupt-controller { 968 interrupt-controller; 969 #address-cells = <0>; 970 #interrupt-cells = <1>; 971 }; 972 }; 973 974 qspi: spi@ff0f0000 { 975 bootph-all; 976 compatible = "xlnx,zynqmp-qspi-1.0"; 977 status = "disabled"; 978 clock-names = "ref_clk", "pclk"; 979 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-parent = <&gic>; 981 num-cs = <1>; 982 reg = <0x0 0xff0f0000 0x0 0x1000>, 983 <0x0 0xc0000000 0x0 0x8000000>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 /* iommus = <&smmu 0x873>; */ 987 power-domains = <&zynqmp_firmware PD_QSPI>; 988 }; 989 990 psgtr: phy@fd400000 { 991 compatible = "xlnx,zynqmp-psgtr-v1.1"; 992 status = "disabled"; 993 reg = <0x0 0xfd400000 0x0 0x40000>, 994 <0x0 0xfd3d0000 0x0 0x1000>; 995 reg-names = "serdes", "siou"; 996 #phy-cells = <4>; 997 }; 998 999 rtc: rtc@ffa60000 { 1000 compatible = "xlnx,zynqmp-rtc"; 1001 status = "disabled"; 1002 reg = <0x0 0xffa60000 0x0 0x100>; 1003 interrupt-parent = <&gic>; 1004 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1006 interrupt-names = "alarm", "sec"; 1007 calibration = <0x7FFF>; 1008 }; 1009 1010 sata: ahci@fd0c0000 { 1011 compatible = "ceva,ahci-1v84"; 1012 status = "disabled"; 1013 reg = <0x0 0xfd0c0000 0x0 0x2000>; 1014 interrupt-parent = <&gic>; 1015 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1016 power-domains = <&zynqmp_firmware PD_SATA>; 1017 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 1018 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ 1019 }; 1020 1021 sdhci0: mmc@ff160000 { 1022 bootph-all; 1023 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 1024 status = "disabled"; 1025 interrupt-parent = <&gic>; 1026 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1027 reg = <0x0 0xff160000 0x0 0x1000>; 1028 clock-names = "clk_xin", "clk_ahb"; 1029 /* iommus = <&smmu 0x870>; */ 1030 #clock-cells = <1>; 1031 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 1032 power-domains = <&zynqmp_firmware PD_SD_0>; 1033 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; 1034 }; 1035 1036 sdhci1: mmc@ff170000 { 1037 bootph-all; 1038 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 1039 status = "disabled"; 1040 interrupt-parent = <&gic>; 1041 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1042 reg = <0x0 0xff170000 0x0 0x1000>; 1043 clock-names = "clk_xin", "clk_ahb"; 1044 /* iommus = <&smmu 0x871>; */ 1045 #clock-cells = <1>; 1046 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 1047 power-domains = <&zynqmp_firmware PD_SD_1>; 1048 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; 1049 }; 1050 1051 smmu: iommu@fd800000 { 1052 compatible = "arm,mmu-500"; 1053 reg = <0x0 0xfd800000 0x0 0x20000>; 1054 #iommu-cells = <1>; 1055 status = "disabled"; 1056 #global-interrupts = <1>; 1057 interrupt-parent = <&gic>; 1058 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1075 }; 1076 1077 spi0: spi@ff040000 { 1078 compatible = "cdns,spi-r1p6"; 1079 status = "disabled"; 1080 interrupt-parent = <&gic>; 1081 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1082 reg = <0x0 0xff040000 0x0 0x1000>; 1083 clock-names = "ref_clk", "pclk"; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 power-domains = <&zynqmp_firmware PD_SPI_0>; 1087 }; 1088 1089 spi1: spi@ff050000 { 1090 compatible = "cdns,spi-r1p6"; 1091 status = "disabled"; 1092 interrupt-parent = <&gic>; 1093 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1094 reg = <0x0 0xff050000 0x0 0x1000>; 1095 clock-names = "ref_clk", "pclk"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 power-domains = <&zynqmp_firmware PD_SPI_1>; 1099 }; 1100 1101 ttc0: timer@ff110000 { 1102 compatible = "cdns,ttc"; 1103 status = "disabled"; 1104 interrupt-parent = <&gic>; 1105 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1108 reg = <0x0 0xff110000 0x0 0x1000>; 1109 timer-width = <32>; 1110 power-domains = <&zynqmp_firmware PD_TTC_0>; 1111 }; 1112 1113 ttc1: timer@ff120000 { 1114 compatible = "cdns,ttc"; 1115 status = "disabled"; 1116 interrupt-parent = <&gic>; 1117 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1120 reg = <0x0 0xff120000 0x0 0x1000>; 1121 timer-width = <32>; 1122 power-domains = <&zynqmp_firmware PD_TTC_1>; 1123 }; 1124 1125 ttc2: timer@ff130000 { 1126 compatible = "cdns,ttc"; 1127 status = "disabled"; 1128 interrupt-parent = <&gic>; 1129 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1132 reg = <0x0 0xff130000 0x0 0x1000>; 1133 timer-width = <32>; 1134 power-domains = <&zynqmp_firmware PD_TTC_2>; 1135 }; 1136 1137 ttc3: timer@ff140000 { 1138 compatible = "cdns,ttc"; 1139 status = "disabled"; 1140 interrupt-parent = <&gic>; 1141 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1144 reg = <0x0 0xff140000 0x0 0x1000>; 1145 timer-width = <32>; 1146 power-domains = <&zynqmp_firmware PD_TTC_3>; 1147 }; 1148 1149 uart0: serial@ff000000 { 1150 bootph-all; 1151 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 1152 status = "disabled"; 1153 interrupt-parent = <&gic>; 1154 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1155 reg = <0x0 0xff000000 0x0 0x1000>; 1156 clock-names = "uart_clk", "pclk"; 1157 power-domains = <&zynqmp_firmware PD_UART_0>; 1158 resets = <&zynqmp_reset ZYNQMP_RESET_UART0>; 1159 }; 1160 1161 uart1: serial@ff010000 { 1162 bootph-all; 1163 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 1164 status = "disabled"; 1165 interrupt-parent = <&gic>; 1166 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1167 reg = <0x0 0xff010000 0x0 0x1000>; 1168 clock-names = "uart_clk", "pclk"; 1169 power-domains = <&zynqmp_firmware PD_UART_1>; 1170 resets = <&zynqmp_reset ZYNQMP_RESET_UART1>; 1171 }; 1172 1173 usb0: usb@ff9d0000 { 1174 #address-cells = <2>; 1175 #size-cells = <2>; 1176 status = "disabled"; 1177 compatible = "xlnx,zynqmp-dwc3"; 1178 reg = <0x0 0xff9d0000 0x0 0x100>; 1179 clock-names = "bus_clk", "ref_clk"; 1180 power-domains = <&zynqmp_firmware PD_USB_0>; 1181 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 1182 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 1183 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 1184 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 1185 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 1186 ranges; 1187 1188 dwc3_0: usb@fe200000 { 1189 compatible = "snps,dwc3"; 1190 status = "disabled"; 1191 reg = <0x0 0xfe200000 0x0 0x40000>; 1192 interrupt-parent = <&gic>; 1193 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1194 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1198 clock-names = "ref"; 1199 /* iommus = <&smmu 0x860>; */ 1200 snps,quirk-frame-length-adjustment = <0x20>; 1201 snps,resume-hs-terminations; 1202 /* dma-coherent; */ 1203 }; 1204 }; 1205 1206 usb1: usb@ff9e0000 { 1207 #address-cells = <2>; 1208 #size-cells = <2>; 1209 status = "disabled"; 1210 compatible = "xlnx,zynqmp-dwc3"; 1211 reg = <0x0 0xff9e0000 0x0 0x100>; 1212 clock-names = "bus_clk", "ref_clk"; 1213 power-domains = <&zynqmp_firmware PD_USB_1>; 1214 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 1215 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 1216 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 1217 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 1218 ranges; 1219 1220 dwc3_1: usb@fe300000 { 1221 compatible = "snps,dwc3"; 1222 status = "disabled"; 1223 reg = <0x0 0xfe300000 0x0 0x40000>; 1224 interrupt-parent = <&gic>; 1225 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1226 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1230 clock-names = "ref"; 1231 /* iommus = <&smmu 0x861>; */ 1232 snps,quirk-frame-length-adjustment = <0x20>; 1233 snps,resume-hs-terminations; 1234 /* dma-coherent; */ 1235 }; 1236 }; 1237 1238 watchdog0: watchdog@fd4d0000 { 1239 compatible = "cdns,wdt-r1p2"; 1240 status = "disabled"; 1241 interrupt-parent = <&gic>; 1242 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 1243 reg = <0x0 0xfd4d0000 0x0 0x1000>; 1244 timeout-sec = <60>; 1245 reset-on-timeout; 1246 }; 1247 1248 lpd_watchdog: watchdog@ff150000 { 1249 compatible = "cdns,wdt-r1p2"; 1250 status = "disabled"; 1251 interrupt-parent = <&gic>; 1252 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1253 reg = <0x0 0xff150000 0x0 0x1000>; 1254 timeout-sec = <10>; 1255 }; 1256 1257 xilinx_ams: ams@ffa50000 { 1258 compatible = "xlnx,zynqmp-ams"; 1259 interrupt-parent = <&gic>; 1260 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1261 reg = <0x0 0xffa50000 0x0 0x800>; 1262 #address-cells = <1>; 1263 #size-cells = <1>; 1264 #io-channel-cells = <1>; 1265 ranges = <0 0 0xffa50800 0x800>; 1266 1267 ams_ps: ams-ps@0 { 1268 compatible = "xlnx,zynqmp-ams-ps"; 1269 status = "disabled"; 1270 reg = <0x0 0x400>; 1271 }; 1272 1273 ams_pl: ams-pl@400 { 1274 compatible = "xlnx,zynqmp-ams-pl"; 1275 status = "disabled"; 1276 reg = <0x400 0x400>; 1277 }; 1278 }; 1279 1280 zynqmp_dpdma: dma-controller@fd4c0000 { 1281 compatible = "xlnx,zynqmp-dpdma"; 1282 status = "disabled"; 1283 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1284 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1285 interrupt-parent = <&gic>; 1286 clock-names = "axi_clk"; 1287 power-domains = <&zynqmp_firmware PD_DP>; 1288 /* iommus = <&smmu 0xce4>; */ 1289 #dma-cells = <1>; 1290 }; 1291 1292 zynqmp_dpsub: display@fd4a0000 { 1293 bootph-all; 1294 compatible = "xlnx,zynqmp-dpsub-1.7"; 1295 status = "disabled"; 1296 reg = <0x0 0xfd4a0000 0x0 0x1000>, 1297 <0x0 0xfd4aa000 0x0 0x1000>, 1298 <0x0 0xfd4ab000 0x0 0x1000>, 1299 <0x0 0xfd4ac000 0x0 0x1000>; 1300 reg-names = "dp", "blend", "av_buf", "aud"; 1301 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1302 interrupt-parent = <&gic>; 1303 /* iommus = <&smmu 0xce3>; */ 1304 clock-names = "dp_apb_clk", "dp_aud_clk", 1305 "dp_vtc_pixel_clk_in"; 1306 power-domains = <&zynqmp_firmware PD_DP>; 1307 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 1308 dma-names = "vid0", "vid1", "vid2", "gfx0", 1309 "aud0", "aud1"; 1310 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 1311 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 1312 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 1313 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>, 1314 <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>, 1315 <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>; 1316 1317 ports { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 1321 live_video: port@0 { 1322 reg = <0>; 1323 }; 1324 live_gfx: port@1 { 1325 reg = <1>; 1326 }; 1327 live_audio: port@2 { 1328 reg = <2>; 1329 }; 1330 out_video: port@3 { 1331 reg = <3>; 1332 }; 1333 out_audio: port@4 { 1334 reg = <4>; 1335 }; 1336 out_dp: port@5 { 1337 reg = <5>; 1338 }; 1339 }; 1340 }; 1341 }; 1342};
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