zynqmp-sck-kv-g-revB.dtso

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dts file for KV260 revA Carrier Card
  4 *
  5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
  6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  7 *
  8 * Michal Simek <michal.simek@amd.com>
  9 */
 10
 11#include <dt-bindings/gpio/gpio.h>
 12#include <dt-bindings/net/ti-dp83867.h>
 13#include <dt-bindings/phy/phy.h>
 14#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 15
 16/dts-v1/;
 17/plugin/;
 18
 19&{/} {
 20	compatible = "xlnx,zynqmp-sk-kv260-rev2",
 21		     "xlnx,zynqmp-sk-kv260-rev1",
 22		     "xlnx,zynqmp-sk-kv260-revB",
 23		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
 24	model = "ZynqMP KV260 revB";
 25
 26	aliases {
 27		ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
 28	};
 29
 30	ina260-u14 {
 31		compatible = "iio-hwmon";
 32		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 33	};
 34
 35	si5332_0: si5332-0 { /* u17 */
 36		compatible = "fixed-clock";
 37		#clock-cells = <0>;
 38		clock-frequency = <125000000>;
 39	};
 40
 41	si5332_1: si5332-1 { /* u17 */
 42		compatible = "fixed-clock";
 43		#clock-cells = <0>;
 44		clock-frequency = <25000000>;
 45	};
 46
 47	si5332_2: si5332-2 { /* u17 */
 48		compatible = "fixed-clock";
 49		#clock-cells = <0>;
 50		clock-frequency = <48000000>;
 51	};
 52
 53	si5332_3: si5332-3 { /* u17 */
 54		compatible = "fixed-clock";
 55		#clock-cells = <0>;
 56		clock-frequency = <24000000>;
 57	};
 58
 59	si5332_4: si5332-4 { /* u17 */
 60		compatible = "fixed-clock";
 61		#clock-cells = <0>;
 62		clock-frequency = <26000000>;
 63	};
 64
 65	si5332_5: si5332-5 { /* u17 */
 66		compatible = "fixed-clock";
 67		#clock-cells = <0>;
 68		clock-frequency = <27000000>;
 69	};
 70
 71	dpcon {
 72		compatible = "dp-connector";
 73		label = "P11";
 74		type = "full-size";
 75
 76		port {
 77			dpcon_in: endpoint {
 78				remote-endpoint = <&dpsub_dp_out>;
 79			};
 80		};
 81	};
 82};
 83
 84&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
 85	#address-cells = <1>;
 86	#size-cells = <0>;
 87	pinctrl-names = "default", "gpio";
 88	pinctrl-0 = <&pinctrl_i2c1_default>;
 89	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 90	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 91	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 92
 93	u14: ina260@40 { /* u14 */
 94		compatible = "ti,ina260";
 95		#io-channel-cells = <1>;
 96		label = "ina260-u14";
 97		reg = <0x40>;
 98	};
 99	hub: usb-hub@2d {
100		compatible = "microchip,usb5744";
101		reg = <0x2d>;
102	};
103	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
104};
105
106/* DP/USB 3.0 */
107&psgtr {
108	status = "okay";
109	/* pcie, usb3, sata */
110	clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
111	clock-names = "ref0", "ref1", "ref2";
112};
113
114&zynqmp_dpsub {
115	status = "okay";
116	phy-names = "dp-phy0", "dp-phy1";
117	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
118	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
119};
120
121&out_dp {
122	dpsub_dp_out: endpoint {
123		remote-endpoint = <&dpcon_in>;
124	};
125};
126
127&zynqmp_dpdma {
128	status = "okay";
129	assigned-clock-rates = <600000000>;
130};
131
132&usb0 {
133	status = "okay";
134	pinctrl-names = "default";
135	pinctrl-0 = <&pinctrl_usb0_default>;
136	phy-names = "usb3-phy";
137	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
138	assigned-clock-rates = <250000000>, <20000000>;
139};
140
141&dwc3_0 {
142	status = "okay";
143	dr_mode = "host";
144	snps,usb3_lpm_capable;
145	maximum-speed = "super-speed";
146	#address-cells = <1>;
147	#size-cells = <0>;
148
149	/* 2.0 hub on port 1 */
150	hub_2_0: hub@1 {
151		compatible = "usb424,2744";
152		reg = <1>;
153		peer-hub = <&hub_3_0>;
154		i2c-bus = <&hub>;
155		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
156	};
157
158	/* 3.0 hub on port 2 */
159	hub_3_0: hub@2 {
160		compatible = "usb424,5744";
161		reg = <2>;
162		peer-hub = <&hub_2_0>;
163		i2c-bus = <&hub>;
164		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
165	};
166};
167
168&sdhci1 { /* on CC with tuned parameters */
169	status = "okay";
170	pinctrl-names = "default";
171	pinctrl-0 = <&pinctrl_sdhci1_default>;
172	/*
173	 * SD 3.0 requires level shifter and this property
174	 * should be removed if the board has level shifter and
175	 * need to work in UHS mode
176	 */
177	no-1-8-v;
178	disable-wp;
179	xlnx,mio-bank = <1>;
180	clk-phase-sd-hs = <126>, <60>;
181	clk-phase-uhs-sdr25 = <120>, <60>;
182	clk-phase-uhs-ddr50 = <126>, <48>;
183	assigned-clock-rates = <187498123>;
184	bus-width = <4>;
185};
186
187&gem3 {
188	status = "okay";
189	pinctrl-names = "default";
190	pinctrl-0 = <&pinctrl_gem3_default>;
191	phy-handle = <&phy0>;
192	phy-mode = "rgmii-id";
193	assigned-clock-rates = <250000000>;
194
195	mdio: mdio {
196		#address-cells = <1>;
197		#size-cells = <0>;
198
199		phy0: ethernet-phy@1 {
200			#phy-cells = <1>;
201			reg = <1>;
202			compatible = "ethernet-phy-id2000.a231";
203			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
204			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
205			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
206			ti,dp83867-rxctrl-strap-quirk;
207			reset-assert-us = <100>;
208			reset-deassert-us = <280>;
209			reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
210		};
211	};
212};
213
214&pinctrl0 {
215	status = "okay";
216
217	pinctrl_gpio0_default: gpio0-default {
218		conf {
219			groups = "gpio0_38_grp";
220			bias-pull-up;
221			power-source = <IO_STANDARD_LVCMOS18>;
222		};
223
224		mux {
225			groups = "gpio0_38_grp";
226			function = "gpio0";
227		};
228
229		conf-tx {
230			pins = "MIO38";
231			bias-disable;
232			output-enable;
233		};
234	};
235
236	pinctrl_uart1_default: uart1-default {
237		conf {
238			groups = "uart1_9_grp";
239			slew-rate = <SLEW_RATE_SLOW>;
240			power-source = <IO_STANDARD_LVCMOS18>;
241			drive-strength = <12>;
242		};
243
244		conf-rx {
245			pins = "MIO37";
246			bias-high-impedance;
247		};
248
249		conf-tx {
250			pins = "MIO36";
251			bias-disable;
252			output-enable;
253		};
254
255		mux {
256			groups = "uart1_9_grp";
257			function = "uart1";
258		};
259	};
260
261	pinctrl_i2c1_default: i2c1-default {
262		conf {
263			groups = "i2c1_6_grp";
264			bias-pull-up;
265			slew-rate = <SLEW_RATE_SLOW>;
266			power-source = <IO_STANDARD_LVCMOS18>;
267		};
268
269		mux {
270			groups = "i2c1_6_grp";
271			function = "i2c1";
272		};
273	};
274
275	pinctrl_i2c1_gpio: i2c1-gpio-grp {
276		conf {
277			groups = "gpio0_24_grp", "gpio0_25_grp";
278			slew-rate = <SLEW_RATE_SLOW>;
279			power-source = <IO_STANDARD_LVCMOS18>;
280		};
281
282		mux {
283			groups = "gpio0_24_grp", "gpio0_25_grp";
284			function = "gpio0";
285		};
286	};
287
288	pinctrl_gem3_default: gem3-default {
289		conf {
290			groups = "ethernet3_0_grp";
291			slew-rate = <SLEW_RATE_SLOW>;
292			power-source = <IO_STANDARD_LVCMOS18>;
293		};
294
295		conf-rx {
296			pins = "MIO70", "MIO72", "MIO74";
297			bias-high-impedance;
298			low-power-disable;
299		};
300
301		conf-bootstrap {
302			pins = "MIO71", "MIO73", "MIO75";
303			bias-disable;
304			output-enable;
305			low-power-disable;
306		};
307
308		conf-tx {
309			pins = "MIO64", "MIO65", "MIO66",
310				"MIO67", "MIO68", "MIO69";
311			bias-disable;
312			output-enable;
313			low-power-enable;
314		};
315
316		conf-mdio {
317			groups = "mdio3_0_grp";
318			slew-rate = <SLEW_RATE_SLOW>;
319			power-source = <IO_STANDARD_LVCMOS18>;
320			bias-disable;
321			output-enable;
322		};
323
324		mux-mdio {
325			function = "mdio3";
326			groups = "mdio3_0_grp";
327		};
328
329		mux {
330			function = "ethernet3";
331			groups = "ethernet3_0_grp";
332		};
333	};
334
335	pinctrl_usb0_default: usb0-default {
336		conf {
337			groups = "usb0_0_grp";
338			power-source = <IO_STANDARD_LVCMOS18>;
339		};
340
341		conf-rx {
342			pins = "MIO52", "MIO53", "MIO55";
343			bias-high-impedance;
344			drive-strength = <12>;
345			slew-rate = <SLEW_RATE_FAST>;
346		};
347
348		conf-tx {
349			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
350			"MIO60", "MIO61", "MIO62", "MIO63";
351			bias-disable;
352			output-enable;
353			drive-strength = <4>;
354			slew-rate = <SLEW_RATE_SLOW>;
355		};
356
357		mux {
358			groups = "usb0_0_grp";
359			function = "usb0";
360		};
361	};
362
363	pinctrl_sdhci1_default: sdhci1-default {
364		conf {
365			groups = "sdio1_0_grp";
366			slew-rate = <SLEW_RATE_SLOW>;
367			power-source = <IO_STANDARD_LVCMOS18>;
368			bias-disable;
369			output-enable;
370		};
371
372		conf-cd {
373			groups = "sdio1_cd_0_grp";
374			bias-high-impedance;
375			bias-pull-up;
376			slew-rate = <SLEW_RATE_SLOW>;
377			power-source = <IO_STANDARD_LVCMOS18>;
378		};
379
380		mux-cd {
381			groups = "sdio1_cd_0_grp";
382			function = "sdio1_cd";
383		};
384
385		mux {
386			groups = "sdio1_0_grp";
387			function = "sdio1";
388		};
389	};
390};
391
392&gpio {
393	status = "okay";
394	pinctrl-names = "default";
395	pinctrl-0 = <&pinctrl_gpio0_default>;
396};
397
398&uart1 {
399	status = "okay";
400	pinctrl-names = "default";
401	pinctrl-0 = <&pinctrl_uart1_default>;
402};