zynqmp-sck-kv-g-revA.dtso

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dts file for KV260 revA Carrier Card
  4 *
  5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
  6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  7 *
  8 * SD level shifter:
  9 * "A" - A01 board un-modified (NXP)
 10 * "Y" - A01 board modified with legacy interposer (Nexperia)
 11 * "Z" - A01 board modified with Diode interposer
 12 *
 13 * Michal Simek <michal.simek@amd.com>
 14 */
 15
 16#include <dt-bindings/gpio/gpio.h>
 17#include <dt-bindings/net/ti-dp83867.h>
 18#include <dt-bindings/phy/phy.h>
 19#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 20
 21/dts-v1/;
 22/plugin/;
 23
 24&{/} {
 25	compatible = "xlnx,zynqmp-sk-kv260-revA",
 26		     "xlnx,zynqmp-sk-kv260-revY",
 27		     "xlnx,zynqmp-sk-kv260-revZ",
 28		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
 29	model = "ZynqMP KV260 revA";
 30
 31	aliases {
 32		ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
 33	};
 34
 35	ina260-u14 {
 36		compatible = "iio-hwmon";
 37		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 38	};
 39
 40	si5332_0: si5332-0 { /* u17 */
 41		compatible = "fixed-clock";
 42		#clock-cells = <0>;
 43		clock-frequency = <125000000>;
 44	};
 45
 46	si5332_1: si5332-1 { /* u17 */
 47		compatible = "fixed-clock";
 48		#clock-cells = <0>;
 49		clock-frequency = <25000000>;
 50	};
 51
 52	si5332_2: si5332-2 { /* u17 */
 53		compatible = "fixed-clock";
 54		#clock-cells = <0>;
 55		clock-frequency = <48000000>;
 56	};
 57
 58	si5332_3: si5332-3 { /* u17 */
 59		compatible = "fixed-clock";
 60		#clock-cells = <0>;
 61		clock-frequency = <24000000>;
 62	};
 63
 64	si5332_4: si5332-4 { /* u17 */
 65		compatible = "fixed-clock";
 66		#clock-cells = <0>;
 67		clock-frequency = <26000000>;
 68	};
 69
 70	si5332_5: si5332-5 { /* u17 */
 71		compatible = "fixed-clock";
 72		#clock-cells = <0>;
 73		clock-frequency = <27000000>;
 74	};
 75	dpcon {
 76		compatible = "dp-connector";
 77		label = "P11";
 78		type = "full-size";
 79
 80		port {
 81			dpcon_in: endpoint {
 82				remote-endpoint = <&dpsub_dp_out>;
 83			};
 84		};
 85	};
 86};
 87
 88&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
 89	#address-cells = <1>;
 90	#size-cells = <0>;
 91	pinctrl-names = "default", "gpio";
 92	pinctrl-0 = <&pinctrl_i2c1_default>;
 93	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 94	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 95	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 96
 97	u14: ina260@40 { /* u14 */
 98		compatible = "ti,ina260";
 99		#io-channel-cells = <1>;
100		label = "ina260-u14";
101		reg = <0x40>;
102	};
103	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
104};
105
106/* DP/USB 3.0 and SATA */
107&psgtr {
108	status = "okay";
109	/* pcie, usb3, sata */
110	clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
111	clock-names = "ref0", "ref1", "ref2";
112};
113
114&sata {
115	status = "okay";
116	/* SATA OOB timing settings */
117	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
118	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
119	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
120	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
121	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
122	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
123	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
124	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
125	phy-names = "sata-phy";
126	phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
127};
128
129&zynqmp_dpsub {
130	status = "okay";
131	phy-names = "dp-phy0", "dp-phy1";
132	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
133	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
134};
135
136&out_dp {
137	dpsub_dp_out: endpoint {
138		remote-endpoint = <&dpcon_in>;
139	};
140};
141
142&zynqmp_dpdma {
143	status = "okay";
144	assigned-clock-rates = <600000000>;
145};
146
147&usb0 {
148	status = "okay";
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_usb0_default>;
151	phy-names = "usb3-phy";
152	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
153};
154
155&dwc3_0 {
156	status = "okay";
157	dr_mode = "host";
158	snps,usb3_lpm_capable;
159	maximum-speed = "super-speed";
160	#address-cells = <1>;
161	#size-cells = <0>;
162
163	/* 2.0 hub on port 1 */
164	hub_2_0: hub@1 {
165		compatible = "usb424,2744";
166		reg = <1>;
167		peer-hub = <&hub_3_0>;
168		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
169	};
170
171	/* 3.0 hub on port 2 */
172	hub_3_0: hub@2 {
173		compatible = "usb424,5744";
174		reg = <2>;
175		peer-hub = <&hub_2_0>;
176		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
177	};
178};
179
180&sdhci1 { /* on CC with tuned parameters */
181	status = "okay";
182	pinctrl-names = "default";
183	pinctrl-0 = <&pinctrl_sdhci1_default>;
184	/*
185	 * SD 3.0 requires level shifter and this property
186	 * should be removed if the board has level shifter and
187	 * need to work in UHS mode
188	 */
189	no-1-8-v;
190	disable-wp;
191	xlnx,mio-bank = <1>;
192	assigned-clock-rates = <187498123>;
193	bus-width = <4>;
194};
195
196&gem3 {
197	status = "okay";
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_gem3_default>;
200	phy-handle = <&phy0>;
201	phy-mode = "rgmii-id";
202	assigned-clock-rates = <250000000>;
203
204	mdio: mdio {
205		#address-cells = <1>;
206		#size-cells = <0>;
207
208		phy0: ethernet-phy@1 {
209			#phy-cells = <1>;
210			reg = <1>;
211			compatible = "ethernet-phy-id2000.a231";
212			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
213			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
214			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
215			ti,dp83867-rxctrl-strap-quirk;
216			reset-assert-us = <100>;
217			reset-deassert-us = <280>;
218			reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
219		};
220	};
221};
222
223&pinctrl0 {
224	status = "okay";
225
226	pinctrl_gpio0_default: gpio0-default {
227                conf {
228                        groups = "gpio0_38_grp";
229                        bias-pull-up;
230                        power-source = <IO_STANDARD_LVCMOS18>;
231                };
232
233                mux {
234                        groups = "gpio0_38_grp";
235                        function = "gpio0";
236                };
237
238                conf-tx {
239                        pins = "MIO38";
240                        bias-disable;
241                        output-enable;
242                };
243        };
244
245	pinctrl_uart1_default: uart1-default {
246		conf {
247			groups = "uart1_9_grp";
248			slew-rate = <SLEW_RATE_SLOW>;
249			power-source = <IO_STANDARD_LVCMOS18>;
250			drive-strength = <12>;
251		};
252
253		conf-rx {
254			pins = "MIO37";
255			bias-high-impedance;
256		};
257
258		conf-tx {
259			pins = "MIO36";
260			bias-disable;
261			output-enable;
262		};
263
264		mux {
265			groups = "uart1_9_grp";
266			function = "uart1";
267		};
268	};
269
270	pinctrl_i2c1_default: i2c1-default {
271		conf {
272			groups = "i2c1_6_grp";
273			bias-pull-up;
274			slew-rate = <SLEW_RATE_SLOW>;
275			power-source = <IO_STANDARD_LVCMOS18>;
276		};
277
278		mux {
279			groups = "i2c1_6_grp";
280			function = "i2c1";
281		};
282	};
283
284	pinctrl_i2c1_gpio: i2c1-gpio-grp {
285		conf {
286			groups = "gpio0_24_grp", "gpio0_25_grp";
287			slew-rate = <SLEW_RATE_SLOW>;
288			power-source = <IO_STANDARD_LVCMOS18>;
289		};
290
291		mux {
292			groups = "gpio0_24_grp", "gpio0_25_grp";
293			function = "gpio0";
294		};
295	};
296
297	pinctrl_gem3_default: gem3-default {
298		conf {
299			groups = "ethernet3_0_grp";
300			slew-rate = <SLEW_RATE_SLOW>;
301			power-source = <IO_STANDARD_LVCMOS18>;
302		};
303
304		conf-rx {
305			pins = "MIO70", "MIO72", "MIO74";
306			bias-high-impedance;
307			low-power-disable;
308		};
309
310		conf-bootstrap {
311			pins = "MIO71", "MIO73", "MIO75";
312			bias-disable;
313			output-enable;
314			low-power-disable;
315		};
316
317		conf-tx {
318			pins = "MIO64", "MIO65", "MIO66",
319				"MIO67", "MIO68", "MIO69";
320			bias-disable;
321			output-enable;
322			low-power-enable;
323		};
324
325		conf-mdio {
326			groups = "mdio3_0_grp";
327			slew-rate = <SLEW_RATE_SLOW>;
328			power-source = <IO_STANDARD_LVCMOS18>;
329			bias-disable;
330			output-enable;
331		};
332
333		mux-mdio {
334			function = "mdio3";
335			groups = "mdio3_0_grp";
336		};
337
338		mux {
339			function = "ethernet3";
340			groups = "ethernet3_0_grp";
341		};
342	};
343
344	pinctrl_usb0_default: usb0-default {
345		conf {
346			groups = "usb0_0_grp";
347			power-source = <IO_STANDARD_LVCMOS18>;
348		};
349
350		conf-rx {
351			pins = "MIO52", "MIO53", "MIO55";
352			bias-high-impedance;
353			drive-strength = <12>;
354			slew-rate = <SLEW_RATE_FAST>;
355		};
356
357		conf-tx {
358			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
359			"MIO60", "MIO61", "MIO62", "MIO63";
360			bias-disable;
361			output-enable;
362			drive-strength = <4>;
363			slew-rate = <SLEW_RATE_SLOW>;
364		};
365
366		mux {
367			groups = "usb0_0_grp";
368			function = "usb0";
369		};
370	};
371
372	pinctrl_sdhci1_default: sdhci1-default {
373		conf {
374			groups = "sdio1_0_grp";
375			slew-rate = <SLEW_RATE_SLOW>;
376			power-source = <IO_STANDARD_LVCMOS18>;
377			bias-disable;
378			output-enable;
379		};
380
381		conf-cd {
382			groups = "sdio1_cd_0_grp";
383			bias-high-impedance;
384			bias-pull-up;
385			slew-rate = <SLEW_RATE_SLOW>;
386			power-source = <IO_STANDARD_LVCMOS18>;
387		};
388
389		mux-cd {
390			groups = "sdio1_cd_0_grp";
391			function = "sdio1_cd";
392		};
393
394		mux {
395			groups = "sdio1_0_grp";
396			function = "sdio1";
397		};
398	};
399};
400
401&gpio {
402        status = "okay";
403        pinctrl-names = "default";
404        pinctrl-0 = <&pinctrl_gpio0_default>;
405};
406
407&uart1 {
408	status = "okay";
409	pinctrl-names = "default";
410	pinctrl-0 = <&pinctrl_uart1_default>;
411};