zynqmp-sck-kr-g-revB.dtso

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dts file for KR260 revB Carrier Card (A03 revision)
  4 *
  5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
  6 *
  7 * Michal Simek <michal.simek@amd.com>
  8 */
  9
 10#include <dt-bindings/gpio/gpio.h>
 11#include <dt-bindings/net/ti-dp83867.h>
 12#include <dt-bindings/phy/phy.h>
 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 14
 15/dts-v1/;
 16/plugin/;
 17
 18&{/} {
 19	compatible = "xlnx,zynqmp-sk-kr260-revB",
 20		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
 21	model = "ZynqMP KR260 revB";
 22
 23	aliases {
 24		ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
 25		ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
 26	};
 27
 28	ina260-u14 {
 29		compatible = "iio-hwmon";
 30		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 31	};
 32
 33	clk_125: clock0 { /* u87 - GEM0/1 */
 34		compatible = "fixed-clock";
 35		#clock-cells = <0>;
 36		clock-frequency = <125000000>;
 37	};
 38
 39	clk_27: clock1 { /* u86 - DP */
 40		compatible = "fixed-clock";
 41		#clock-cells = <0>;
 42		clock-frequency = <27000000>;
 43	};
 44
 45	clk_26: clock2 { /* u89 - USB */
 46		compatible = "fixed-clock";
 47		#clock-cells = <0>;
 48		clock-frequency = <26000000>;
 49	};
 50
 51	clk_156: clock3 { /* u90 - SFP+ */
 52		compatible = "fixed-clock";
 53		#clock-cells = <0>;
 54		clock-frequency = <156250000>;
 55	};
 56
 57	clk_25_0: clock4 { /* u92/u91 - GEM2 */
 58		compatible = "fixed-clock";
 59		#clock-cells = <0>;
 60		clock-frequency = <25000000>;
 61	};
 62
 63	clk_25_1: clock5 { /* u92/u91 - GEM3 */
 64		compatible = "fixed-clock";
 65		#clock-cells = <0>;
 66		clock-frequency = <25000000>;
 67	};
 68
 69	clk_74: clock6 { /* u88 - SLVC-EC */
 70		compatible = "fixed-clock";
 71		#clock-cells = <0>;
 72		clock-frequency = <74250000>;
 73	};
 74
 75	dpcon {
 76		compatible = "dp-connector";
 77		label = "P11";
 78		type = "full-size";
 79
 80		port {
 81			dpcon_in: endpoint {
 82				remote-endpoint = <&dpsub_dp_out>;
 83			};
 84		};
 85	};
 86};
 87
 88&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
 89	#address-cells = <1>;
 90	#size-cells = <0>;
 91	pinctrl-names = "default", "gpio";
 92	pinctrl-0 = <&pinctrl_i2c1_default>;
 93	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 94	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 95	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 96
 97	u14: ina260@40 { /* u14 */
 98		compatible = "ti,ina260";
 99		#io-channel-cells = <1>;
100		label = "ina260-u14";
101		reg = <0x40>;
102	};
103
104	slg7xl45106: gpio@11 { /* u19 - reset logic */
105		compatible = "dlg,slg7xl45106";
106		reg = <0x11>;
107		label = "resetchip";
108		gpio-controller;
109		#gpio-cells = <2>;
110		gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
111				  "SD_RESET_B", "USB0_HUB_RESET_B",
112				  "USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
113				  "PS_GEM1_RESET_B", "";
114	};
115
116	i2c-mux@74 { /* u18 */
117		compatible = "nxp,pca9546";
118		#address-cells = <1>;
119		#size-cells = <0>;
120		reg = <0x74>;
121		usbhub_i2c0: i2c@0 {
122			#address-cells = <1>;
123			#size-cells = <0>;
124			reg = <0>;
125			hub_1: usb-hub@2d {
126				compatible = "microchip,usb5744";
127				reg = <0x2d>;
128			};
129		};
130		usbhub_i2c1: i2c@1 {
131			#address-cells = <1>;
132			#size-cells = <0>;
133			reg = <1>;
134			hub_2: usb-hub@2d {
135				compatible = "microchip,usb5744";
136				reg = <0x2d>;
137			};
138		};
139		/* Bus 2/3 are not connected */
140	};
141
142	/* si5332@6a - u17 - clock-generator */
143};
144
145/* GEM SGMII/DP and USB 3.0 */
146&psgtr {
147	status = "okay";
148	/* gem0/1, dp, usb */
149	clocks = <&clk_125>, <&clk_27>, <&clk_26>;
150	clock-names = "ref0", "ref1", "ref2";
151};
152
153&zynqmp_dpsub {
154	status = "okay";
155	phy-names = "dp-phy0";
156	phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
157	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
158};
159
160&out_dp {
161	dpsub_dp_out: endpoint {
162		remote-endpoint = <&dpcon_in>;
163	};
164};
165
166&zynqmp_dpdma {
167	status = "okay";
168	assigned-clock-rates = <600000000>;
169};
170
171&usb0 { /* mio52 - mio63 */
172	status = "okay";
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_usb0_default>;
175	phy-names = "usb3-phy";
176	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
177	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
178	assigned-clock-rates = <250000000>, <20000000>;
179};
180
181&dwc3_0 {
182	status = "okay";
183	dr_mode = "host";
184	snps,usb3_lpm_capable;
185	maximum-speed = "super-speed";
186	#address-cells = <1>;
187	#size-cells = <0>;
188
189	/* 2.0 hub on port 1 */
190	hub_2_0: hub@1 {
191		compatible = "usb424,2744";
192		reg = <1>;
193		peer-hub = <&hub_3_0>;
194		i2c-bus = <&hub_1>;
195		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
196	};
197
198	/* 3.0 hub on port 2 */
199	hub_3_0: hub@2 {
200		compatible = "usb424,5744";
201		reg = <2>;
202		peer-hub = <&hub_2_0>;
203		i2c-bus = <&hub_1>;
204		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
205	};
206};
207
208&usb1 { /* mio64 - mio75 */
209	status = "okay";
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_usb1_default>;
212	phy-names = "usb3-phy";
213	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
214	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
215	assigned-clock-rates = <250000000>, <20000000>;
216};
217
218&dwc3_1 {
219	status = "okay";
220	dr_mode = "host";
221	snps,usb3_lpm_capable;
222	maximum-speed = "super-speed";
223	#address-cells = <1>;
224	#size-cells = <0>;
225
226	/* 2.0 hub on port 1 */
227	hub1_2_0: hub@1 {
228		compatible = "usb424,2744";
229		reg = <1>;
230		peer-hub = <&hub1_3_0>;
231		i2c-bus = <&hub_2>;
232		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
233	};
234
235	/* 3.0 hub on port 2 */
236	hub1_3_0: hub@2 {
237		compatible = "usb424,5744";
238		reg = <2>;
239		peer-hub = <&hub1_2_0>;
240		i2c-bus = <&hub_2>;
241		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
242	};
243};
244
245&gem0 { /* mdio mio50/51 */
246	status = "okay";
247	phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
248	phy-handle = <&phy0>;
249	phy-mode = "sgmii";
250	assigned-clock-rates = <250000000>;
251};
252
253&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
254	status = "okay";
255	pinctrl-names = "default";
256	pinctrl-0 = <&pinctrl_gem1_default>;
257	phy-handle = <&phy1>;
258	phy-mode = "rgmii-id";
259	assigned-clock-rates = <250000000>;
260
261	mdio: mdio {
262		#address-cells = <1>;
263		#size-cells = <0>;
264		phy0: ethernet-phy@4 { /* u81 */
265			#phy-cells = <1>;
266			compatible = "ethernet-phy-id2000.a231";
267			reg = <4>;
268			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
269			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
270			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
271			ti,dp83867-rxctrl-strap-quirk;
272			reset-assert-us = <300>;
273			reset-deassert-us = <280>;
274			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
275		};
276		phy1: ethernet-phy@8 { /* u36 */
277			#phy-cells = <1>;
278			compatible = "ethernet-phy-id2000.a231";
279			reg = <8>;
280			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
281			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
282			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
283			ti,dp83867-rxctrl-strap-quirk;
284			reset-assert-us = <100>;
285			reset-deassert-us = <280>;
286			reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
287		};
288	};
289};
290
291/* gem2/gem3 via PL with phys u79@2 and u80@3 */
292
293&pinctrl0 {
294	status = "okay";
295
296	pinctrl_uart1_default: uart1-default {
297		conf {
298			groups = "uart1_9_grp";
299			slew-rate = <SLEW_RATE_SLOW>;
300			power-source = <IO_STANDARD_LVCMOS18>;
301			drive-strength = <12>;
302		};
303
304		conf-rx {
305			pins = "MIO37";
306			bias-high-impedance;
307		};
308
309		conf-tx {
310			pins = "MIO36";
311			bias-disable;
312			output-enable;
313		};
314
315		mux {
316			groups = "uart1_9_grp";
317			function = "uart1";
318		};
319	};
320
321	pinctrl_i2c1_default: i2c1-default {
322		conf {
323			groups = "i2c1_6_grp";
324			bias-pull-up;
325			slew-rate = <SLEW_RATE_SLOW>;
326			power-source = <IO_STANDARD_LVCMOS18>;
327		};
328
329		mux {
330			groups = "i2c1_6_grp";
331			function = "i2c1";
332		};
333	};
334
335	pinctrl_i2c1_gpio: i2c1-gpio-grp {
336		conf {
337			groups = "gpio0_24_grp", "gpio0_25_grp";
338			slew-rate = <SLEW_RATE_SLOW>;
339			power-source = <IO_STANDARD_LVCMOS18>;
340		};
341
342		mux {
343			groups = "gpio0_24_grp", "gpio0_25_grp";
344			function = "gpio0";
345		};
346	};
347
348	pinctrl_gem1_default: gem1-default {
349		conf {
350			groups = "ethernet1_0_grp";
351			slew-rate = <SLEW_RATE_SLOW>;
352			power-source = <IO_STANDARD_LVCMOS18>;
353		};
354
355		conf-rx {
356			pins = "MIO44", "MIO46", "MIO48";
357			bias-high-impedance;
358			low-power-disable;
359		};
360
361		conf-bootstrap {
362			pins = "MIO45", "MIO47", "MIO49";
363			bias-disable;
364			output-enable;
365			low-power-disable;
366		};
367
368		conf-tx {
369			pins = "MIO38", "MIO39", "MIO40",
370				"MIO41", "MIO42", "MIO43";
371			bias-disable;
372			output-enable;
373			low-power-enable;
374		};
375
376		conf-mdio {
377			groups = "mdio1_0_grp";
378			slew-rate = <SLEW_RATE_SLOW>;
379			power-source = <IO_STANDARD_LVCMOS18>;
380			bias-disable;
381			output-enable;
382		};
383
384		mux-mdio {
385			function = "mdio1";
386			groups = "mdio1_0_grp";
387		};
388
389		mux {
390			function = "ethernet1";
391			groups = "ethernet1_0_grp";
392		};
393	};
394
395	pinctrl_usb0_default: usb0-default {
396		conf {
397			groups = "usb0_0_grp";
398			power-source = <IO_STANDARD_LVCMOS18>;
399		};
400
401		conf-rx {
402			pins = "MIO52", "MIO53", "MIO55";
403			bias-high-impedance;
404			drive-strength = <12>;
405			slew-rate = <SLEW_RATE_FAST>;
406		};
407
408		conf-tx {
409			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
410			"MIO60", "MIO61", "MIO62", "MIO63";
411			bias-disable;
412			output-enable;
413			drive-strength = <4>;
414			slew-rate = <SLEW_RATE_SLOW>;
415		};
416
417		mux {
418			groups = "usb0_0_grp";
419			function = "usb0";
420		};
421	};
422
423	pinctrl_usb1_default: usb1-default {
424		conf {
425			groups = "usb1_0_grp";
426			power-source = <IO_STANDARD_LVCMOS18>;
427		};
428
429		conf-rx {
430			pins = "MIO64", "MIO65", "MIO67";
431			bias-high-impedance;
432			drive-strength = <12>;
433			slew-rate = <SLEW_RATE_FAST>;
434		};
435
436		conf-tx {
437			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
438			"MIO72", "MIO73", "MIO74", "MIO75";
439			bias-disable;
440			output-enable;
441			drive-strength = <4>;
442			slew-rate = <SLEW_RATE_SLOW>;
443		};
444
445		mux {
446			groups = "usb1_0_grp";
447			function = "usb1";
448		};
449	};
450};
451
452&uart1 {
453	status = "okay";
454	pinctrl-names = "default";
455	pinctrl-0 = <&pinctrl_uart1_default>;
456};